arch, cpu: Add support for flattening misc register indexes.

With ARMv8 support the same misc register id  results in accessing different
registers depending on the current mode of the processor. This patch adds
the same orthogonality to the misc register file as the others (int, float, cc).
For all the othre ISAs this is currently a null-implementation.

Additionally, a system variable is added to all the ISA objects.

src/arch/alpha/AlphaISA.py

@@ -35,9 +35,13 @@
 #
 # Authors: Andreas Sandberg
 
+from m5.params import *
+from m5.proxy import *
 from m5.SimObject import SimObject
 
 class AlphaISA(SimObject):
     type = 'AlphaISA'
     cxx_class = 'AlphaISA::ISA'
     cxx_header = "arch/alpha/isa.hh"
+
+    system = Param.System(Parent.any, "System this ISA object belongs to")

src/arch/alpha/isa.cc

@@ -40,7 +40,7 @@ namespace AlphaISA
 {
 
 ISA::ISA(Params *p)
-    : SimObject(p)
+    : SimObject(p), system(p->system)
 {
     clear();
     initializeIprTable();

src/arch/alpha/isa.hh

@@ -39,6 +39,7 @@
 #include "arch/alpha/types.hh"
 #include "base/types.hh"
 #include "sim/sim_object.hh"
+#include "sim/system.hh"
 
 struct AlphaISAParams;
 class BaseCPU;
@@ -55,6 +56,9 @@ namespace AlphaISA
         typedef AlphaISAParams Params;
 
       protected:
+        // Parent system
+        System *system;
+
         uint64_t fpcr;       // floating point condition codes
         uint64_t uniq;       // process-unique register
         bool lock_flag;      // lock flag for LL/SC
@@ -110,6 +114,12 @@ namespace AlphaISA
             return reg;
         }
 
+        int
+        flattenMiscIndex(int reg)
+        {
+            return reg;
+        }
+
         const Params *params() const;
 
         ISA(Params *p);

src/arch/mips/MipsISA.py

@@ -37,11 +37,14 @@
 
 from m5.SimObject import SimObject
 from m5.params import *
+from m5.proxy import *
 
 class MipsISA(SimObject):
     type = 'MipsISA'
     cxx_class = 'MipsISA::ISA'
     cxx_header = "arch/mips/isa.hh"
 
+    system = Param.System(Parent.any, "System this ISA object belongs to")
+
     num_threads = Param.UInt8(1, "Maximum number this ISA can handle")
     num_vpes = Param.UInt8(1, "Maximum number of vpes this ISA can handle")

src/arch/mips/isa.cc

@@ -89,8 +89,7 @@ ISA::miscRegNames[NumMiscRegs] =
 };
 
 ISA::ISA(Params *p)
-    : SimObject(p),
-      numThreads(p->num_threads), numVpes(p->num_vpes)
+    : SimObject(p), numThreads(p->num_threads), numVpes(p->num_vpes)
 {
     miscRegFile.resize(NumMiscRegs);
     bankType.resize(NumMiscRegs);

src/arch/mips/isa.hh

@@ -184,6 +184,13 @@ namespace MipsISA
         {
             return reg;
         }
+
+        int
+        flattenMiscIndex(int reg)
+        {
+            return reg;
+        }
+
     };
 }
 

src/arch/power/isa.hh

@@ -105,6 +105,12 @@ class ISA : public SimObject
         return reg;
     }
 
+    int
+    flattenMiscIndex(int reg)
+    {
+        return reg;
+    }
+
     void startup(ThreadContext *tc) {}
 
     /// Explicitly import the otherwise hidden startup

src/arch/sparc/isa.hh

@@ -177,7 +177,6 @@ class ISA : public SimObject
     using SimObject::startup;
 
   protected:
-
     bool isHyperPriv() { return hpstate.hpriv; }
     bool isPriv() { return hpstate.hpriv || pstate.priv; }
     bool isNonPriv() { return !isPriv(); }
@@ -213,6 +212,13 @@ class ISA : public SimObject
         return reg;
     }
 
+    int
+    flattenMiscIndex(int reg)
+    {
+        return reg;
+    }
+
+
     typedef SparcISAParams Params;
     const Params *params() const;
 

src/arch/x86/isa.hh

@@ -91,6 +91,12 @@ namespace X86ISA
             return reg;
         }
 
+        int
+        flattenMiscIndex(int reg)
+        {
+            return reg;
+        }
+
         void serialize(std::ostream &os);
         void unserialize(Checkpoint *cp, const std::string &section);
         void startup(ThreadContext *tc);

src/cpu/checker/thread_context.hh

@@ -300,6 +300,7 @@ class CheckerThreadContext : public ThreadContext
     int flattenIntIndex(int reg) { return actualTC->flattenIntIndex(reg); }
     int flattenFloatIndex(int reg) { return actualTC->flattenFloatIndex(reg); }
     int flattenCCIndex(int reg) { return actualTC->flattenCCIndex(reg); }
+    int flattenMiscIndex(int reg) { return actualTC->flattenMiscIndex(reg); }
 
     unsigned readStCondFailures()
     { return actualTC->readStCondFailures(); }

src/cpu/inorder/thread_context.hh

@@ -273,6 +273,9 @@ class InOrderThreadContext : public ThreadContext
     int flattenCCIndex(int reg)
     { return cpu->isa[thread->threadId()]->flattenCCIndex(reg); }
 
+    int flattenMiscIndex(int reg)
+    { return cpu->isa[thread->threadId()]->flattenMiscIndex(reg); }
+
     void activateContext(Cycles delay)
     { cpu->activateContext(thread->threadId(), delay); }
 

src/cpu/o3/thread_context.hh

@@ -244,6 +244,7 @@ class O3ThreadContext : public ThreadContext
     virtual int flattenIntIndex(int reg);
     virtual int flattenFloatIndex(int reg);
     virtual int flattenCCIndex(int reg);
+    virtual int flattenMiscIndex(int reg);
 
     /** Returns the number of consecutive store conditional failures. */
     // @todo: Figure out where these store cond failures should go.

src/cpu/o3/thread_context_impl.hh

@@ -291,6 +291,13 @@ O3ThreadContext<Impl>::flattenCCIndex(int reg)
     return cpu->isa[thread->threadId()]->flattenCCIndex(reg);
 }
 
+template <class Impl>
+int
+O3ThreadContext<Impl>::flattenMiscIndex(int reg)
+{
+    return cpu->isa[thread->threadId()]->flattenMiscIndex(reg);
+}
+
 template <class Impl>
 void
 O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)

src/cpu/simple_thread.hh

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011 ARM Limited
+ * Copyright (c) 2011-2012 ARM Limited
  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved
  *
@@ -415,6 +415,12 @@ class SimpleThread : public ThreadState
         return isa->flattenCCIndex(reg);
     }
 
+    int
+    flattenMiscIndex(int reg)
+    {
+        return isa->flattenMiscIndex(reg);
+    }
+
     unsigned readStCondFailures() { return storeCondFailures; }
 
     void setStCondFailures(unsigned sc_failures)

src/cpu/thread_context.hh

@@ -235,6 +235,7 @@ class ThreadContext
     virtual int flattenIntIndex(int reg) = 0;
     virtual int flattenFloatIndex(int reg) = 0;
     virtual int flattenCCIndex(int reg) = 0;
+    virtual int flattenMiscIndex(int reg) = 0;
 
     virtual uint64_t
     readRegOtherThread(int misc_reg, ThreadID tid)
@@ -451,6 +452,9 @@ class ProxyThreadContext : public ThreadContext
     int flattenCCIndex(int reg)
     { return actualTC->flattenCCIndex(reg); }
 
+    int flattenMiscIndex(int reg)
+    { return actualTC->flattenMiscIndex(reg); }
+
     unsigned readStCondFailures()
     { return actualTC->readStCondFailures(); }