diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py index c8efd9619..70b21980e 100644 --- a/configs/common/Simulation.py +++ b/configs/common/Simulation.py @@ -1,3 +1,15 @@ +# Copyright (c) 2012 ARM Limited +# All rights reserved +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# # Copyright (c) 2006-2008 The Regents of The University of Michigan # Copyright (c) 2010 Advanced Micro Devices, Inc. # All rights reserved. @@ -64,14 +76,11 @@ def setCPUClass(options): depending on the options provided. """ - if options.cpu_type == "detailed" or \ - options.cpu_type == "arm_detailed" or \ - options.cpu_type == "inorder" : - if not options.caches and not options.ruby: - fatal("O3/Inorder CPU must be used with caches") - TmpClass, test_mem_mode = getCPUClass(options.cpu_type) CPUClass = None + if TmpClass.require_caches() and \ + not options.caches and not options.ruby: + fatal("%s must be used with caches" % options.cpu_type) if options.checkpoint_restore != None: if options.restore_with_cpu != options.cpu_type: @@ -317,29 +326,17 @@ def run(options, root, testsys, cpu_class): switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] if options.repeat_switch: - if options.cpu_type == "arm_detailed": - if not options.caches: - print "O3 CPU must be used with caches" - sys.exit(1) - - repeat_switch_cpus = [O3_ARM_v7a_3(switched_out=True, \ - cpu_id=(i)) for i in xrange(np)] - elif options.cpu_type == "detailed": - if not options.caches: - print "O3 CPU must be used with caches" - sys.exit(1) - - repeat_switch_cpus = [DerivO3CPU(switched_out=True, \ - cpu_id=(i)) for i in xrange(np)] - elif options.cpu_type == "inorder": - print "inorder CPU switching not supported" + switch_class = getCPUClass(options.cpu_type)[0] + if switch_class.require_caches() and \ + not options.caches: + print "%s: Must be used with caches" % str(switch_class) sys.exit(1) - elif options.cpu_type == "timing": - repeat_switch_cpus = [TimingSimpleCPU(switched_out=True, \ - cpu_id=(i)) for i in xrange(np)] - else: - repeat_switch_cpus = [AtomicSimpleCPU(switched_out=True, \ - cpu_id=(i)) for i in xrange(np)] + if not switch_class.support_take_over(): + print "%s: CPU switching not supported" % str(switch_class) + sys.exit(1) + + repeat_switch_cpus = [switch_class(switched_out=True, \ + cpu_id=(i)) for i in xrange(np)] for i in xrange(np): repeat_switch_cpus[i].system = testsys diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 759bc0881..4fc2ebf1b 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -100,6 +100,25 @@ class BaseCPU(MemObject): void flushTLBs(); ''') + @classmethod + def memory_mode(cls): + """Which memory mode does this CPU require?""" + return 'invalid' + + @classmethod + def require_caches(cls): + """Does the CPU model require caches? + + Some CPU models might make assumptions that require them to + have caches. + """ + return False + + @classmethod + def support_take_over(cls): + """Does the CPU model support CPU takeOverFrom?""" + return False + def takeOverFrom(self, old_cpu): self._ccObject.takeOverFrom(old_cpu._ccObject) diff --git a/src/cpu/inorder/InOrderCPU.py b/src/cpu/inorder/InOrderCPU.py index 3285d50ce..e29a29556 100644 --- a/src/cpu/inorder/InOrderCPU.py +++ b/src/cpu/inorder/InOrderCPU.py @@ -39,6 +39,14 @@ class InOrderCPU(BaseCPU): cxx_header = "cpu/inorder/cpu.hh" activity = Param.Unsigned(0, "Initial count") + @classmethod + def memory_mode(cls): + return 'timing' + + @classmethod + def require_caches(cls): + return True + threadModel = Param.ThreadModel('SMT', "Multithreading model (SE-MODE only)") cachePorts = Param.Unsigned(2, "Cache Ports") diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py index 4f720a8f6..f46388b4c 100644 --- a/src/cpu/o3/O3CPU.py +++ b/src/cpu/o3/O3CPU.py @@ -38,6 +38,18 @@ class DerivO3CPU(BaseCPU): type = 'DerivO3CPU' cxx_header = 'cpu/o3/deriv.hh' + @classmethod + def memory_mode(cls): + return 'timing' + + @classmethod + def require_caches(cls): + return True + + @classmethod + def support_take_over(cls): + return True + activity = Param.Unsigned(0, "Initial count") cachePorts = Param.Unsigned(200, "Cache Ports") diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py index 1927a5862..c747582f6 100644 --- a/src/cpu/simple/AtomicSimpleCPU.py +++ b/src/cpu/simple/AtomicSimpleCPU.py @@ -42,8 +42,21 @@ from m5.params import * from BaseSimpleCPU import BaseSimpleCPU class AtomicSimpleCPU(BaseSimpleCPU): + """Simple CPU model executing a configurable number of + instructions per cycle. This model uses the simplified 'atomic' + memory mode.""" + type = 'AtomicSimpleCPU' cxx_header = "cpu/simple/atomic.hh" + + @classmethod + def memory_mode(cls): + return 'atomic' + + @classmethod + def support_take_over(cls): + return True + width = Param.Int(1, "CPU width") simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles") simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles") diff --git a/src/cpu/simple/TimingSimpleCPU.py b/src/cpu/simple/TimingSimpleCPU.py index 72560366e..25149eaa8 100644 --- a/src/cpu/simple/TimingSimpleCPU.py +++ b/src/cpu/simple/TimingSimpleCPU.py @@ -32,3 +32,11 @@ from BaseSimpleCPU import BaseSimpleCPU class TimingSimpleCPU(BaseSimpleCPU): type = 'TimingSimpleCPU' cxx_header = "cpu/simple/timing.hh" + + @classmethod + def memory_mode(cls): + return 'timing' + + @classmethod + def support_take_over(cls): + return True