Last minute check in. Very few functional changes other than some minor config updates. Also include some recently generated stats.
SConstruct:
Make test CPUs option non-sticky.
configs/common/FSConfig.py:
Be sure to set the memory mode.
configs/test/fs.py:
Wrong string.
tests/SConscript:
Only test valid CPUs that have been compiled in.
tests/test1/ref/alpha/atomic/config.ini:
tests/test1/ref/alpha/atomic/config.out:
tests/test1/ref/alpha/atomic/m5stats.txt:
tests/test1/ref/alpha/atomic/stdout:
tests/test1/ref/alpha/detailed/config.ini:
tests/test1/ref/alpha/detailed/config.out:
tests/test1/ref/alpha/detailed/m5stats.txt:
tests/test1/ref/alpha/detailed/stdout:
tests/test1/ref/alpha/timing/config.ini:
tests/test1/ref/alpha/timing/config.out:
tests/test1/ref/alpha/timing/m5stats.txt:
tests/test1/ref/alpha/timing/stdout:
Update output.
--HG--
extra : convert_revision : 6eee2a5eae0291b5121b41bcd7021179cdd520a3
This commit is contained in:
Kevin Lim
parent
db5f710a7b
commit
7ccdb7accc
16 changed files with 445 additions and 470 deletions
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@ -279,8 +279,6 @@ sticky_opts.AddOptions(
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# scons 0.96.90 or later.
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ListOption('CPU_MODELS', 'CPU models', 'AtomicSimpleCPU,TimingSimpleCPU',
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env['ALL_CPU_LIST']),
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ListOption('TEST_CPU_MODELS', 'CPU models to test if regression is being run', '',
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env['ALL_CPU_LIST']),
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BoolOption('ALPHA_TLASER',
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'Model Alpha TurboLaser platform (vs. Tsunami)', False),
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BoolOption('NO_FAST_ALLOC', 'Disable fast object allocator', False),
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@ -304,6 +302,8 @@ sticky_opts.AddOptions(
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# Non-sticky options only apply to the current build.
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nonsticky_opts = Options(args=ARGUMENTS)
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nonsticky_opts.AddOptions(
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ListOption('TEST_CPU_MODELS', 'CPU models to test if regression is being run', '',
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env['ALL_CPU_LIST']),
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BoolOption('update_ref', 'Update test reference outputs', False)
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)
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@ -74,7 +74,7 @@ def MyLinuxAlphaSystem(cpu, mem_mode, linux_image, icache=None, dcache=None, l2c
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read_only = True))
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self.intrctrl = IntrControl()
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self.cpu = cpu
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self.mem_mode = mem_mode
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connectCpu(self.cpu, self.membus, icache, dcache, l2cache)
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for each_cpu in listWrapper(self.cpu):
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each_cpu.itb = AlphaITB()
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@ -25,15 +25,15 @@ if args:
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if options.detailed:
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cpu = DetailedO3CPU()
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cpu2 = DetailedO3CPU()
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mem_mode = 'Timing'
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mem_mode = 'timing'
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elif options.timing:
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cpu = TimingSimpleCPU()
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cpu2 = TimingSimpleCPU()
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mem_mode = 'Timing'
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mem_mode = 'timing'
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else:
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cpu = AtomicSimpleCPU()
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cpu2 = AtomicSimpleCPU()
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mem_mode = 'Atomic'
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mem_mode = 'atomic'
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if options.dual:
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root = DualRoot(
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@ -155,14 +155,20 @@ def test_builder(env, category, cpu_list=[], os_list=[], refdir='ref',
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default_refdir = False
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if refdir == 'ref':
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default_refdir = True
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valid_cpu_list = []
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if len(cpu_list) == 0:
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cpu_list = env['CPU_MODELS']
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valid_cpu_list = env['CPU_MODELS']
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else:
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for i in cpu_list:
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if i in env['CPU_MODELS']:
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valid_cpu_list.append(i)
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cpu_list = valid_cpu_list
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if env['TEST_CPU_MODELS']:
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temp_cpu_list = []
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valid_cpu_list = []
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for i in env['TEST_CPU_MODELS']:
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if i in cpu_list:
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temp_cpu_list.append(i)
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cpu_list = temp_cpu_list
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valid_cpu_list.append(i)
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cpu_list = valid_cpu_list
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# Code commented out that shows the general structure if we want to test
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# different OS's as well.
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# if len(os_list) == 0:
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@ -48,11 +48,11 @@ text_file=m5stats.txt
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[system]
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type=System
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children=cpu0 physmem workload
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children=cpu physmem workload
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mem_mode=atomic
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physmem=system.physmem
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[system.cpu0]
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[system.cpu]
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type=AtomicSimpleCPU
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children=mem
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clock=1
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@ -63,13 +63,13 @@ max_insts_all_threads=0
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max_insts_any_thread=500000
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max_loads_all_threads=0
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max_loads_any_thread=0
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mem=system.cpu0.mem
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mem=system.cpu.mem
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simulate_stalls=false
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system=system
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width=1
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workload=system.workload
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[system.cpu0.mem]
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[system.cpu.mem]
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type=Bus
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bus_id=0
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@ -23,17 +23,17 @@ chkpt=
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output=cout
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system=system
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[system.cpu0.mem]
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[system.cpu.mem]
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type=Bus
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bus_id=0
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[system.cpu0]
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[system.cpu]
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type=AtomicSimpleCPU
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max_insts_any_thread=500000
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max_insts_all_threads=0
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max_loads_any_thread=0
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max_loads_all_threads=0
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mem=system.cpu0.mem
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mem=system.cpu.mem
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system=system
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workload=system.workload
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clock=1
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@ -1,18 +1,18 @@
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---------- Begin Simulation Statistics ----------
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host_inst_rate 1301768 # Simulator instruction rate (inst/s)
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host_mem_usage 147756 # Number of bytes of host memory used
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host_inst_rate 1310554 # Simulator instruction rate (inst/s)
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host_mem_usage 147620 # Number of bytes of host memory used
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host_seconds 0.38 # Real time elapsed on the host
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host_tick_rate 1300060 # Simulator tick rate (ticks/s)
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host_tick_rate 1308843 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 500000 # Number of instructions simulated
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sim_seconds 0.000000 # Number of seconds simulated
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sim_ticks 499999 # Number of ticks simulated
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system.cpu0.idle_fraction 0 # Percentage of idle cycles
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system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu0.numCycles 500000 # number of cpu cycles simulated
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system.cpu0.num_insts 500000 # Number of instructions executed
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system.cpu0.num_refs 182204 # Number of memory references
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.numCycles 500000 # number of cpu cycles simulated
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system.cpu.num_insts 500000 # Number of instructions executed
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system.cpu.num_refs 182204 # Number of memory references
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system.workload.PROG:num_syscalls 18 # Number of system calls
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---------- End Simulation Statistics ----------
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@ -7,8 +7,7 @@ The Regents of The University of Michigan
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All Rights Reserved
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M5 compiled Jul 19 2006 15:49:01
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M5 started Wed Jul 19 15:49:10 2006
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M5 compiled Jul 21 2006 16:19:30
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M5 started Fri Jul 21 16:40:43 2006
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M5 executing on zamp.eecs.umich.edu
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Creating SE system
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Exiting @ tick 499999 because a thread reached the max instruction count
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@ -48,13 +48,13 @@ text_file=m5stats.txt
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[system]
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type=System
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children=cpu0 physmem workload
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children=cpu physmem workload
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mem_mode=atomic
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physmem=system.physmem
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[system.cpu0]
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[system.cpu]
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type=DerivO3CPU
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children=checker fuPool mem
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children=fuPool mem
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BTBEntries=4096
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BTBTagSize=16
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LFSTSize=1024
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@ -64,7 +64,6 @@ SQEntries=32
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SSITSize=1024
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activity=0
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backComSize=5
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checker=system.cpu0.checker
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choiceCtrBits=2
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choicePredictorSize=8192
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clock=1
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@ -79,9 +78,10 @@ decodeWidth=8
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defer_registration=false
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dispatchWidth=8
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fetchToDecodeDelay=1
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fetchTrapLatency=1
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fetchWidth=8
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forwardComSize=5
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fuPool=system.cpu0.fuPool
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fuPool=system.cpu.fuPool
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function_trace=false
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function_trace_start=0
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globalCtrBits=2
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@ -102,11 +102,12 @@ max_insts_all_threads=0
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max_insts_any_thread=500000
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max_loads_all_threads=0
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max_loads_any_thread=0
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mem=system.cpu0.mem
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mem=system.cpu.mem
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numIQEntries=64
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numPhysFloatRegs=256
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numPhysIntRegs=256
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numROBEntries=192
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numRobs=1
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numThreads=1
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predType=tournament
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renameToDecodeDelay=1
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@ -116,163 +117,149 @@ renameToROBDelay=1
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renameWidth=8
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squashWidth=8
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system=system
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trapLatency=13
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wbDepth=1
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wbWidth=8
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workload=system.workload
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[system.cpu0.checker]
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type=O3Checker
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clock=1
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defer_registration=false
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exitOnError=true
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function_trace=false
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function_trace_start=0
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max_insts_all_threads=0
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max_insts_any_thread=0
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max_loads_all_threads=0
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max_loads_any_thread=0
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system=system
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warnOnlyOnLoadError=false
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workload=system.workload
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[system.cpu0.fuPool]
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[system.cpu.fuPool]
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type=FUPool
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children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
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FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7
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FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
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[system.cpu0.fuPool.FUList0]
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[system.cpu.fuPool.FUList0]
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type=FUDesc
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children=opList0
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count=6
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opList=system.cpu0.fuPool.FUList0.opList0
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opList=system.cpu.fuPool.FUList0.opList0
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[system.cpu0.fuPool.FUList0.opList0]
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[system.cpu.fuPool.FUList0.opList0]
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type=OpDesc
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issueLat=1
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opClass=IntAlu
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opLat=1
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[system.cpu0.fuPool.FUList1]
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[system.cpu.fuPool.FUList1]
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type=FUDesc
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children=opList0 opList1
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count=2
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opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1
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opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
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[system.cpu0.fuPool.FUList1.opList0]
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[system.cpu.fuPool.FUList1.opList0]
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type=OpDesc
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issueLat=1
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opClass=IntMult
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opLat=3
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[system.cpu0.fuPool.FUList1.opList1]
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[system.cpu.fuPool.FUList1.opList1]
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type=OpDesc
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issueLat=19
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opClass=IntDiv
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opLat=20
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[system.cpu0.fuPool.FUList2]
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[system.cpu.fuPool.FUList2]
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type=FUDesc
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children=opList0 opList1 opList2
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count=4
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opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2
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opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
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[system.cpu0.fuPool.FUList2.opList0]
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[system.cpu.fuPool.FUList2.opList0]
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type=OpDesc
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issueLat=1
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opClass=FloatAdd
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opLat=2
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[system.cpu0.fuPool.FUList2.opList1]
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[system.cpu.fuPool.FUList2.opList1]
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type=OpDesc
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issueLat=1
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opClass=FloatCmp
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opLat=2
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[system.cpu0.fuPool.FUList2.opList2]
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[system.cpu.fuPool.FUList2.opList2]
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type=OpDesc
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issueLat=1
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opClass=FloatCvt
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opLat=2
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[system.cpu0.fuPool.FUList3]
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[system.cpu.fuPool.FUList3]
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type=FUDesc
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children=opList0 opList1 opList2
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count=2
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opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2
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opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
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[system.cpu0.fuPool.FUList3.opList0]
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[system.cpu.fuPool.FUList3.opList0]
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type=OpDesc
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issueLat=1
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opClass=FloatMult
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opLat=4
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[system.cpu0.fuPool.FUList3.opList1]
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[system.cpu.fuPool.FUList3.opList1]
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type=OpDesc
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issueLat=12
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opClass=FloatDiv
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opLat=12
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[system.cpu0.fuPool.FUList3.opList2]
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[system.cpu.fuPool.FUList3.opList2]
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type=OpDesc
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issueLat=24
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opClass=FloatSqrt
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opLat=24
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[system.cpu0.fuPool.FUList4]
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[system.cpu.fuPool.FUList4]
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type=FUDesc
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children=opList0
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count=0
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opList=system.cpu0.fuPool.FUList4.opList0
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opList=system.cpu.fuPool.FUList4.opList0
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[system.cpu0.fuPool.FUList4.opList0]
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[system.cpu.fuPool.FUList4.opList0]
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type=OpDesc
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issueLat=1
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opClass=MemRead
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opLat=1
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[system.cpu0.fuPool.FUList5]
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[system.cpu.fuPool.FUList5]
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type=FUDesc
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children=opList0
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count=0
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opList=system.cpu0.fuPool.FUList5.opList0
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opList=system.cpu.fuPool.FUList5.opList0
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[system.cpu0.fuPool.FUList5.opList0]
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[system.cpu.fuPool.FUList5.opList0]
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type=OpDesc
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issueLat=1
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opClass=MemWrite
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opLat=1
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[system.cpu0.fuPool.FUList6]
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[system.cpu.fuPool.FUList6]
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type=FUDesc
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children=opList0 opList1
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count=4
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opList=system.cpu0.fuPool.FUList6.opList0 system.cpu0.fuPool.FUList6.opList1
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opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
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[system.cpu0.fuPool.FUList6.opList0]
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[system.cpu.fuPool.FUList6.opList0]
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type=OpDesc
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issueLat=1
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||||
opClass=MemRead
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opLat=1
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[system.cpu0.fuPool.FUList6.opList1]
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[system.cpu.fuPool.FUList6.opList1]
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type=OpDesc
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||||
issueLat=1
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||||
opClass=MemWrite
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opLat=1
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||||
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[system.cpu0.fuPool.FUList7]
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[system.cpu.fuPool.FUList7]
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type=FUDesc
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||||
children=opList0
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count=1
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opList=system.cpu0.fuPool.FUList7.opList0
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opList=system.cpu.fuPool.FUList7.opList0
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[system.cpu0.fuPool.FUList7.opList0]
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[system.cpu.fuPool.FUList7.opList0]
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type=OpDesc
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||||
issueLat=3
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||||
opClass=IprAccess
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||||
opLat=3
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||||
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[system.cpu0.mem]
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[system.cpu.mem]
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||||
type=Bus
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bus_id=0
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||||
|
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@ -23,160 +23,146 @@ chkpt=
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output=cout
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system=system
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[system.cpu0.mem]
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[system.cpu.mem]
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type=Bus
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bus_id=0
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[system.cpu0.checker]
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type=O3Checker
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||||
max_insts_any_thread=0
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||||
max_insts_all_threads=0
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||||
max_loads_any_thread=0
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||||
max_loads_all_threads=0
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||||
workload=system.workload
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clock=1
|
||||
defer_registration=false
|
||||
exitOnError=true
|
||||
warnOnlyOnLoadError=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
|
||||
[system.cpu0.fuPool.FUList0.opList0]
|
||||
[system.cpu.fuPool.FUList0.opList0]
|
||||
type=OpDesc
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList0]
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
opList=system.cpu0.fuPool.FUList0.opList0
|
||||
opList=system.cpu.fuPool.FUList0.opList0
|
||||
count=6
|
||||
|
||||
[system.cpu0.fuPool.FUList1.opList0]
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
issueLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList1.opList1]
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
issueLat=19
|
||||
|
||||
[system.cpu0.fuPool.FUList1]
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
count=2
|
||||
|
||||
[system.cpu0.fuPool.FUList2.opList0]
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList2.opList1]
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList2.opList2]
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList2]
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
count=4
|
||||
|
||||
[system.cpu0.fuPool.FUList3.opList0]
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
issueLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList3.opList1]
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
issueLat=12
|
||||
|
||||
[system.cpu0.fuPool.FUList3.opList2]
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
issueLat=24
|
||||
|
||||
[system.cpu0.fuPool.FUList3]
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
count=2
|
||||
|
||||
[system.cpu0.fuPool.FUList4.opList0]
|
||||
[system.cpu.fuPool.FUList4.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList4]
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
opList=system.cpu0.fuPool.FUList4.opList0
|
||||
opList=system.cpu.fuPool.FUList4.opList0
|
||||
count=0
|
||||
|
||||
[system.cpu0.fuPool.FUList5.opList0]
|
||||
[system.cpu.fuPool.FUList5.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList5]
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
opList=system.cpu0.fuPool.FUList5.opList0
|
||||
opList=system.cpu.fuPool.FUList5.opList0
|
||||
count=0
|
||||
|
||||
[system.cpu0.fuPool.FUList6.opList0]
|
||||
[system.cpu.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList6.opList1]
|
||||
[system.cpu.fuPool.FUList6.opList1]
|
||||
type=OpDesc
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList6]
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
opList=system.cpu0.fuPool.FUList6.opList0 system.cpu0.fuPool.FUList6.opList1
|
||||
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
|
||||
count=4
|
||||
|
||||
[system.cpu0.fuPool.FUList7.opList0]
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
issueLat=3
|
||||
|
||||
[system.cpu0.fuPool.FUList7]
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
opList=system.cpu0.fuPool.FUList7.opList0
|
||||
opList=system.cpu.fuPool.FUList7.opList0
|
||||
count=1
|
||||
|
||||
[system.cpu0.fuPool]
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
|
||||
|
||||
[system.cpu0]
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
clock=1
|
||||
numThreads=1
|
||||
activity=0
|
||||
workload=system.workload
|
||||
mem=system.cpu0.mem
|
||||
checker=system.cpu0.checker
|
||||
mem=system.cpu.mem
|
||||
checker=null
|
||||
max_insts_any_thread=500000
|
||||
max_insts_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
|
|
@ -203,12 +189,12 @@ dispatchWidth=8
|
|||
issueWidth=8
|
||||
wbWidth=8
|
||||
wbDepth=1
|
||||
fuPool=system.cpu0.fuPool
|
||||
fuPool=system.cpu.fuPool
|
||||
iewToCommitDelay=1
|
||||
renameToROBDelay=1
|
||||
commitWidth=8
|
||||
squashWidth=8
|
||||
trapLatency=6
|
||||
trapLatency=13
|
||||
backComSize=5
|
||||
forwardComSize=5
|
||||
predType=tournament
|
||||
|
|
|
|||
|
|
@ -1,136 +1,135 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
global.BPredUnit.BTBHits 45390 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 59902 # Number of BTB lookups
|
||||
global.BPredUnit.RASInCorrect 85 # Number of incorrect RAS predictions.
|
||||
global.BPredUnit.condIncorrect 3098 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 46029 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 70231 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 7755 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 69741 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 148316 # Number of bytes of host memory used
|
||||
host_seconds 7.17 # Real time elapsed on the host
|
||||
host_tick_rate 36160 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 15235 # Number of conflicting loads.
|
||||
memdepunit.memDep.conflictingStores 2693 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 145639 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 60928 # Number of stores inserted to the mem dependence unit.
|
||||
global.BPredUnit.BTBHits 47245 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 62226 # Number of BTB lookups
|
||||
global.BPredUnit.RASInCorrect 88 # Number of incorrect RAS predictions.
|
||||
global.BPredUnit.condIncorrect 3133 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 48198 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 72853 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 7892 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 90438 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 148172 # Number of bytes of host memory used
|
||||
host_seconds 5.53 # Real time elapsed on the host
|
||||
host_tick_rate 35958 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 15372 # Number of conflicting loads.
|
||||
memdepunit.memDep.conflictingStores 1808 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 147140 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 63225 # Number of stores inserted to the mem dependence unit.
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 500002 # Number of instructions simulated
|
||||
sim_seconds 0.000000 # Number of seconds simulated
|
||||
sim_ticks 259259 # Number of ticks simulated
|
||||
system.cpu0.checker.numCycles 518940 # number of cpu cycles simulated
|
||||
system.cpu0.commit.COM:branches 61160 # Number of branches committed
|
||||
system.cpu0.commit.COM:bw_lim_events 17172 # number cycles where commit BW limit reached
|
||||
system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu0.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
|
||||
system.cpu0.commit.COM:committed_per_cycle.samples 251997
|
||||
system.cpu0.commit.COM:committed_per_cycle.min_value 0
|
||||
0 70509 2798.01%
|
||||
1 75489 2995.63%
|
||||
2 28876 1145.89%
|
||||
3 23224 921.60%
|
||||
4 21222 842.15%
|
||||
5 3198 126.91%
|
||||
6 8368 332.07%
|
||||
7 3939 156.31%
|
||||
8 17172 681.44%
|
||||
system.cpu0.commit.COM:committed_per_cycle.max_value 8
|
||||
system.cpu0.commit.COM:committed_per_cycle.end_dist
|
||||
sim_ticks 198813 # Number of ticks simulated
|
||||
system.cpu.commit.COM:branches 61160 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 24524 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 189916
|
||||
system.cpu.commit.COM:committed_per_cycle.min_value 0
|
||||
0 37455 1972.19%
|
||||
1 50343 2650.80%
|
||||
2 29014 1527.73%
|
||||
3 12786 673.25%
|
||||
4 19808 1042.99%
|
||||
5 2516 132.48%
|
||||
6 10075 530.50%
|
||||
7 3395 178.76%
|
||||
8 24524 1291.31%
|
||||
system.cpu.commit.COM:committed_per_cycle.max_value 8
|
||||
system.cpu.commit.COM:committed_per_cycle.end_dist
|
||||
|
||||
system.cpu0.commit.COM:count 518948 # Number of instructions committed
|
||||
system.cpu0.commit.COM:loads 131376 # Number of loads committed
|
||||
system.cpu0.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu0.commit.COM:refs 189772 # Number of memory references committed
|
||||
system.cpu0.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu0.commit.branchMispredicts 2836 # The number of times a branch was mispredicted
|
||||
system.cpu0.commit.commitCommittedInsts 518948 # The number of committed instructions
|
||||
system.cpu0.commit.commitNonSpecStalls 18 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu0.commit.commitSquashedInsts 44297 # The number of squashed insts skipped by commit
|
||||
system.cpu0.committedInsts 500002 # Number of Instructions Simulated
|
||||
system.cpu0.committedInsts_total 500002 # Number of Instructions Simulated
|
||||
system.cpu0.cpi 0.518516 # CPI: Cycles Per Instruction
|
||||
system.cpu0.cpi_total 0.518516 # CPI: Total CPI of All Threads
|
||||
system.cpu0.decode.DECODE:BlockedCycles 743 # Number of cycles decode is blocked
|
||||
system.cpu0.decode.DECODE:BranchMispred 281 # Number of times decode detected a branch misprediction
|
||||
system.cpu0.decode.DECODE:BranchResolved 16033 # Number of times decode resolved a branch
|
||||
system.cpu0.decode.DECODE:DecodedInsts 586219 # Number of instructions handled by decode
|
||||
system.cpu0.decode.DECODE:IdleCycles 143055 # Number of cycles decode is idle
|
||||
system.cpu0.decode.DECODE:RunCycles 108199 # Number of cycles decode is running
|
||||
system.cpu0.decode.DECODE:SquashCycles 7263 # Number of cycles decode is squashing
|
||||
system.cpu0.decode.DECODE:SquashedInsts 989 # Number of squashed instructions handled by decode
|
||||
system.cpu0.fetch.Branches 70231 # Number of branches that fetch encountered
|
||||
system.cpu0.fetch.CacheLines 71036 # Number of cache lines fetched
|
||||
system.cpu0.fetch.Cycles 180480 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu0.fetch.IcacheSquashes 962 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu0.fetch.Insts 594968 # Number of instructions fetch has processed
|
||||
system.cpu0.fetch.SquashCycles 3140 # Number of cycles fetch has spent squashing
|
||||
system.cpu0.fetch.branchRate 0.270890 # Number of branch fetches per cycle
|
||||
system.cpu0.fetch.icacheStallCycles 71036 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu0.fetch.predictedBranches 53145 # Number of branches that fetch has predicted taken
|
||||
system.cpu0.fetch.rate 2.294870 # Number of inst fetches per cycle
|
||||
system.cpu0.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
|
||||
system.cpu0.fetch.rateDist.samples 259260
|
||||
system.cpu0.fetch.rateDist.min_value 0
|
||||
0 149817 5778.64%
|
||||
1 3603 138.97%
|
||||
2 9058 349.38%
|
||||
3 10685 412.13%
|
||||
4 8455 326.12%
|
||||
5 18775 724.18%
|
||||
6 25664 989.89%
|
||||
7 6109 235.63%
|
||||
8 27094 1045.05%
|
||||
system.cpu0.fetch.rateDist.max_value 8
|
||||
system.cpu0.fetch.rateDist.end_dist
|
||||
system.cpu.commit.COM:count 518948 # Number of instructions committed
|
||||
system.cpu.commit.COM:loads 131376 # Number of loads committed
|
||||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 189772 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 2863 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 518948 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 18 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 59006 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 500002 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 500002 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.397624 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.397624 # CPI: Total CPI of All Threads
|
||||
system.cpu.decode.DECODE:BlockedCycles 2191 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 297 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 16283 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 604200 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 76141 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 110735 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 8898 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 1017 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 849 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 72853 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 72795 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 186280 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.Insts 616104 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 3180 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.366438 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 72795 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 55137 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 3.098896 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist.samples 198814
|
||||
system.cpu.fetch.rateDist.min_value 0
|
||||
0 85330 4291.95%
|
||||
1 3737 187.96%
|
||||
2 9626 484.17%
|
||||
3 11018 554.19%
|
||||
4 8626 433.87%
|
||||
5 19021 956.72%
|
||||
6 27490 1382.70%
|
||||
7 6216 312.65%
|
||||
8 27750 1395.78%
|
||||
system.cpu.fetch.rateDist.max_value 8
|
||||
system.cpu.fetch.rateDist.end_dist
|
||||
|
||||
system.cpu0.iew.EXEC:branches 64672 # Number of branches executed
|
||||
system.cpu0.iew.EXEC:insts 526242 # Number of executed instructions
|
||||
system.cpu0.iew.EXEC:loads 140576 # Number of load instructions executed
|
||||
system.cpu0.iew.EXEC:nop 19405 # number of nop insts executed
|
||||
system.cpu0.iew.EXEC:rate 2.029785 # Inst execution rate
|
||||
system.cpu0.iew.EXEC:refs 200121 # number of memory reference insts executed
|
||||
system.cpu0.iew.EXEC:squashedInsts 5760 # Number of squashed instructions skipped in execute
|
||||
system.cpu0.iew.EXEC:stores 59545 # Number of stores executed
|
||||
system.cpu0.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu0.iew.WB:consumers 394903 # num instructions consuming a value
|
||||
system.cpu0.iew.WB:count 523588 # cumulative count of insts written-back
|
||||
system.cpu0.iew.WB:fanout 0.746115 # average fanout of values written-back
|
||||
system.cpu0.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu0.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu0.iew.WB:producers 294643 # num instructions producing a value
|
||||
system.cpu0.iew.WB:rate 2.019548 # insts written-back per cycle
|
||||
system.cpu0.iew.WB:sent 524223 # cumulative count of insts sent to commit
|
||||
system.cpu0.iew.branchMispredicts 2948 # Number of branch mispredicts detected at execute
|
||||
system.cpu0.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
|
||||
system.cpu0.iew.iewDispLoadInsts 145639 # Number of dispatched load instructions
|
||||
system.cpu0.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions
|
||||
system.cpu0.iew.iewDispSquashedInsts 1523 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu0.iew.iewDispStoreInsts 60928 # Number of dispatched store instructions
|
||||
system.cpu0.iew.iewDispatchedInsts 563297 # Number of instructions dispatched to IQ
|
||||
system.cpu0.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu0.iew.iewSquashCycles 7263 # Number of cycles IEW is squashing
|
||||
system.cpu0.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
|
||||
system.cpu0.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu0.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu0.iew.lsq.thread.0.forwLoads 18223 # Number of loads that had data forwarded from stores
|
||||
system.cpu0.iew.lsq.thread.0.ignoredResponses 9 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu0.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu0.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
|
||||
system.cpu0.iew.lsq.thread.0.squashedLoads 14246 # Number of loads squashed
|
||||
system.cpu0.iew.lsq.thread.0.squashedStores 2528 # Number of stores squashed
|
||||
system.cpu0.iew.memOrderViolationEvents 44 # Number of memory order violations
|
||||
system.cpu0.iew.predictedNotTakenIncorrect 1750 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu0.iew.predictedTakenIncorrect 1198 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu0.ipc 1.928581 # IPC: Instructions Per Cycle
|
||||
system.cpu0.ipc_total 1.928581 # IPC: Total IPC of All Threads
|
||||
system.cpu0.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue
|
||||
system.cpu0.iq.IQ:residence:(null).samples 0
|
||||
system.cpu0.iq.IQ:residence:(null).min_value 0
|
||||
system.cpu.iew.EXEC:branches 65998 # Number of branches executed
|
||||
system.cpu.iew.EXEC:insts 534582 # Number of executed instructions
|
||||
system.cpu.iew.EXEC:loads 141825 # Number of load instructions executed
|
||||
system.cpu.iew.EXEC:nop 21827 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 2.688855 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 202010 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:squashedInsts 7038 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.EXEC:stores 60185 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 413743 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 532886 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.745847 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 308589 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 2.680324 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 533753 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 3004 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 147140 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 1292 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 63225 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 578006 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 8898 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 22061 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 15747 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 4825 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 48 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 1801 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 1203 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 2.514936 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 2.514936 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue
|
||||
system.cpu.iq.IQ:residence:(null).samples 0
|
||||
system.cpu.iq.IQ:residence:(null).min_value 0
|
||||
0 0
|
||||
2 0
|
||||
4 0
|
||||
|
|
@ -181,12 +180,12 @@ system.cpu0.iq.IQ:residence:(null).min_value 0
|
|||
94 0
|
||||
96 0
|
||||
98 0
|
||||
system.cpu0.iq.IQ:residence:(null).max_value 0
|
||||
system.cpu0.iq.IQ:residence:(null).end_dist
|
||||
system.cpu.iq.IQ:residence:(null).max_value 0
|
||||
system.cpu.iq.IQ:residence:(null).end_dist
|
||||
|
||||
system.cpu0.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue
|
||||
system.cpu0.iq.IQ:residence:IntAlu.samples 0
|
||||
system.cpu0.iq.IQ:residence:IntAlu.min_value 0
|
||||
system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue
|
||||
system.cpu.iq.IQ:residence:IntAlu.samples 0
|
||||
system.cpu.iq.IQ:residence:IntAlu.min_value 0
|
||||
0 0
|
||||
2 0
|
||||
4 0
|
||||
|
|
@ -237,12 +236,12 @@ system.cpu0.iq.IQ:residence:IntAlu.min_value 0
|
|||
94 0
|
||||
96 0
|
||||
98 0
|
||||
system.cpu0.iq.IQ:residence:IntAlu.max_value 0
|
||||
system.cpu0.iq.IQ:residence:IntAlu.end_dist
|
||||
system.cpu.iq.IQ:residence:IntAlu.max_value 0
|
||||
system.cpu.iq.IQ:residence:IntAlu.end_dist
|
||||
|
||||
system.cpu0.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue
|
||||
system.cpu0.iq.IQ:residence:IntMult.samples 0
|
||||
system.cpu0.iq.IQ:residence:IntMult.min_value 0
|
||||
system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue
|
||||
system.cpu.iq.IQ:residence:IntMult.samples 0
|
||||
system.cpu.iq.IQ:residence:IntMult.min_value 0
|
||||
0 0
|
||||
2 0
|
||||
4 0
|
||||
|
|
@ -293,12 +292,12 @@ system.cpu0.iq.IQ:residence:IntMult.min_value 0
|
|||
94 0
|
||||
96 0
|
||||
98 0
|
||||
system.cpu0.iq.IQ:residence:IntMult.max_value 0
|
||||
system.cpu0.iq.IQ:residence:IntMult.end_dist
|
||||
system.cpu.iq.IQ:residence:IntMult.max_value 0
|
||||
system.cpu.iq.IQ:residence:IntMult.end_dist
|
||||
|
||||
system.cpu0.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue
|
||||
system.cpu0.iq.IQ:residence:IntDiv.samples 0
|
||||
system.cpu0.iq.IQ:residence:IntDiv.min_value 0
|
||||
system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue
|
||||
system.cpu.iq.IQ:residence:IntDiv.samples 0
|
||||
system.cpu.iq.IQ:residence:IntDiv.min_value 0
|
||||
0 0
|
||||
2 0
|
||||
4 0
|
||||
|
|
@ -349,12 +348,12 @@ system.cpu0.iq.IQ:residence:IntDiv.min_value 0
|
|||
94 0
|
||||
96 0
|
||||
98 0
|
||||
system.cpu0.iq.IQ:residence:IntDiv.max_value 0
|
||||
system.cpu0.iq.IQ:residence:IntDiv.end_dist
|
||||
system.cpu.iq.IQ:residence:IntDiv.max_value 0
|
||||
system.cpu.iq.IQ:residence:IntDiv.end_dist
|
||||
|
||||
system.cpu0.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue
|
||||
system.cpu0.iq.IQ:residence:FloatAdd.samples 0
|
||||
system.cpu0.iq.IQ:residence:FloatAdd.min_value 0
|
||||
system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue
|
||||
system.cpu.iq.IQ:residence:FloatAdd.samples 0
|
||||
system.cpu.iq.IQ:residence:FloatAdd.min_value 0
|
||||
0 0
|
||||
2 0
|
||||
4 0
|
||||
|
|
@ -405,12 +404,12 @@ system.cpu0.iq.IQ:residence:FloatAdd.min_value 0
|
|||
94 0
|
||||
96 0
|
||||
98 0
|
||||
system.cpu0.iq.IQ:residence:FloatAdd.max_value 0
|
||||
system.cpu0.iq.IQ:residence:FloatAdd.end_dist
|
||||
system.cpu.iq.IQ:residence:FloatAdd.max_value 0
|
||||
system.cpu.iq.IQ:residence:FloatAdd.end_dist
|
||||
|
||||
system.cpu0.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue
|
||||
system.cpu0.iq.IQ:residence:FloatCmp.samples 0
|
||||
system.cpu0.iq.IQ:residence:FloatCmp.min_value 0
|
||||
system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue
|
||||
system.cpu.iq.IQ:residence:FloatCmp.samples 0
|
||||
system.cpu.iq.IQ:residence:FloatCmp.min_value 0
|
||||
0 0
|
||||
2 0
|
||||
4 0
|
||||
|
|
@ -461,12 +460,12 @@ system.cpu0.iq.IQ:residence:FloatCmp.min_value 0
|
|||
94 0
|
||||
96 0
|
||||
98 0
|
||||
system.cpu0.iq.IQ:residence:FloatCmp.max_value 0
|
||||
system.cpu0.iq.IQ:residence:FloatCmp.end_dist
|
||||
system.cpu.iq.IQ:residence:FloatCmp.max_value 0
|
||||
system.cpu.iq.IQ:residence:FloatCmp.end_dist
|
||||
|
||||
system.cpu0.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue
|
||||
system.cpu0.iq.IQ:residence:FloatCvt.samples 0
|
||||
system.cpu0.iq.IQ:residence:FloatCvt.min_value 0
|
||||
system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue
|
||||
system.cpu.iq.IQ:residence:FloatCvt.samples 0
|
||||
system.cpu.iq.IQ:residence:FloatCvt.min_value 0
|
||||
0 0
|
||||
2 0
|
||||
4 0
|
||||
|
|
@ -517,12 +516,12 @@ system.cpu0.iq.IQ:residence:FloatCvt.min_value 0
|
|||
94 0
|
||||
96 0
|
||||
98 0
|
||||
system.cpu0.iq.IQ:residence:FloatCvt.max_value 0
|
||||
system.cpu0.iq.IQ:residence:FloatCvt.end_dist
|
||||
system.cpu.iq.IQ:residence:FloatCvt.max_value 0
|
||||
system.cpu.iq.IQ:residence:FloatCvt.end_dist
|
||||
|
||||
system.cpu0.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue
|
||||
system.cpu0.iq.IQ:residence:FloatMult.samples 0
|
||||
system.cpu0.iq.IQ:residence:FloatMult.min_value 0
|
||||
system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue
|
||||
system.cpu.iq.IQ:residence:FloatMult.samples 0
|
||||
system.cpu.iq.IQ:residence:FloatMult.min_value 0
|
||||
0 0
|
||||
2 0
|
||||
4 0
|
||||
|
|
@ -573,12 +572,12 @@ system.cpu0.iq.IQ:residence:FloatMult.min_value 0
|
|||
94 0
|
||||
96 0
|
||||
98 0
|
||||
system.cpu0.iq.IQ:residence:FloatMult.max_value 0
|
||||
system.cpu0.iq.IQ:residence:FloatMult.end_dist
|
||||
system.cpu.iq.IQ:residence:FloatMult.max_value 0
|
||||
system.cpu.iq.IQ:residence:FloatMult.end_dist
|
||||
|
||||
system.cpu0.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue
|
||||
system.cpu0.iq.IQ:residence:FloatDiv.samples 0
|
||||
system.cpu0.iq.IQ:residence:FloatDiv.min_value 0
|
||||
system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue
|
||||
system.cpu.iq.IQ:residence:FloatDiv.samples 0
|
||||
system.cpu.iq.IQ:residence:FloatDiv.min_value 0
|
||||
0 0
|
||||
2 0
|
||||
4 0
|
||||
|
|
@ -629,12 +628,12 @@ system.cpu0.iq.IQ:residence:FloatDiv.min_value 0
|
|||
94 0
|
||||
96 0
|
||||
98 0
|
||||
system.cpu0.iq.IQ:residence:FloatDiv.max_value 0
|
||||
system.cpu0.iq.IQ:residence:FloatDiv.end_dist
|
||||
system.cpu.iq.IQ:residence:FloatDiv.max_value 0
|
||||
system.cpu.iq.IQ:residence:FloatDiv.end_dist
|
||||
|
||||
system.cpu0.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue
|
||||
system.cpu0.iq.IQ:residence:FloatSqrt.samples 0
|
||||
system.cpu0.iq.IQ:residence:FloatSqrt.min_value 0
|
||||
system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue
|
||||
system.cpu.iq.IQ:residence:FloatSqrt.samples 0
|
||||
system.cpu.iq.IQ:residence:FloatSqrt.min_value 0
|
||||
0 0
|
||||
2 0
|
||||
4 0
|
||||
|
|
@ -685,12 +684,12 @@ system.cpu0.iq.IQ:residence:FloatSqrt.min_value 0
|
|||
94 0
|
||||
96 0
|
||||
98 0
|
||||
system.cpu0.iq.IQ:residence:FloatSqrt.max_value 0
|
||||
system.cpu0.iq.IQ:residence:FloatSqrt.end_dist
|
||||
system.cpu.iq.IQ:residence:FloatSqrt.max_value 0
|
||||
system.cpu.iq.IQ:residence:FloatSqrt.end_dist
|
||||
|
||||
system.cpu0.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue
|
||||
system.cpu0.iq.IQ:residence:MemRead.samples 0
|
||||
system.cpu0.iq.IQ:residence:MemRead.min_value 0
|
||||
system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue
|
||||
system.cpu.iq.IQ:residence:MemRead.samples 0
|
||||
system.cpu.iq.IQ:residence:MemRead.min_value 0
|
||||
0 0
|
||||
2 0
|
||||
4 0
|
||||
|
|
@ -741,12 +740,12 @@ system.cpu0.iq.IQ:residence:MemRead.min_value 0
|
|||
94 0
|
||||
96 0
|
||||
98 0
|
||||
system.cpu0.iq.IQ:residence:MemRead.max_value 0
|
||||
system.cpu0.iq.IQ:residence:MemRead.end_dist
|
||||
system.cpu.iq.IQ:residence:MemRead.max_value 0
|
||||
system.cpu.iq.IQ:residence:MemRead.end_dist
|
||||
|
||||
system.cpu0.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue
|
||||
system.cpu0.iq.IQ:residence:MemWrite.samples 0
|
||||
system.cpu0.iq.IQ:residence:MemWrite.min_value 0
|
||||
system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue
|
||||
system.cpu.iq.IQ:residence:MemWrite.samples 0
|
||||
system.cpu.iq.IQ:residence:MemWrite.min_value 0
|
||||
0 0
|
||||
2 0
|
||||
4 0
|
||||
|
|
@ -797,12 +796,12 @@ system.cpu0.iq.IQ:residence:MemWrite.min_value 0
|
|||
94 0
|
||||
96 0
|
||||
98 0
|
||||
system.cpu0.iq.IQ:residence:MemWrite.max_value 0
|
||||
system.cpu0.iq.IQ:residence:MemWrite.end_dist
|
||||
system.cpu.iq.IQ:residence:MemWrite.max_value 0
|
||||
system.cpu.iq.IQ:residence:MemWrite.end_dist
|
||||
|
||||
system.cpu0.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue
|
||||
system.cpu0.iq.IQ:residence:IprAccess.samples 0
|
||||
system.cpu0.iq.IQ:residence:IprAccess.min_value 0
|
||||
system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue
|
||||
system.cpu.iq.IQ:residence:IprAccess.samples 0
|
||||
system.cpu.iq.IQ:residence:IprAccess.min_value 0
|
||||
0 0
|
||||
2 0
|
||||
4 0
|
||||
|
|
@ -853,12 +852,12 @@ system.cpu0.iq.IQ:residence:IprAccess.min_value 0
|
|||
94 0
|
||||
96 0
|
||||
98 0
|
||||
system.cpu0.iq.IQ:residence:IprAccess.max_value 0
|
||||
system.cpu0.iq.IQ:residence:IprAccess.end_dist
|
||||
system.cpu.iq.IQ:residence:IprAccess.max_value 0
|
||||
system.cpu.iq.IQ:residence:IprAccess.end_dist
|
||||
|
||||
system.cpu0.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue
|
||||
system.cpu0.iq.IQ:residence:InstPrefetch.samples 0
|
||||
system.cpu0.iq.IQ:residence:InstPrefetch.min_value 0
|
||||
system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue
|
||||
system.cpu.iq.IQ:residence:InstPrefetch.samples 0
|
||||
system.cpu.iq.IQ:residence:InstPrefetch.min_value 0
|
||||
0 0
|
||||
2 0
|
||||
4 0
|
||||
|
|
@ -909,12 +908,12 @@ system.cpu0.iq.IQ:residence:InstPrefetch.min_value 0
|
|||
94 0
|
||||
96 0
|
||||
98 0
|
||||
system.cpu0.iq.IQ:residence:InstPrefetch.max_value 0
|
||||
system.cpu0.iq.IQ:residence:InstPrefetch.end_dist
|
||||
system.cpu.iq.IQ:residence:InstPrefetch.max_value 0
|
||||
system.cpu.iq.IQ:residence:InstPrefetch.end_dist
|
||||
|
||||
system.cpu0.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue
|
||||
system.cpu0.iq.ISSUE:(null)_delay.samples 0
|
||||
system.cpu0.iq.ISSUE:(null)_delay.min_value 0
|
||||
system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue
|
||||
system.cpu.iq.ISSUE:(null)_delay.samples 0
|
||||
system.cpu.iq.ISSUE:(null)_delay.min_value 0
|
||||
0 0
|
||||
2 0
|
||||
4 0
|
||||
|
|
@ -965,12 +964,12 @@ system.cpu0.iq.ISSUE:(null)_delay.min_value 0
|
|||
94 0
|
||||
96 0
|
||||
98 0
|
||||
system.cpu0.iq.ISSUE:(null)_delay.max_value 0
|
||||
system.cpu0.iq.ISSUE:(null)_delay.end_dist
|
||||
system.cpu.iq.ISSUE:(null)_delay.max_value 0
|
||||
system.cpu.iq.ISSUE:(null)_delay.end_dist
|
||||
|
||||
system.cpu0.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue
|
||||
system.cpu0.iq.ISSUE:IntAlu_delay.samples 0
|
||||
system.cpu0.iq.ISSUE:IntAlu_delay.min_value 0
|
||||
system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue
|
||||
system.cpu.iq.ISSUE:IntAlu_delay.samples 0
|
||||
system.cpu.iq.ISSUE:IntAlu_delay.min_value 0
|
||||
0 0
|
||||
2 0
|
||||
4 0
|
||||
|
|
@ -1021,12 +1020,12 @@ system.cpu0.iq.ISSUE:IntAlu_delay.min_value 0
|
|||
94 0
|
||||
96 0
|
||||
98 0
|
||||
system.cpu0.iq.ISSUE:IntAlu_delay.max_value 0
|
||||
system.cpu0.iq.ISSUE:IntAlu_delay.end_dist
|
||||
system.cpu.iq.ISSUE:IntAlu_delay.max_value 0
|
||||
system.cpu.iq.ISSUE:IntAlu_delay.end_dist
|
||||
|
||||
system.cpu0.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue
|
||||
system.cpu0.iq.ISSUE:IntMult_delay.samples 0
|
||||
system.cpu0.iq.ISSUE:IntMult_delay.min_value 0
|
||||
system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue
|
||||
system.cpu.iq.ISSUE:IntMult_delay.samples 0
|
||||
system.cpu.iq.ISSUE:IntMult_delay.min_value 0
|
||||
0 0
|
||||
2 0
|
||||
4 0
|
||||
|
|
@ -1077,12 +1076,12 @@ system.cpu0.iq.ISSUE:IntMult_delay.min_value 0
|
|||
94 0
|
||||
96 0
|
||||
98 0
|
||||
system.cpu0.iq.ISSUE:IntMult_delay.max_value 0
|
||||
system.cpu0.iq.ISSUE:IntMult_delay.end_dist
|
||||
system.cpu.iq.ISSUE:IntMult_delay.max_value 0
|
||||
system.cpu.iq.ISSUE:IntMult_delay.end_dist
|
||||
|
||||
system.cpu0.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue
|
||||
system.cpu0.iq.ISSUE:IntDiv_delay.samples 0
|
||||
system.cpu0.iq.ISSUE:IntDiv_delay.min_value 0
|
||||
system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue
|
||||
system.cpu.iq.ISSUE:IntDiv_delay.samples 0
|
||||
system.cpu.iq.ISSUE:IntDiv_delay.min_value 0
|
||||
0 0
|
||||
2 0
|
||||
4 0
|
||||
|
|
@ -1133,12 +1132,12 @@ system.cpu0.iq.ISSUE:IntDiv_delay.min_value 0
|
|||
94 0
|
||||
96 0
|
||||
98 0
|
||||
system.cpu0.iq.ISSUE:IntDiv_delay.max_value 0
|
||||
system.cpu0.iq.ISSUE:IntDiv_delay.end_dist
|
||||
system.cpu.iq.ISSUE:IntDiv_delay.max_value 0
|
||||
system.cpu.iq.ISSUE:IntDiv_delay.end_dist
|
||||
|
||||
system.cpu0.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue
|
||||
system.cpu0.iq.ISSUE:FloatAdd_delay.samples 0
|
||||
system.cpu0.iq.ISSUE:FloatAdd_delay.min_value 0
|
||||
system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue
|
||||
system.cpu.iq.ISSUE:FloatAdd_delay.samples 0
|
||||
system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0
|
||||
0 0
|
||||
2 0
|
||||
4 0
|
||||
|
|
@ -1189,12 +1188,12 @@ system.cpu0.iq.ISSUE:FloatAdd_delay.min_value 0
|
|||
94 0
|
||||
96 0
|
||||
98 0
|
||||
system.cpu0.iq.ISSUE:FloatAdd_delay.max_value 0
|
||||
system.cpu0.iq.ISSUE:FloatAdd_delay.end_dist
|
||||
system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0
|
||||
system.cpu.iq.ISSUE:FloatAdd_delay.end_dist
|
||||
|
||||
system.cpu0.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue
|
||||
system.cpu0.iq.ISSUE:FloatCmp_delay.samples 0
|
||||
system.cpu0.iq.ISSUE:FloatCmp_delay.min_value 0
|
||||
system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue
|
||||
system.cpu.iq.ISSUE:FloatCmp_delay.samples 0
|
||||
system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0
|
||||
0 0
|
||||
2 0
|
||||
4 0
|
||||
|
|
@ -1245,12 +1244,12 @@ system.cpu0.iq.ISSUE:FloatCmp_delay.min_value 0
|
|||
94 0
|
||||
96 0
|
||||
98 0
|
||||
system.cpu0.iq.ISSUE:FloatCmp_delay.max_value 0
|
||||
system.cpu0.iq.ISSUE:FloatCmp_delay.end_dist
|
||||
system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0
|
||||
system.cpu.iq.ISSUE:FloatCmp_delay.end_dist
|
||||
|
||||
system.cpu0.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue
|
||||
system.cpu0.iq.ISSUE:FloatCvt_delay.samples 0
|
||||
system.cpu0.iq.ISSUE:FloatCvt_delay.min_value 0
|
||||
system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue
|
||||
system.cpu.iq.ISSUE:FloatCvt_delay.samples 0
|
||||
system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0
|
||||
0 0
|
||||
2 0
|
||||
4 0
|
||||
|
|
@ -1301,12 +1300,12 @@ system.cpu0.iq.ISSUE:FloatCvt_delay.min_value 0
|
|||
94 0
|
||||
96 0
|
||||
98 0
|
||||
system.cpu0.iq.ISSUE:FloatCvt_delay.max_value 0
|
||||
system.cpu0.iq.ISSUE:FloatCvt_delay.end_dist
|
||||
system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0
|
||||
system.cpu.iq.ISSUE:FloatCvt_delay.end_dist
|
||||
|
||||
system.cpu0.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue
|
||||
system.cpu0.iq.ISSUE:FloatMult_delay.samples 0
|
||||
system.cpu0.iq.ISSUE:FloatMult_delay.min_value 0
|
||||
system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue
|
||||
system.cpu.iq.ISSUE:FloatMult_delay.samples 0
|
||||
system.cpu.iq.ISSUE:FloatMult_delay.min_value 0
|
||||
0 0
|
||||
2 0
|
||||
4 0
|
||||
|
|
@ -1357,12 +1356,12 @@ system.cpu0.iq.ISSUE:FloatMult_delay.min_value 0
|
|||
94 0
|
||||
96 0
|
||||
98 0
|
||||
system.cpu0.iq.ISSUE:FloatMult_delay.max_value 0
|
||||
system.cpu0.iq.ISSUE:FloatMult_delay.end_dist
|
||||
system.cpu.iq.ISSUE:FloatMult_delay.max_value 0
|
||||
system.cpu.iq.ISSUE:FloatMult_delay.end_dist
|
||||
|
||||
system.cpu0.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue
|
||||
system.cpu0.iq.ISSUE:FloatDiv_delay.samples 0
|
||||
system.cpu0.iq.ISSUE:FloatDiv_delay.min_value 0
|
||||
system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue
|
||||
system.cpu.iq.ISSUE:FloatDiv_delay.samples 0
|
||||
system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0
|
||||
0 0
|
||||
2 0
|
||||
4 0
|
||||
|
|
@ -1413,12 +1412,12 @@ system.cpu0.iq.ISSUE:FloatDiv_delay.min_value 0
|
|||
94 0
|
||||
96 0
|
||||
98 0
|
||||
system.cpu0.iq.ISSUE:FloatDiv_delay.max_value 0
|
||||
system.cpu0.iq.ISSUE:FloatDiv_delay.end_dist
|
||||
system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0
|
||||
system.cpu.iq.ISSUE:FloatDiv_delay.end_dist
|
||||
|
||||
system.cpu0.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue
|
||||
system.cpu0.iq.ISSUE:FloatSqrt_delay.samples 0
|
||||
system.cpu0.iq.ISSUE:FloatSqrt_delay.min_value 0
|
||||
system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue
|
||||
system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0
|
||||
system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0
|
||||
0 0
|
||||
2 0
|
||||
4 0
|
||||
|
|
@ -1469,12 +1468,12 @@ system.cpu0.iq.ISSUE:FloatSqrt_delay.min_value 0
|
|||
94 0
|
||||
96 0
|
||||
98 0
|
||||
system.cpu0.iq.ISSUE:FloatSqrt_delay.max_value 0
|
||||
system.cpu0.iq.ISSUE:FloatSqrt_delay.end_dist
|
||||
system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0
|
||||
system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist
|
||||
|
||||
system.cpu0.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue
|
||||
system.cpu0.iq.ISSUE:MemRead_delay.samples 0
|
||||
system.cpu0.iq.ISSUE:MemRead_delay.min_value 0
|
||||
system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue
|
||||
system.cpu.iq.ISSUE:MemRead_delay.samples 0
|
||||
system.cpu.iq.ISSUE:MemRead_delay.min_value 0
|
||||
0 0
|
||||
2 0
|
||||
4 0
|
||||
|
|
@ -1525,12 +1524,12 @@ system.cpu0.iq.ISSUE:MemRead_delay.min_value 0
|
|||
94 0
|
||||
96 0
|
||||
98 0
|
||||
system.cpu0.iq.ISSUE:MemRead_delay.max_value 0
|
||||
system.cpu0.iq.ISSUE:MemRead_delay.end_dist
|
||||
system.cpu.iq.ISSUE:MemRead_delay.max_value 0
|
||||
system.cpu.iq.ISSUE:MemRead_delay.end_dist
|
||||
|
||||
system.cpu0.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue
|
||||
system.cpu0.iq.ISSUE:MemWrite_delay.samples 0
|
||||
system.cpu0.iq.ISSUE:MemWrite_delay.min_value 0
|
||||
system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue
|
||||
system.cpu.iq.ISSUE:MemWrite_delay.samples 0
|
||||
system.cpu.iq.ISSUE:MemWrite_delay.min_value 0
|
||||
0 0
|
||||
2 0
|
||||
4 0
|
||||
|
|
@ -1581,12 +1580,12 @@ system.cpu0.iq.ISSUE:MemWrite_delay.min_value 0
|
|||
94 0
|
||||
96 0
|
||||
98 0
|
||||
system.cpu0.iq.ISSUE:MemWrite_delay.max_value 0
|
||||
system.cpu0.iq.ISSUE:MemWrite_delay.end_dist
|
||||
system.cpu.iq.ISSUE:MemWrite_delay.max_value 0
|
||||
system.cpu.iq.ISSUE:MemWrite_delay.end_dist
|
||||
|
||||
system.cpu0.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue
|
||||
system.cpu0.iq.ISSUE:IprAccess_delay.samples 0
|
||||
system.cpu0.iq.ISSUE:IprAccess_delay.min_value 0
|
||||
system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue
|
||||
system.cpu.iq.ISSUE:IprAccess_delay.samples 0
|
||||
system.cpu.iq.ISSUE:IprAccess_delay.min_value 0
|
||||
0 0
|
||||
2 0
|
||||
4 0
|
||||
|
|
@ -1637,12 +1636,12 @@ system.cpu0.iq.ISSUE:IprAccess_delay.min_value 0
|
|||
94 0
|
||||
96 0
|
||||
98 0
|
||||
system.cpu0.iq.ISSUE:IprAccess_delay.max_value 0
|
||||
system.cpu0.iq.ISSUE:IprAccess_delay.end_dist
|
||||
system.cpu.iq.ISSUE:IprAccess_delay.max_value 0
|
||||
system.cpu.iq.ISSUE:IprAccess_delay.end_dist
|
||||
|
||||
system.cpu0.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue
|
||||
system.cpu0.iq.ISSUE:InstPrefetch_delay.samples 0
|
||||
system.cpu0.iq.ISSUE:InstPrefetch_delay.min_value 0
|
||||
system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue
|
||||
system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0
|
||||
system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0
|
||||
0 0
|
||||
2 0
|
||||
4 0
|
||||
|
|
@ -1693,13 +1692,13 @@ system.cpu0.iq.ISSUE:InstPrefetch_delay.min_value 0
|
|||
94 0
|
||||
96 0
|
||||
98 0
|
||||
system.cpu0.iq.ISSUE:InstPrefetch_delay.max_value 0
|
||||
system.cpu0.iq.ISSUE:InstPrefetch_delay.end_dist
|
||||
system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0
|
||||
system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist
|
||||
|
||||
system.cpu0.iq.ISSUE:FU_type_0 532005 # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0.start_dist
|
||||
system.cpu.iq.ISSUE:FU_type_0 541621 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
||||
(null) 0 0.00% # Type of FU issued
|
||||
IntAlu 329259 61.89% # Type of FU issued
|
||||
IntAlu 336144 62.06% # Type of FU issued
|
||||
IntMult 10 0.00% # Type of FU issued
|
||||
IntDiv 0 0.00% # Type of FU issued
|
||||
FloatAdd 13 0.00% # Type of FU issued
|
||||
|
|
@ -1708,16 +1707,16 @@ system.cpu0.iq.ISSUE:FU_type_0.start_dist
|
|||
FloatMult 2 0.00% # Type of FU issued
|
||||
FloatDiv 0 0.00% # Type of FU issued
|
||||
FloatSqrt 0 0.00% # Type of FU issued
|
||||
MemRead 142868 26.85% # Type of FU issued
|
||||
MemWrite 59850 11.25% # Type of FU issued
|
||||
MemRead 144008 26.59% # Type of FU issued
|
||||
MemWrite 61441 11.34% # Type of FU issued
|
||||
IprAccess 0 0.00% # Type of FU issued
|
||||
InstPrefetch 0 0.00% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0.end_dist
|
||||
system.cpu0.iq.ISSUE:fu_busy_cnt 5510 # FU busy when requested
|
||||
system.cpu0.iq.ISSUE:fu_busy_rate 0.010357 # FU busy rate (busy events/executed inst)
|
||||
system.cpu0.iq.ISSUE:fu_full.start_dist
|
||||
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 10389 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.019181 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full.start_dist
|
||||
(null) 0 0.00% # attempts to use FU when none available
|
||||
IntAlu 1663 30.18% # attempts to use FU when none available
|
||||
IntAlu 6229 59.96% # attempts to use FU when none available
|
||||
IntMult 0 0.00% # attempts to use FU when none available
|
||||
IntDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatAdd 0 0.00% # attempts to use FU when none available
|
||||
|
|
@ -1726,50 +1725,50 @@ system.cpu0.iq.ISSUE:fu_full.start_dist
|
|||
FloatMult 0 0.00% # attempts to use FU when none available
|
||||
FloatDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatSqrt 0 0.00% # attempts to use FU when none available
|
||||
MemRead 2693 48.87% # attempts to use FU when none available
|
||||
MemWrite 1154 20.94% # attempts to use FU when none available
|
||||
MemRead 2497 24.04% # attempts to use FU when none available
|
||||
MemWrite 1663 16.01% # attempts to use FU when none available
|
||||
IprAccess 0 0.00% # attempts to use FU when none available
|
||||
InstPrefetch 0 0.00% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full.end_dist
|
||||
system.cpu0.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
||||
system.cpu0.iq.ISSUE:issued_per_cycle.samples 259260
|
||||
system.cpu0.iq.ISSUE:issued_per_cycle.min_value 0
|
||||
0 59185 2282.84%
|
||||
1 72964 2814.32%
|
||||
2 38364 1479.75%
|
||||
3 33144 1278.41%
|
||||
4 19818 764.41%
|
||||
5 14624 564.07%
|
||||
6 18233 703.27%
|
||||
7 2333 89.99%
|
||||
8 595 22.95%
|
||||
system.cpu0.iq.ISSUE:issued_per_cycle.max_value 8
|
||||
system.cpu0.iq.ISSUE:issued_per_cycle.end_dist
|
||||
system.cpu.iq.ISSUE:fu_full.end_dist
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 198814
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
||||
0 27333 1374.80%
|
||||
1 36906 1856.31%
|
||||
2 35716 1796.45%
|
||||
3 28916 1454.42%
|
||||
4 31868 1602.91%
|
||||
5 13027 655.24%
|
||||
6 21677 1090.32%
|
||||
7 3102 156.03%
|
||||
8 269 13.53%
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
||||
|
||||
system.cpu0.iq.ISSUE:rate 2.052013 # Inst issue rate
|
||||
system.cpu0.iq.iqInstsAdded 543865 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu0.iq.iqInstsIssued 532005 # Number of instructions issued
|
||||
system.cpu0.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu0.iq.iqSquashedInstsExamined 42716 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu0.iq.iqSquashedInstsIssued 611 # Number of squashed instructions issued
|
||||
system.cpu0.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu0.iq.iqSquashedOperandsExamined 21818 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu0.numCycles 259260 # number of cpu cycles simulated
|
||||
system.cpu0.rename.RENAME:BlockCycles 191 # Number of cycles rename is blocking
|
||||
system.cpu0.rename.RENAME:CommittedMaps 386063 # Number of HB maps that are committed
|
||||
system.cpu0.rename.RENAME:IdleCycles 144885 # Number of cycles rename is idle
|
||||
system.cpu0.rename.RENAME:LSQFullEvents 336 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu0.rename.RENAME:RenameLookups 753146 # Number of register rename lookups that rename has made
|
||||
system.cpu0.rename.RENAME:RenamedInsts 577319 # Number of instructions processed by rename
|
||||
system.cpu0.rename.RENAME:RenamedOperands 432146 # Number of destination operands rename has renamed
|
||||
system.cpu0.rename.RENAME:RunCycles 106374 # Number of cycles rename is running
|
||||
system.cpu0.rename.RENAME:SquashCycles 7263 # Number of cycles rename is squashing
|
||||
system.cpu0.rename.RENAME:UnblockCycles 302 # Number of cycles rename is unblocking
|
||||
system.cpu0.rename.RENAME:UndoneMaps 46034 # Number of HB maps that are undone due to squashing
|
||||
system.cpu0.rename.RENAME:serializeStallCycles 245 # count of cycles rename stalled for serializing inst
|
||||
system.cpu0.rename.RENAME:serializingInsts 34 # count of serializing insts renamed
|
||||
system.cpu0.rename.RENAME:skidInsts 421 # count of insts added to the skid buffer
|
||||
system.cpu0.rename.RENAME:tempSerializingInsts 32 # count of temporary serializing insts renamed
|
||||
system.cpu.iq.ISSUE:rate 2.724260 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 556152 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 541621 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 55198 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 404 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 27398 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.numCycles 198814 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 266 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 386063 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IdleCycles 78342 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 1401 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 775201 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 594947 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 443127 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 109388 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 8898 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 1662 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 57015 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 258 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 41 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 4872 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 39 # count of temporary serializing insts renamed
|
||||
system.workload.PROG:num_syscalls 18 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -7,8 +7,7 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 19 2006 15:49:01
|
||||
M5 started Wed Jul 19 15:49:12 2006
|
||||
M5 compiled Jul 21 2006 16:19:30
|
||||
M5 started Fri Jul 21 16:41:07 2006
|
||||
M5 executing on zamp.eecs.umich.edu
|
||||
Creating SE system
|
||||
Exiting @ tick 259259 because a thread reached the max instruction count
|
||||
Exiting @ tick 198813 because a thread reached the max instruction count
|
||||
|
|
|
|||
|
|
@ -48,11 +48,11 @@ text_file=m5stats.txt
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu0 physmem workload
|
||||
children=cpu physmem workload
|
||||
mem_mode=atomic
|
||||
physmem=system.physmem
|
||||
|
||||
[system.cpu0]
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=mem
|
||||
clock=1
|
||||
|
|
@ -63,11 +63,11 @@ max_insts_all_threads=0
|
|||
max_insts_any_thread=500000
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
mem=system.cpu0.mem
|
||||
mem=system.cpu.mem
|
||||
system=system
|
||||
workload=system.workload
|
||||
|
||||
[system.cpu0.mem]
|
||||
[system.cpu.mem]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
|
||||
|
|
|
|||
|
|
@ -23,17 +23,17 @@ chkpt=
|
|||
output=cout
|
||||
system=system
|
||||
|
||||
[system.cpu0.mem]
|
||||
[system.cpu.mem]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
|
||||
[system.cpu0]
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
max_insts_any_thread=500000
|
||||
max_insts_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
mem=system.cpu0.mem
|
||||
mem=system.cpu.mem
|
||||
system=system
|
||||
workload=system.workload
|
||||
clock=1
|
||||
|
|
|
|||
|
|
@ -1,18 +1,18 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 739858 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 147760 # Number of bytes of host memory used
|
||||
host_seconds 0.68 # Real time elapsed on the host
|
||||
host_tick_rate 1006609 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 781730 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 147616 # Number of bytes of host memory used
|
||||
host_seconds 0.64 # Real time elapsed on the host
|
||||
host_tick_rate 1063244 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 500000 # Number of instructions simulated
|
||||
sim_seconds 0.000001 # Number of seconds simulated
|
||||
sim_ticks 680774 # Number of ticks simulated
|
||||
system.cpu0.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu0.numCycles 0 # number of cpu cycles simulated
|
||||
system.cpu0.num_insts 500000 # Number of instructions executed
|
||||
system.cpu0.num_refs 182203 # Number of memory references
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 0 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 500000 # Number of instructions executed
|
||||
system.cpu.num_refs 182203 # Number of memory references
|
||||
system.workload.PROG:num_syscalls 18 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -7,8 +7,7 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 19 2006 15:49:01
|
||||
M5 started Wed Jul 19 15:49:19 2006
|
||||
M5 compiled Jul 21 2006 16:19:30
|
||||
M5 started Fri Jul 21 16:19:43 2006
|
||||
M5 executing on zamp.eecs.umich.edu
|
||||
Creating SE system
|
||||
Exiting @ tick 680774 because a thread reached the max instruction count
|
||||
|
|
|
|||
Loading…
Reference in a new issue