file name changes ... minor ISA changes

arch/mips/isa/base.isa:
    restoring base.isa file ...
arch/mips/isa/formats/basic.isa:
    add c++ emacs header
arch/mips/isa/formats/branch.isa:
    added branch likely format
arch/mips/isa/formats/int.isa:
    small change to python code

--HG--
extra : convert_revision : defd592abb1a724f5f88b19c197b858420e92d17
This commit is contained in:
Korey Sewell 2006-02-16 02:39:46 -05:00
parent a0cdf213ab
commit 7c9ea671af
4 changed files with 79 additions and 90 deletions

View file

@ -1,18 +1,21 @@
// -*- mode:c++ -*-
//////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////
// //
// Base class for sparc instructions, and some support functions // Base class for MIPS instructions, and some support functions
// //
//Outputs to decoder.hh
output header {{ output header {{
/** /**
* Base class for all SPARC static instructions. * Base class for all SPARC static instructions.
*/ */
class SparcStaticInst : public StaticInst<SPARCISA> class MipsStaticInst : public StaticInst<MIPSISA>
{ {
protected: protected:
// Constructor. // Constructor.
SparcStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass) MipsStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass)
: StaticInst<SPARCISA>(mnem, _machInst, __opClass) : StaticInst<SPARCISA>(mnem, _machInst, __opClass)
{ {
} }
@ -20,12 +23,12 @@ output header {{
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
}; };
bool passesCondition(struct {uint8_t c:1; uint8_t v:1; uint8_t z:1; uint8_t n:1} codes, uint8_t condition);
}}; }};
//Ouputs to decoder.cc
output decoder {{ output decoder {{
std::string SparcStaticInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const std::string MipsStaticInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{ {
std::stringstream ss; std::stringstream ss;
@ -56,27 +59,5 @@ output decoder {{
return ss.str(); return ss.str();
} }
bool passesCondition(struct {uint8_t c:1; uint8_t v:1; uint8_t z:1; uint8_t n:1} codes, uint8_t condition)
{
switch(condition)
{
case 0b1000: return true;
case 0b0000: return false;
case 0b1001: return !codes.z;
case 0b0001: return codes.z;
case 0b1010: return !(codes.z | (codes.n ^ codes.v));
case 0b0010: return codes.z | (codes.n ^ codes.v);
case 0b1011: return !(codes.n ^ codes.v);
case 0b0011: return (codes.n ^ codes.v);
case 0b1100: return !(codes.c | codes.z);
case 0b0100: return (codes.c | codes.z);
case 0b1101: return !codes.c;
case 0b0101: return codes.c;
case 0b1110: return !codes.n;
case 0b0110: return codes.n;
case 0b1111: return !codes.v;
case 0b0111: return codes.v;
}
}
}}; }};

View file

@ -1,3 +1,4 @@
// -*- mode:c++ -*-
// Declarations for execute() methods. // Declarations for execute() methods.
def template BasicExecDeclare {{ def template BasicExecDeclare {{

View file

@ -1,30 +1,9 @@
// -*- mode:c++ -*- e// -*- mode:c++ -*-
// Copyright (c) 2003-2005 The Regents of The University of Michigan ////////////////////////////////////////////////////////////////////
// All rights reserved.
// //
// Redistribution and use in source and binary forms, with or without // Control transfer instructions
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
output header {{ output header {{
@ -37,18 +16,19 @@ output header {{
* where the disassembly string includes the target address (which * where the disassembly string includes the target address (which
* may depend on the PC and/or symbol table). * may depend on the PC and/or symbol table).
*/ */
class PCDependentDisassembly : public AlphaStaticInst class PCDependentDisassembly : public MipsStaticInst
{ {
protected: protected:
/// Cached program counter from last disassembly /// Cached program counter from last disassembly
mutable Addr cachedPC; mutable Addr cachedPC;
/// Cached symbol table pointer from last disassembly /// Cached symbol table pointer from last disassembly
mutable const SymbolTable *cachedSymtab; mutable const SymbolTable *cachedSymtab;
/// Constructor /// Constructor
PCDependentDisassembly(const char *mnem, MachInst _machInst, PCDependentDisassembly(const char *mnem, MachInst _machInst,
OpClass __opClass) OpClass __opClass)
: AlphaStaticInst(mnem, _machInst, __opClass), : MipsStaticInst(mnem, _machInst, __opClass),
cachedPC(0), cachedSymtab(0) cachedPC(0), cachedSymtab(0)
{ {
} }
@ -64,13 +44,36 @@ output header {{
class Branch : public PCDependentDisassembly class Branch : public PCDependentDisassembly
{ {
protected: protected:
/// Displacement to target address (signed). /// target address (signed) Displacement .
int32_t disp; int32_t targetOffset;
/// Constructor. /// Constructor.
Branch(const char *mnem, MachInst _machInst, OpClass __opClass) Branch(const char *mnem, MachInst _machInst, OpClass __opClass)
: PCDependentDisassembly(mnem, _machInst, __opClass), : PCDependentDisassembly(mnem, _machInst, __opClass),
disp(BRDISP << 2) targetOffset(OFFSET << 2)
{
}
Addr branchTarget(Addr branchPC) const;
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
/**
* Base class for branches (PC-relative control transfers),
* conditional or unconditional.
*/
class BranchLikely : public PCDependentDisassembly
{
protected:
/// target address (signed) Displacement .
int32_t targetOffset;
/// Constructor.
Branch(const char *mnem, MachInst _machInst, OpClass __opClass)
: PCDependentDisassembly(mnem, _machInst, __opClass),
targetOffset(OFFSET << 2)
{ {
} }
@ -82,7 +85,7 @@ output header {{
/** /**
* Base class for jumps (register-indirect control transfers). In * Base class for jumps (register-indirect control transfers). In
* the Alpha ISA, these are always unconditional. * the Mips ISA, these are always unconditional.
*/ */
class Jump : public PCDependentDisassembly class Jump : public PCDependentDisassembly
{ {
@ -95,7 +98,7 @@ output header {{
/// Constructor /// Constructor
Jump(const char *mnem, MachInst _machInst, OpClass __opClass) Jump(const char *mnem, MachInst _machInst, OpClass __opClass)
: PCDependentDisassembly(mnem, _machInst, __opClass), : PCDependentDisassembly(mnem, _machInst, __opClass),
disp(BRDISP) disp(OFFSET)
{ {
} }
@ -204,12 +207,12 @@ output decoder {{
}}; }};
def template JumpOrBranchDecode {{ def template JumpOrBranchDecode {{
return (RA == 31) return (RD == 0)
? (StaticInst<AlphaISA> *)new %(class_name)s(machInst) ? (StaticInst<MipsISA> *)new %(class_name)s(machInst)
: (StaticInst<AlphaISA> *)new %(class_name)sAndLink(machInst); : (StaticInst<MipsISA> *)new %(class_name)sAndLink(machInst);
}}; }};
def format CondBranch(code) {{ def format Branch(code) {{
code = 'bool cond;\n' + code + '\nif (cond) NPC = NPC + disp;\n'; code = 'bool cond;\n' + code + '\nif (cond) NPC = NPC + disp;\n';
iop = InstObjParams(name, Name, 'Branch', CodeBlock(code), iop = InstObjParams(name, Name, 'Branch', CodeBlock(code),
('IsDirectControl', 'IsCondControl')) ('IsDirectControl', 'IsCondControl'))
@ -219,31 +222,18 @@ def format CondBranch(code) {{
exec_output = BasicExecute.subst(iop) exec_output = BasicExecute.subst(iop)
}}; }};
let {{
def UncondCtrlBase(name, Name, base_class, npc_expr, flags):
# Declare basic control transfer w/o link (i.e. link reg is R31)
nolink_code = 'NPC = %s;\n' % npc_expr
nolink_iop = InstObjParams(name, Name, base_class,
CodeBlock(nolink_code), flags)
header_output = BasicDeclare.subst(nolink_iop)
decoder_output = BasicConstructor.subst(nolink_iop)
exec_output = BasicExecute.subst(nolink_iop)
# Generate declaration of '*AndLink' version, append to decls def format BranchLikely(code) {{
link_code = 'Ra = NPC & ~3;\n' + nolink_code code = 'bool cond;\n' + code + '\nif (cond) NPC = NPC + disp;\n';
link_iop = InstObjParams(name, Name + 'AndLink', base_class, iop = InstObjParams(name, Name, 'Branch', CodeBlock(code),
CodeBlock(link_code), flags) ('IsDirectControl', 'IsCondControl'))
header_output += BasicDeclare.subst(link_iop) header_output = BasicDeclare.subst(iop)
decoder_output += BasicConstructor.subst(link_iop) decoder_output = BasicConstructor.subst(iop)
exec_output += BasicExecute.subst(link_iop) decode_block = BasicDecode.subst(iop)
exec_output = BasicExecute.subst(iop)
# need to use link_iop for the decode template since it is expecting
# the shorter version of class_name (w/o "AndLink")
return (header_output, decoder_output,
JumpOrBranchDecode.subst(nolink_iop), exec_output)
}}; }};
def format UncondBranch(*flags) {{ def format UncondBranch(*flags) {{
flags += ('IsUncondControl', 'IsDirectControl') flags += ('IsUncondControl', 'IsDirectControl')
(header_output, decoder_output, decode_block, exec_output) = \ (header_output, decoder_output, decode_block, exec_output) = \

View file

@ -1,8 +1,11 @@
// -*- mode:c++ -*-
//////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////
// //
// Integer operate instructions // Integer operate instructions
// //
//Outputs to decoder.hh
output header {{ output header {{
/** /**
* Base class for integer operations. * Base class for integer operations.
@ -12,7 +15,7 @@ output header {{
protected: protected:
/// Constructor /// Constructor
IntegerOp(const char *mnem, MachInst _machInst, OpClass __opClass) : IntOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
MipsStaticInst(mnem, _machInst, __opClass) MipsStaticInst(mnem, _machInst, __opClass)
{ {
} }
@ -26,7 +29,7 @@ output header {{
uint16_t imm; uint16_t imm;
/// Constructor /// Constructor
IntegerOp(const char *mnem, MachInst _machInst, OpClass __opClass) : IntImmOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
MipsStaticInst(mnem, _machInst, __opClass),imm(INTIMM) MipsStaticInst(mnem, _machInst, __opClass),imm(INTIMM)
{ {
} }
@ -36,6 +39,7 @@ output header {{
}}; }};
//Outputs to decoder.cc
output decoder {{ output decoder {{
std::string IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const std::string IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{ {
@ -48,17 +52,30 @@ output decoder {{
} }
}}; }};
// Primary format for integer operate instructions:
// integer & FP operate instructions use Rd as dest, so check for
// Rd == 0 to detect nops
def template OperateNopCheckDecode {{
{
MipsStaticInst *i = new %(class_name)s(machInst);
if (RD == 0) {
i = makeNop(i);
}
return i;
}
}};
//Used by decoder.isa
def format IntOp(code, *opt_flags) {{ def format IntOp(code, *opt_flags) {{
orig_code = code orig_code = code
cblk = CodeBlock(code) cblk = CodeBlock(code)
# Figure out if we are creating a IntImmOp or a IntOp # Figure out if we are creating a IntImmOp or a IntOp
# by looking at the instruction name
iop = InstObjParams(name, Name, 'IntOp', cblk, opt_flags)
strlen = len(name) strlen = len(name)
if name[strlen-1] == 'i' or name[strlen-2:] == 'iu': if name[strlen-1] == 'i' or name[strlen-2:] == 'iu':
iop = InstObjParams(name, Name, 'IntOp', cblk, opt_flags) iop = InstObjParams(name, Name, 'IntImmOp', cblk, opt_flags)
else:
iop = InstObjParams(name, Name, 'IntImmOp', cblk, opt_flags)
header_output = BasicDeclare.subst(iop) header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop) decoder_output = BasicConstructor.subst(iop)