X86: Get PCI config space to work, and adjust address space prefix numbering scheme.

--HG--
extra : convert_revision : 2b382f478ee8cde3a35aa4c105196f200bc7afa6
This commit is contained in:
Gabe Black 2008-02-26 23:38:01 -05:00
parent 8c0baf2ce4
commit 7bde0285e5
8 changed files with 50 additions and 8 deletions

View file

@ -156,7 +156,7 @@ def makeLinuxMipsSystem(mem_mode, mdesc = None):
return self return self
def x86IOAddress(port): def x86IOAddress(port):
IO_address_space_base = 0x1000000000000000 IO_address_space_base = 0x8000000000000000
return IO_address_space_base + port; return IO_address_space_base + port;
def makeLinuxX86System(mem_mode, mdesc = None): def makeLinuxX86System(mem_mode, mdesc = None):
@ -189,6 +189,7 @@ def makeLinuxX86System(mem_mode, mdesc = None):
# Platform # Platform
self.opteron = Opteron() self.opteron = Opteron()
self.opteron.attachIO(self.iobus)
self.intrctrl = IntrControl() self.intrctrl = IntrControl()

View file

@ -339,6 +339,8 @@ namespace X86ISA
//XXX Add "Model-Specific Registers" //XXX Add "Model-Specific Registers"
MISCREG_PCI_CONFIG_ADDRESS,
NUM_MISCREGS NUM_MISCREGS
}; };

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@ -64,6 +64,7 @@
* ISA-specific helper functions for memory mapped IPR accesses. * ISA-specific helper functions for memory mapped IPR accesses.
*/ */
#include "arch/x86/miscregs.hh"
#include "config/full_system.hh" #include "config/full_system.hh"
#include "cpu/base.hh" #include "cpu/base.hh"
#include "cpu/thread_context.hh" #include "cpu/thread_context.hh"
@ -88,8 +89,13 @@ namespace X86ISA
#if !FULL_SYSTEM #if !FULL_SYSTEM
panic("Shouldn't have a memory mapped register in SE\n"); panic("Shouldn't have a memory mapped register in SE\n");
#else #else
xc->setMiscReg(pkt->getAddr() / sizeof(MiscReg), MiscRegIndex index = (MiscRegIndex)(pkt->getAddr() / sizeof(MiscReg));
gtoh(pkt->get<uint64_t>())); if (index == MISCREG_PCI_CONFIG_ADDRESS) {
xc->setMiscReg(index, gtoh(pkt->get<uint32_t>()));
} else {
xc->setMiscReg(pkt->getAddr() / sizeof(MiscReg),
gtoh(pkt->get<uint64_t>()));
}
#endif #endif
return xc->getCpuPtr()->ticks(1); return xc->getCpuPtr()->ticks(1);
} }

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@ -76,7 +76,7 @@
namespace X86ISA { namespace X86ISA {
TLB::TLB(const Params *p) : SimObject(p), size(p->size) TLB::TLB(const Params *p) : SimObject(p), configAddress(0), size(p->size)
{ {
tlb = new TlbEntry[size]; tlb = new TlbEntry[size];
std::memset(tlb, 0, sizeof(TlbEntry) * size); std::memset(tlb, 0, sizeof(TlbEntry) * size);
@ -147,6 +147,12 @@ TLB::invalidateAll()
} }
} }
void
TLB::setConfigAddress(uint32_t addr)
{
configAddress = addr;
}
void void
TLB::invalidateNonGlobal() TLB::invalidateNonGlobal()
{ {
@ -478,7 +484,19 @@ TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute)
// Make sure the address fits in the expected 16 bit IO address // Make sure the address fits in the expected 16 bit IO address
// space. // space.
assert(!(IOPort & ~0xFFFF)); assert(!(IOPort & ~0xFFFF));
req->setPaddr(PhysAddrPrefixIO | IOPort); if (IOPort == 0xCF8 && req->getSize() == 4) {
req->setMmapedIpr(true);
req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg));
} else if ((IOPort & ~mask(2)) == 0xCFC) {
Addr configAddress =
tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS);
if (bits(configAddress, 31, 31)) {
req->setPaddr(PhysAddrPrefixPciConfig |
bits(configAddress, 30, 0));
}
} else {
req->setPaddr(PhysAddrPrefixIO | IOPort);
}
return NoFault; return NoFault;
} else { } else {
panic("Access to unrecognized internal address space %#x.\n", panic("Access to unrecognized internal address space %#x.\n",

View file

@ -90,6 +90,7 @@ namespace X86ISA
friend class FakeDTLBFault; friend class FakeDTLBFault;
bool _allowNX; bool _allowNX;
uint32_t configAddress;
public: public:
bool allowNX() const bool allowNX() const
@ -104,6 +105,8 @@ namespace X86ISA
TlbEntry *lookup(Addr va, bool update_lru = true); TlbEntry *lookup(Addr va, bool update_lru = true);
void setConfigAddress(uint32_t addr);
#if FULL_SYSTEM #if FULL_SYSTEM
protected: protected:

View file

@ -88,7 +88,8 @@ namespace X86ISA
const Addr IntAddrPrefixMSR = ULL(0x200000000); const Addr IntAddrPrefixMSR = ULL(0x200000000);
const Addr IntAddrPrefixIO = ULL(0x300000000); const Addr IntAddrPrefixIO = ULL(0x300000000);
const Addr PhysAddrPrefixIO = ULL(0x1000000000000000); const Addr PhysAddrPrefixIO = ULL(0x8000000000000000);
const Addr PhysAddrPrefixPciConfig = ULL(0xC000000000000000);
} }
#endif //__ARCH_X86_X86TRAITS_HH__ #endif //__ARCH_X86_X86TRAITS_HH__

View file

@ -3,8 +3,16 @@ from m5.proxy import *
from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr
from Uart import Uart8250 from Uart import Uart8250
from Platform import Platform from Platform import Platform
from Pci import PciConfigAll
from SimConsole import SimConsole from SimConsole import SimConsole
class Opteron(Platform): class Opteron(Platform):
type = 'Opteron' type = 'Opteron'
system = Param.System(Parent.any, "system") system = Param.System(Parent.any, "system")
pciconfig = PciConfigAll()
def attachIO(self, bus):
self.pciconfig.pio = bus.default
bus.responder_set = True
bus.responder = self.pciconfig

View file

@ -36,6 +36,7 @@
#include <string> #include <string>
#include <vector> #include <vector>
#include "arch/x86/x86_traits.hh"
#include "cpu/intr_control.hh" #include "cpu/intr_control.hh"
#include "dev/simconsole.hh" #include "dev/simconsole.hh"
#include "dev/x86/opteron.hh" #include "dev/x86/opteron.hh"
@ -95,8 +96,10 @@ Opteron::pciToDma(Addr pciAddr) const
Addr Addr
Opteron::calcConfigAddr(int bus, int dev, int func) Opteron::calcConfigAddr(int bus, int dev, int func)
{ {
panic("Need implementation\n"); assert(func < 8);
M5_DUMMY_RETURN assert(dev < 32);
assert(bus == 0);
return (PhysAddrPrefixPciConfig | (func << 8) | (dev << 11));
} }
Opteron * Opteron *