add a flag that supercedes all other InstExec flags to print a trace in the Intel sim compatible format.
--HG-- extra : convert_revision : 19569e5645f2d68fb68a0352753c08c2a24bfdc4
This commit is contained in:
parent
a23ff5ac96
commit
7b04cd9561
130
cpu/exetrace.cc
130
cpu/exetrace.cc
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@ -51,81 +51,91 @@ using namespace std;
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void
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void
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Trace::InstRecord::dump(ostream &outs)
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Trace::InstRecord::dump(ostream &outs)
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{
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{
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if (flags[INTEL_FORMAT]) {
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ccprintf(outs, "%7d ) ", cycle);
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outs << "0x" << hex << PC << ":\t";
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if (staticInst->isLoad()) {
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outs << "<RD 0x" << hex << addr;
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outs << ">";
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} else if (staticInst->isStore()) {
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outs << "<WR 0x" << hex << addr;
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outs << ">";
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}
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} else {
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if (flags[PRINT_CYCLE])
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ccprintf(outs, "%7d: ", cycle);
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if (flags[PRINT_CYCLE])
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outs << cpu->name() << " ";
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ccprintf(outs, "%7d: ", cycle);
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outs << cpu->name() << " ";
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if (flags[TRACE_MISSPEC])
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outs << (misspeculating ? "-" : "+") << " ";
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if (flags[TRACE_MISSPEC])
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if (flags[PRINT_THREAD_NUM])
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outs << (misspeculating ? "-" : "+") << " ";
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outs << "T" << thread << " : ";
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if (flags[PRINT_THREAD_NUM])
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outs << "T" << thread << " : ";
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std::string sym_str;
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std::string sym_str;
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Addr sym_addr;
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Addr sym_addr;
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if (debugSymbolTable
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if (debugSymbolTable
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&& debugSymbolTable->findNearestSymbol(PC, sym_str, sym_addr)) {
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&& debugSymbolTable->findNearestSymbol(PC, sym_str, sym_addr)) {
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if (PC != sym_addr)
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if (PC != sym_addr)
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sym_str += csprintf("+%d", PC - sym_addr);
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sym_str += csprintf("+%d", PC - sym_addr);
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outs << "@" << sym_str << " : ";
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outs << "@" << sym_str << " : ";
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}
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}
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else {
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else {
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outs << "0x" << hex << PC << " : ";
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outs << "0x" << hex << PC << " : ";
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}
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}
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//
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//
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// Print decoded instruction
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// Print decoded instruction
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//
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//
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#if defined(__GNUC__) && (__GNUC__ < 3)
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#if defined(__GNUC__) && (__GNUC__ < 3)
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// There's a bug in gcc 2.x library that prevents setw()
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// There's a bug in gcc 2.x library that prevents setw()
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// from working properly on strings
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// from working properly on strings
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string mc(staticInst->disassemble(PC, debugSymbolTable));
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string mc(staticInst->disassemble(PC, debugSymbolTable));
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while (mc.length() < 26)
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while (mc.length() < 26)
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mc += " ";
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mc += " ";
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outs << mc;
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outs << mc;
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#else
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#else
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outs << setw(26) << left << staticInst->disassemble(PC, debugSymbolTable);
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outs << setw(26) << left << staticInst->disassemble(PC, debugSymbolTable);
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#endif
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#endif
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outs << " : ";
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outs << " : ";
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if (flags[PRINT_OP_CLASS]) {
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if (flags[PRINT_OP_CLASS]) {
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outs << opClassStrings[staticInst->opClass()] << " : ";
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outs << opClassStrings[staticInst->opClass()] << " : ";
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}
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}
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if (flags[PRINT_RESULT_DATA] && data_status != DataInvalid) {
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if (flags[PRINT_RESULT_DATA] && data_status != DataInvalid) {
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outs << " D=";
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outs << " D=";
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#if 0
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#if 0
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if (data_status == DataDouble)
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if (data_status == DataDouble)
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ccprintf(outs, "%f", data.as_double);
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ccprintf(outs, "%f", data.as_double);
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else
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else
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ccprintf(outs, "%#018x", data.as_int);
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ccprintf(outs, "%#018x", data.as_int);
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#else
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#else
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ccprintf(outs, "%#018x", data.as_int);
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ccprintf(outs, "%#018x", data.as_int);
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#endif
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#endif
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}
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if (flags[PRINT_EFF_ADDR] && addr_valid)
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outs << " A=0x" << hex << addr;
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if (flags[PRINT_INT_REGS] && regs_valid) {
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for (int i = 0; i < 32;)
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for (int j = i + 1; i <= j; i++)
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ccprintf(outs, "r%02d = %#018x%s", i, iregs->regs[i],
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((i == j) ? "\n" : " "));
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outs << "\n";
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}
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if (flags[PRINT_FETCH_SEQ] && fetch_seq_valid)
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outs << " FetchSeq=" << dec << fetch_seq;
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if (flags[PRINT_CP_SEQ] && cp_seq_valid)
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outs << " CPSeq=" << dec << cp_seq;
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}
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}
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if (flags[PRINT_EFF_ADDR] && addr_valid)
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outs << " A=0x" << hex << addr;
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if (flags[PRINT_INT_REGS] && regs_valid) {
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for (int i = 0; i < 32;)
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for (int j = i + 1; i <= j; i++)
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ccprintf(outs, "r%02d = %#018x%s", i, iregs->regs[i],
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((i == j) ? "\n" : " "));
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outs << "\n";
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}
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if (flags[PRINT_FETCH_SEQ] && fetch_seq_valid)
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outs << " FetchSeq=" << dec << fetch_seq;
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if (flags[PRINT_CP_SEQ] && cp_seq_valid)
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outs << " CPSeq=" << dec << cp_seq;
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//
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//
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// End of line...
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// End of line...
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//
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//
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@ -172,6 +182,9 @@ Param<bool> exe_trace_print_fetchseq(&exeTraceParams, "print_fetchseq",
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"print fetch sequence number", false);
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"print fetch sequence number", false);
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Param<bool> exe_trace_print_cp_seq(&exeTraceParams, "print_cpseq",
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Param<bool> exe_trace_print_cp_seq(&exeTraceParams, "print_cpseq",
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"print correct-path sequence number", false);
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"print correct-path sequence number", false);
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Param<bool> exe_trace_intel_format(&exeTraceParams, "intel_format",
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"print trace in intel compatible format", false);
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//
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//
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// Helper function for ExecutionTraceParamContext::checkParams() just
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// Helper function for ExecutionTraceParamContext::checkParams() just
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@ -190,6 +203,7 @@ Trace::InstRecord::setParams()
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flags[PRINT_INT_REGS] = exe_trace_print_iregs;
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flags[PRINT_INT_REGS] = exe_trace_print_iregs;
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flags[PRINT_FETCH_SEQ] = exe_trace_print_fetchseq;
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flags[PRINT_FETCH_SEQ] = exe_trace_print_fetchseq;
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flags[PRINT_CP_SEQ] = exe_trace_print_cp_seq;
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flags[PRINT_CP_SEQ] = exe_trace_print_cp_seq;
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flags[INTEL_FORMAT] = exe_trace_intel_format;
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}
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}
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void
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void
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@ -143,6 +143,7 @@ class InstRecord : public Record
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PRINT_INT_REGS,
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PRINT_INT_REGS,
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PRINT_FETCH_SEQ,
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PRINT_FETCH_SEQ,
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PRINT_CP_SEQ,
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PRINT_CP_SEQ,
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INTEL_FORMAT,
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NUM_BITS
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NUM_BITS
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};
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};
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