cpu: clean up architectural register classification
Move from a poorly documented scheme where the mapping of unified architectural register indices to register classes is hardcoded all over to one where there's an enum for the register classes and a function that encapsulates the mapping.
This commit is contained in:
parent
4f5775df64
commit
7aa423acad
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@ -1,5 +1,6 @@
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/*
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/*
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* Copyright (c) 2010 ARM Limited
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* Copyright (c) 2010 ARM Limited
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* Copyright (c) 2013 Advanced Micro Devices, Inc.
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* All rights reserved
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* All rights reserved
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*
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*
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* The license below extends only to copyright in the software and shall
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* The license below extends only to copyright in the software and shall
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@ -38,6 +39,7 @@
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*/
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*/
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#include "arch/arm/insts/misc.hh"
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#include "arch/arm/insts/misc.hh"
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#include "cpu/reg_class.hh"
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std::string
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std::string
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MrsOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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MrsOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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@ -48,17 +50,17 @@ MrsOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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ss << ", ";
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ss << ", ";
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bool foundPsr = false;
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bool foundPsr = false;
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for (unsigned i = 0; i < numSrcRegs(); i++) {
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for (unsigned i = 0; i < numSrcRegs(); i++) {
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int idx = srcRegIdx(i);
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RegIndex idx = srcRegIdx(i);
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if (idx < Ctrl_Base_DepTag) {
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RegIndex rel_idx;
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if (regIdxToClass(idx, &rel_idx) != MiscRegClass) {
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continue;
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continue;
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}
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}
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idx -= Ctrl_Base_DepTag;
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if (rel_idx == MISCREG_CPSR) {
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if (idx == MISCREG_CPSR) {
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ss << "cpsr";
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ss << "cpsr";
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foundPsr = true;
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foundPsr = true;
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break;
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break;
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}
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}
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if (idx == MISCREG_SPSR) {
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if (rel_idx == MISCREG_SPSR) {
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ss << "spsr";
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ss << "spsr";
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foundPsr = true;
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foundPsr = true;
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break;
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break;
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@ -1,5 +1,6 @@
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/*
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/*
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* Copyright (c) 2010 ARM Limited
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* Copyright (c) 2010 ARM Limited
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* Copyright (c) 2013 Advanced Micro Devices, Inc.
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* All rights reserved
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* All rights reserved
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*
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*
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* The license below extends only to copyright in the software and shall
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* The license below extends only to copyright in the software and shall
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@ -45,6 +46,7 @@
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#include "base/loader/symtab.hh"
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#include "base/loader/symtab.hh"
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#include "base/condcodes.hh"
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#include "base/condcodes.hh"
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#include "base/cprintf.hh"
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#include "base/cprintf.hh"
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#include "cpu/reg_class.hh"
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namespace ArmISA
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namespace ArmISA
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{
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{
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@ -208,8 +210,11 @@ ArmStaticInst::shift_carry_rs(uint32_t base, uint32_t shamt,
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void
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void
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ArmStaticInst::printReg(std::ostream &os, int reg) const
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ArmStaticInst::printReg(std::ostream &os, int reg) const
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{
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{
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if (reg < FP_Base_DepTag) {
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RegIndex rel_reg;
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switch (reg) {
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switch (regIdxToClass(reg, &rel_reg)) {
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case IntRegClass:
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switch (rel_reg) {
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case PCReg:
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case PCReg:
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ccprintf(os, "pc");
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ccprintf(os, "pc");
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break;
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break;
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@ -226,12 +231,14 @@ ArmStaticInst::printReg(std::ostream &os, int reg) const
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ccprintf(os, "r%d", reg);
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ccprintf(os, "r%d", reg);
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break;
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break;
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}
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}
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} else if (reg < Ctrl_Base_DepTag) {
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break;
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ccprintf(os, "f%d", reg - FP_Base_DepTag);
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case FloatRegClass:
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} else {
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ccprintf(os, "f%d", rel_reg);
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reg -= Ctrl_Base_DepTag;
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break;
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assert(reg < NUM_MISCREGS);
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case MiscRegClass:
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ccprintf(os, "%s", ArmISA::miscRegName[reg]);
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assert(rel_reg < NUM_MISCREGS);
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ccprintf(os, "%s", ArmISA::miscRegName[rel_reg]);
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break;
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}
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}
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}
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}
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@ -1,5 +1,6 @@
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/*
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/*
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* Copyright (c) 2009 The University of Edinburgh
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* Copyright (c) 2009 The University of Edinburgh
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* Copyright (c) 2013 Advanced Micro Devices, Inc.
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* All rights reserved.
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* All rights reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* Redistribution and use in source and binary forms, with or without
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@ -29,23 +30,30 @@
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*/
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*/
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#include "arch/power/insts/static_inst.hh"
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#include "arch/power/insts/static_inst.hh"
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#include "cpu/reg_class.hh"
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using namespace PowerISA;
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using namespace PowerISA;
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void
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void
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PowerStaticInst::printReg(std::ostream &os, int reg) const
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PowerStaticInst::printReg(std::ostream &os, int reg) const
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{
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{
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if (reg < FP_Base_DepTag) {
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RegIndex rel_reg;
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ccprintf(os, "r%d", reg);
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} else if (reg < Ctrl_Base_DepTag) {
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switch (regIdxToClass(reg, &rel_reg)) {
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ccprintf(os, "f%d", reg - FP_Base_DepTag);
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case IntRegClass:
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} else {
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ccprintf(os, "r%d", rel_reg);
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switch (reg - Ctrl_Base_DepTag) {
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break;
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case 0: ccprintf(os, "cr"); break;
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case FloatRegClass:
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case 1: ccprintf(os, "xer"); break;
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ccprintf(os, "f%d", rel_reg);
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case 2: ccprintf(os, "lr"); break;
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break;
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case 3: ccprintf(os, "ctr"); break;
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case MiscRegClass:
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default: ccprintf(os, "unknown_reg");
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switch (rel_reg) {
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case 0: ccprintf(os, "cr"); break;
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case 1: ccprintf(os, "xer"); break;
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case 2: ccprintf(os, "lr"); break;
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case 3: ccprintf(os, "ctr"); break;
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default: ccprintf(os, "unknown_reg");
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break;
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}
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}
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}
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}
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}
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}
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/*
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/*
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* Copyright (c) 2007 The Hewlett-Packard Development Company
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* Copyright (c) 2007 The Hewlett-Packard Development Company
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* Copyright (c) 2013 Advanced Micro Devices, Inc.
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* All rights reserved.
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* All rights reserved.
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*
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*
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* The license below extends only to copyright in the software and shall
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* The license below extends only to copyright in the software and shall
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@ -39,6 +40,7 @@
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#include "arch/x86/insts/static_inst.hh"
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#include "arch/x86/insts/static_inst.hh"
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#include "arch/x86/regs/segment.hh"
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#include "arch/x86/regs/segment.hh"
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#include "cpu/reg_class.hh"
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namespace X86ISA
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namespace X86ISA
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{
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{
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@ -129,17 +131,20 @@ namespace X86ISA
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static const char * microFormats[9] =
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static const char * microFormats[9] =
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{"", "t%db", "t%dw", "", "t%dd", "", "", "", "t%d"};
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{"", "t%db", "t%dw", "", "t%dd", "", "", "", "t%d"};
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if (reg < FP_Base_DepTag) {
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RegIndex rel_reg;
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switch (regIdxToClass(reg, &rel_reg)) {
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case IntRegClass: {
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const char * suffix = "";
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const char * suffix = "";
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bool fold = reg & IntFoldBit;
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bool fold = rel_reg & IntFoldBit;
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reg &= ~IntFoldBit;
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rel_reg &= ~IntFoldBit;
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if(fold)
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if(fold)
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suffix = "h";
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suffix = "h";
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else if(reg < 8 && size == 1)
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else if(rel_reg < 8 && size == 1)
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suffix = "l";
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suffix = "l";
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switch (reg) {
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switch (rel_reg) {
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case INTREG_RAX:
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case INTREG_RAX:
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ccprintf(os, abcdFormats[size], "a");
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ccprintf(os, abcdFormats[size], "a");
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break;
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break;
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@ -189,33 +194,39 @@ namespace X86ISA
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ccprintf(os, longFormats[size], "15");
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ccprintf(os, longFormats[size], "15");
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break;
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break;
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default:
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default:
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ccprintf(os, microFormats[size], reg - NUM_INTREGS);
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ccprintf(os, microFormats[size], rel_reg - NUM_INTREGS);
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}
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}
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ccprintf(os, suffix);
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ccprintf(os, suffix);
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} else if (reg < Ctrl_Base_DepTag) {
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break;
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int fpindex = reg - FP_Base_DepTag;
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}
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if(fpindex < NumMMXRegs) {
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ccprintf(os, "%%mmx%d", reg - FP_Base_DepTag);
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case FloatRegClass: {
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if (rel_reg < NumMMXRegs) {
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ccprintf(os, "%%mmx%d", rel_reg);
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return;
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return;
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}
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}
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fpindex -= NumMMXRegs;
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rel_reg -= NumMMXRegs;
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if(fpindex < NumXMMRegs * 2) {
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if (rel_reg < NumXMMRegs * 2) {
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ccprintf(os, "%%xmm%d_%s", fpindex / 2,
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ccprintf(os, "%%xmm%d_%s", rel_reg / 2,
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(fpindex % 2) ? "high": "low");
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(rel_reg % 2) ? "high": "low");
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return;
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return;
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}
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}
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fpindex -= NumXMMRegs * 2;
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rel_reg -= NumXMMRegs * 2;
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if(fpindex < NumMicroFpRegs) {
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if (rel_reg < NumMicroFpRegs) {
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ccprintf(os, "%%ufp%d", fpindex);
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ccprintf(os, "%%ufp%d", rel_reg);
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return;
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return;
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}
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}
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fpindex -= NumMicroFpRegs;
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rel_reg -= NumMicroFpRegs;
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ccprintf(os, "%%st(%d)", fpindex);
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ccprintf(os, "%%st(%d)", rel_reg);
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} else {
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break;
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switch (reg - Ctrl_Base_DepTag) {
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}
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case MiscRegClass:
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switch (rel_reg) {
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default:
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default:
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ccprintf(os, "%%ctrl%d", reg - Ctrl_Base_DepTag);
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ccprintf(os, "%%ctrl%d", rel_reg);
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}
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}
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break;
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}
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}
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}
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}
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@ -118,6 +118,7 @@ Source('nativetrace.cc')
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Source('pc_event.cc')
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Source('pc_event.cc')
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Source('profile.cc')
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Source('profile.cc')
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Source('quiesce_event.cc')
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Source('quiesce_event.cc')
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Source('reg_class.cc')
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Source('static_inst.cc')
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Source('static_inst.cc')
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Source('simple_thread.cc')
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Source('simple_thread.cc')
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Source('thread_context.cc')
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Source('thread_context.cc')
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@ -1,5 +1,6 @@
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/*
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/*
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* Copyright (c) 2011 ARM Limited
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* Copyright (c) 2011 ARM Limited
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* Copyright (c) 2013 Advanced Micro Devices, Inc.
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* All rights reserved
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* All rights reserved
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*
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*
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* The license below extends only to copyright in the software and shall
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* The license below extends only to copyright in the software and shall
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@ -50,6 +51,7 @@
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#include "config/the_isa.hh"
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#include "config/the_isa.hh"
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#include "cpu/base_dyn_inst.hh"
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#include "cpu/base_dyn_inst.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/reg_class.hh"
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#include "cpu/simple_thread.hh"
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#include "cpu/simple_thread.hh"
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#include "cpu/static_inst.hh"
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#include "cpu/static_inst.hh"
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#include "cpu/thread_context.hh"
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#include "cpu/thread_context.hh"
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@ -597,13 +599,17 @@ Checker<Impl>::copyResult(DynInstPtr &inst, uint64_t mismatch_val,
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// so do the fix-up then start with the next dest reg;
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// so do the fix-up then start with the next dest reg;
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if (start_idx >= 0) {
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if (start_idx >= 0) {
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RegIndex idx = inst->destRegIdx(start_idx);
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RegIndex idx = inst->destRegIdx(start_idx);
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if (idx < TheISA::FP_Base_DepTag) {
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switch (regIdxToClass(idx)) {
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case IntRegClass:
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thread->setIntReg(idx, mismatch_val);
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thread->setIntReg(idx, mismatch_val);
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} else if (idx < TheISA::Ctrl_Base_DepTag) {
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break;
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case FloatRegClass:
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thread->setFloatRegBits(idx, mismatch_val);
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thread->setFloatRegBits(idx, mismatch_val);
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} else if (idx < TheISA::Max_DepTag) {
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break;
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case MiscRegClass:
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thread->setMiscReg(idx - TheISA::Ctrl_Base_DepTag,
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thread->setMiscReg(idx - TheISA::Ctrl_Base_DepTag,
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mismatch_val);
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mismatch_val);
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break;
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}
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}
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}
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}
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start_idx++;
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start_idx++;
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@ -611,14 +617,19 @@ Checker<Impl>::copyResult(DynInstPtr &inst, uint64_t mismatch_val,
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for (int i = start_idx; i < inst->numDestRegs(); i++) {
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for (int i = start_idx; i < inst->numDestRegs(); i++) {
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RegIndex idx = inst->destRegIdx(i);
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RegIndex idx = inst->destRegIdx(i);
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inst->template popResult<uint64_t>(res);
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inst->template popResult<uint64_t>(res);
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if (idx < TheISA::FP_Base_DepTag) {
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switch (regIdxToClass(idx)) {
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case IntRegClass:
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thread->setIntReg(idx, res);
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thread->setIntReg(idx, res);
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} else if (idx < TheISA::Ctrl_Base_DepTag) {
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break;
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case FloatRegClass:
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thread->setFloatRegBits(idx, res);
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thread->setFloatRegBits(idx, res);
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} else if (idx < TheISA::Max_DepTag) {
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break;
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case MiscRegClass:
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// Try to get the proper misc register index for ARM here...
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// Try to get the proper misc register index for ARM here...
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thread->setMiscReg(idx - TheISA::Ctrl_Base_DepTag, res);
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thread->setMiscReg(idx - TheISA::Ctrl_Base_DepTag, res);
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} // else Register is out of range...
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break;
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// else Register is out of range...
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}
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}
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}
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}
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}
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@ -1,5 +1,6 @@
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/*
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/*
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* Copyright (c) 2012 ARM Limited
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* Copyright (c) 2012 ARM Limited
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* Copyright (c) 2013 Advanced Micro Devices, Inc.
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* All rights reserved
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* All rights reserved
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*
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*
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* The license below extends only to copyright in the software and shall
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* The license below extends only to copyright in the software and shall
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@ -59,6 +60,7 @@
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#include "cpu/base.hh"
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#include "cpu/base.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/quiesce_event.hh"
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#include "cpu/quiesce_event.hh"
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#include "cpu/reg_class.hh"
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#include "cpu/simple_thread.hh"
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#include "cpu/simple_thread.hh"
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#include "cpu/thread_context.hh"
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#include "cpu/thread_context.hh"
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#include "debug/Activity.hh"
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#include "debug/Activity.hh"
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@ -1257,16 +1259,23 @@ InOrderCPU::getPipeStage(int stage_num)
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RegIndex
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RegIndex
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InOrderCPU::flattenRegIdx(RegIndex reg_idx, RegType ®_type, ThreadID tid)
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InOrderCPU::flattenRegIdx(RegIndex reg_idx, RegType ®_type, ThreadID tid)
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{
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{
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if (reg_idx < FP_Base_DepTag) {
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RegIndex rel_idx;
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switch (regIdxToClass(reg_idx, &rel_idx)) {
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case IntRegClass:
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reg_type = IntType;
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reg_type = IntType;
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return isa[tid]->flattenIntIndex(reg_idx);
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return isa[tid]->flattenIntIndex(rel_idx);
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} else if (reg_idx < Ctrl_Base_DepTag) {
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case FloatRegClass:
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reg_type = FloatType;
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reg_type = FloatType;
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reg_idx -= FP_Base_DepTag;
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return isa[tid]->flattenFloatIndex(rel_idx);
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return isa[tid]->flattenFloatIndex(reg_idx);
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} else {
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case MiscRegClass:
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reg_type = MiscType;
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reg_type = MiscType;
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return reg_idx - TheISA::Ctrl_Base_DepTag;
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return rel_idx;
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default:
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panic("register %d out of range\n", reg_idx);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -1344,18 +1353,25 @@ InOrderCPU::readRegOtherThread(unsigned reg_idx, ThreadID tid)
|
||||||
tid = TheISA::getTargetThread(tcBase(tid));
|
tid = TheISA::getTargetThread(tcBase(tid));
|
||||||
}
|
}
|
||||||
|
|
||||||
if (reg_idx < FP_Base_DepTag) {
|
RegIndex rel_idx;
|
||||||
|
|
||||||
|
switch (regIdxToClass(reg_idx, &rel_idx)) {
|
||||||
|
case IntRegClass:
|
||||||
// Integer Register File
|
// Integer Register File
|
||||||
return readIntReg(reg_idx, tid);
|
return readIntReg(rel_idx, tid);
|
||||||
} else if (reg_idx < Ctrl_Base_DepTag) {
|
|
||||||
|
case FloatRegClass:
|
||||||
// Float Register File
|
// Float Register File
|
||||||
reg_idx -= FP_Base_DepTag;
|
return readFloatRegBits(rel_idx, tid);
|
||||||
return readFloatRegBits(reg_idx, tid);
|
|
||||||
} else {
|
case MiscRegClass:
|
||||||
reg_idx -= Ctrl_Base_DepTag;
|
return readMiscReg(rel_idx, tid); // Misc. Register File
|
||||||
return readMiscReg(reg_idx, tid); // Misc. Register File
|
|
||||||
|
default:
|
||||||
|
panic("register %d out of range\n", reg_idx);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
void
|
||||||
InOrderCPU::setRegOtherThread(unsigned reg_idx, const MiscReg &val,
|
InOrderCPU::setRegOtherThread(unsigned reg_idx, const MiscReg &val,
|
||||||
ThreadID tid)
|
ThreadID tid)
|
||||||
|
@ -1365,14 +1381,20 @@ InOrderCPU::setRegOtherThread(unsigned reg_idx, const MiscReg &val,
|
||||||
tid = TheISA::getTargetThread(tcBase(tid));
|
tid = TheISA::getTargetThread(tcBase(tid));
|
||||||
}
|
}
|
||||||
|
|
||||||
if (reg_idx < FP_Base_DepTag) { // Integer Register File
|
RegIndex rel_idx;
|
||||||
setIntReg(reg_idx, val, tid);
|
|
||||||
} else if (reg_idx < Ctrl_Base_DepTag) { // Float Register File
|
switch (regIdxToClass(reg_idx, &rel_idx)) {
|
||||||
reg_idx -= FP_Base_DepTag;
|
case IntRegClass:
|
||||||
setFloatRegBits(reg_idx, val, tid);
|
setIntReg(rel_idx, val, tid);
|
||||||
} else {
|
break;
|
||||||
reg_idx -= Ctrl_Base_DepTag;
|
|
||||||
setMiscReg(reg_idx, val, tid); // Misc. Register File
|
case FloatRegClass:
|
||||||
|
setFloatRegBits(rel_idx, val, tid);
|
||||||
|
break;
|
||||||
|
|
||||||
|
case MiscRegClass:
|
||||||
|
setMiscReg(rel_idx, val, tid); // Misc. Register File
|
||||||
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -1,5 +1,6 @@
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2012-2013 ARM Limited
|
* Copyright (c) 2012-2013 ARM Limited
|
||||||
|
* Copyright (c) 2013 Advanced Micro Devices, Inc.
|
||||||
* All rights reserved
|
* All rights reserved
|
||||||
*
|
*
|
||||||
* The license below extends only to copyright in the software and shall
|
* The license below extends only to copyright in the software and shall
|
||||||
|
@ -65,6 +66,7 @@
|
||||||
#include "cpu/o3/rename_map.hh"
|
#include "cpu/o3/rename_map.hh"
|
||||||
#include "cpu/activity.hh"
|
#include "cpu/activity.hh"
|
||||||
#include "cpu/base.hh"
|
#include "cpu/base.hh"
|
||||||
|
#include "cpu/reg_class.hh"
|
||||||
#include "cpu/simple_thread.hh"
|
#include "cpu/simple_thread.hh"
|
||||||
#include "cpu/timebuf.hh"
|
#include "cpu/timebuf.hh"
|
||||||
#include "mem/packet.hh"
|
#include "mem/packet.hh"
|
||||||
|
@ -599,12 +601,19 @@ class InOrderCPU : public BaseCPU
|
||||||
|
|
||||||
RegType inline getRegType(RegIndex reg_idx)
|
RegType inline getRegType(RegIndex reg_idx)
|
||||||
{
|
{
|
||||||
if (reg_idx < TheISA::FP_Base_DepTag)
|
switch (regIdxToClass(reg_idx)) {
|
||||||
|
case IntRegClass:
|
||||||
return IntType;
|
return IntType;
|
||||||
else if (reg_idx < TheISA::Ctrl_Base_DepTag)
|
|
||||||
|
case FloatRegClass:
|
||||||
return FloatType;
|
return FloatType;
|
||||||
else
|
|
||||||
|
case MiscRegClass:
|
||||||
return MiscType;
|
return MiscType;
|
||||||
|
|
||||||
|
default:
|
||||||
|
panic("register %d out of range\n", reg_idx);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
RegIndex flattenRegIdx(RegIndex reg_idx, RegType ®_type, ThreadID tid);
|
RegIndex flattenRegIdx(RegIndex reg_idx, RegType ®_type, ThreadID tid);
|
||||||
|
|
|
@ -1,5 +1,6 @@
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2007 MIPS Technologies, Inc.
|
* Copyright (c) 2007 MIPS Technologies, Inc.
|
||||||
|
* Copyright (c) 2013 Advanced Micro Devices, Inc.
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
@ -42,6 +43,7 @@
|
||||||
#include "cpu/inorder/cpu.hh"
|
#include "cpu/inorder/cpu.hh"
|
||||||
#include "cpu/inorder/inorder_dyn_inst.hh"
|
#include "cpu/inorder/inorder_dyn_inst.hh"
|
||||||
#include "cpu/exetrace.hh"
|
#include "cpu/exetrace.hh"
|
||||||
|
#include "cpu/reg_class.hh"
|
||||||
#include "debug/InOrderDynInst.hh"
|
#include "debug/InOrderDynInst.hh"
|
||||||
#include "mem/request.hh"
|
#include "mem/request.hh"
|
||||||
#include "sim/fault_fwd.hh"
|
#include "sim/fault_fwd.hh"
|
||||||
|
@ -473,14 +475,21 @@ InOrderDynInst::readRegOtherThread(unsigned reg_idx, ThreadID tid)
|
||||||
tid = TheISA::getTargetThread(this->cpu->tcBase(threadNumber));
|
tid = TheISA::getTargetThread(this->cpu->tcBase(threadNumber));
|
||||||
}
|
}
|
||||||
|
|
||||||
if (reg_idx < FP_Base_DepTag) { // Integer Register File
|
RegIndex rel_idx;
|
||||||
return this->cpu->readIntReg(reg_idx, tid);
|
|
||||||
} else if (reg_idx < Ctrl_Base_DepTag) { // Float Register File
|
switch (regIdxToClass(reg_idx, &rel_idx)) {
|
||||||
reg_idx -= FP_Base_DepTag;
|
case IntRegClass:
|
||||||
return this->cpu->readFloatRegBits(reg_idx, tid);
|
return this->cpu->readIntReg(rel_idx, tid);
|
||||||
} else {
|
|
||||||
reg_idx -= Ctrl_Base_DepTag;
|
case FloatRegClass:
|
||||||
return this->cpu->readMiscReg(reg_idx, tid); // Misc. Register File
|
return this->cpu->readFloatRegBits(rel_idx, tid);
|
||||||
|
|
||||||
|
case MiscRegClass:
|
||||||
|
return this->cpu->readMiscReg(rel_idx, tid); // Misc. Register File
|
||||||
|
|
||||||
|
default:
|
||||||
|
panic("register %d out of range\n", reg_idx);
|
||||||
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -542,14 +551,20 @@ InOrderDynInst::setRegOtherThread(unsigned reg_idx, const MiscReg &val,
|
||||||
tid = TheISA::getTargetThread(this->cpu->tcBase(threadNumber));
|
tid = TheISA::getTargetThread(this->cpu->tcBase(threadNumber));
|
||||||
}
|
}
|
||||||
|
|
||||||
if (reg_idx < FP_Base_DepTag) { // Integer Register File
|
RegIndex rel_idx;
|
||||||
this->cpu->setIntReg(reg_idx, val, tid);
|
|
||||||
} else if (reg_idx < Ctrl_Base_DepTag) { // Float Register File
|
switch (regIdxToClass(reg_idx, &rel_idx)) {
|
||||||
reg_idx -= FP_Base_DepTag;
|
case IntRegClass:
|
||||||
this->cpu->setFloatRegBits(reg_idx, val, tid);
|
this->cpu->setIntReg(rel_idx, val, tid);
|
||||||
} else {
|
break;
|
||||||
reg_idx -= Ctrl_Base_DepTag;
|
|
||||||
this->cpu->setMiscReg(reg_idx, val, tid); // Misc. Register File
|
case FloatRegClass:
|
||||||
|
this->cpu->setFloatRegBits(rel_idx, val, tid);
|
||||||
|
break;
|
||||||
|
|
||||||
|
case MiscRegClass:
|
||||||
|
this->cpu->setMiscReg(rel_idx, val, tid); // Misc. Register File
|
||||||
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -1,5 +1,6 @@
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2010 ARM Limited
|
* Copyright (c) 2010 ARM Limited
|
||||||
|
* Copyright (c) 2013 Advanced Micro Devices, Inc.
|
||||||
* All rights reserved
|
* All rights reserved
|
||||||
*
|
*
|
||||||
* The license below extends only to copyright in the software and shall
|
* The license below extends only to copyright in the software and shall
|
||||||
|
@ -49,6 +50,7 @@
|
||||||
#include "cpu/o3/isa_specific.hh"
|
#include "cpu/o3/isa_specific.hh"
|
||||||
#include "cpu/base_dyn_inst.hh"
|
#include "cpu/base_dyn_inst.hh"
|
||||||
#include "cpu/inst_seq.hh"
|
#include "cpu/inst_seq.hh"
|
||||||
|
#include "cpu/reg_class.hh"
|
||||||
|
|
||||||
class Packet;
|
class Packet;
|
||||||
|
|
||||||
|
@ -209,11 +211,21 @@ class BaseO3DynInst : public BaseDynInst<Impl>
|
||||||
|
|
||||||
for (int idx = 0; idx < this->numDestRegs(); idx++) {
|
for (int idx = 0; idx < this->numDestRegs(); idx++) {
|
||||||
PhysRegIndex prev_phys_reg = this->prevDestRegIdx(idx);
|
PhysRegIndex prev_phys_reg = this->prevDestRegIdx(idx);
|
||||||
TheISA::RegIndex original_dest_reg = this->staticInst->destRegIdx(idx);
|
TheISA::RegIndex original_dest_reg =
|
||||||
if (original_dest_reg < TheISA::FP_Base_DepTag)
|
this->staticInst->destRegIdx(idx);
|
||||||
this->setIntRegOperand(this->staticInst.get(), idx, this->cpu->readIntReg(prev_phys_reg));
|
switch (regIdxToClass(original_dest_reg)) {
|
||||||
else if (original_dest_reg < TheISA::Ctrl_Base_DepTag)
|
case IntRegClass:
|
||||||
this->setFloatRegOperandBits(this->staticInst.get(), idx, this->cpu->readFloatRegBits(prev_phys_reg));
|
this->setIntRegOperand(this->staticInst.get(), idx,
|
||||||
|
this->cpu->readIntReg(prev_phys_reg));
|
||||||
|
break;
|
||||||
|
case FloatRegClass:
|
||||||
|
this->setFloatRegOperandBits(this->staticInst.get(), idx,
|
||||||
|
this->cpu->readFloatRegBits(prev_phys_reg));
|
||||||
|
break;
|
||||||
|
case MiscRegClass:
|
||||||
|
// no need to forward misc reg values
|
||||||
|
break;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
/** Calls hardware return from error interrupt. */
|
/** Calls hardware return from error interrupt. */
|
||||||
|
|
|
@ -1,5 +1,6 @@
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2010-2012 ARM Limited
|
* Copyright (c) 2010-2012 ARM Limited
|
||||||
|
* Copyright (c) 2013 Advanced Micro Devices, Inc.
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
*
|
*
|
||||||
* The license below extends only to copyright in the software and shall
|
* The license below extends only to copyright in the software and shall
|
||||||
|
@ -47,6 +48,7 @@
|
||||||
#include "arch/registers.hh"
|
#include "arch/registers.hh"
|
||||||
#include "config/the_isa.hh"
|
#include "config/the_isa.hh"
|
||||||
#include "cpu/o3/rename.hh"
|
#include "cpu/o3/rename.hh"
|
||||||
|
#include "cpu/reg_class.hh"
|
||||||
#include "debug/Activity.hh"
|
#include "debug/Activity.hh"
|
||||||
#include "debug/Rename.hh"
|
#include "debug/Rename.hh"
|
||||||
#include "debug/O3PipeView.hh"
|
#include "debug/O3PipeView.hh"
|
||||||
|
@ -948,22 +950,29 @@ DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid)
|
||||||
for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
|
for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
|
||||||
RegIndex src_reg = inst->srcRegIdx(src_idx);
|
RegIndex src_reg = inst->srcRegIdx(src_idx);
|
||||||
RegIndex flat_src_reg = src_reg;
|
RegIndex flat_src_reg = src_reg;
|
||||||
if (src_reg < TheISA::FP_Base_DepTag) {
|
switch (regIdxToClass(src_reg)) {
|
||||||
|
case IntRegClass:
|
||||||
flat_src_reg = inst->tcBase()->flattenIntIndex(src_reg);
|
flat_src_reg = inst->tcBase()->flattenIntIndex(src_reg);
|
||||||
DPRINTF(Rename, "Flattening index %d to %d.\n",
|
DPRINTF(Rename, "Flattening index %d to %d.\n",
|
||||||
(int)src_reg, (int)flat_src_reg);
|
(int)src_reg, (int)flat_src_reg);
|
||||||
} else if (src_reg < TheISA::Ctrl_Base_DepTag) {
|
break;
|
||||||
|
|
||||||
|
case FloatRegClass:
|
||||||
src_reg = src_reg - TheISA::FP_Base_DepTag;
|
src_reg = src_reg - TheISA::FP_Base_DepTag;
|
||||||
flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg);
|
flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg);
|
||||||
DPRINTF(Rename, "Flattening index %d to %d.\n",
|
DPRINTF(Rename, "Flattening index %d to %d.\n",
|
||||||
(int)src_reg, (int)flat_src_reg);
|
(int)src_reg, (int)flat_src_reg);
|
||||||
flat_src_reg += TheISA::NumIntRegs;
|
flat_src_reg += TheISA::NumIntRegs;
|
||||||
} else if (src_reg < TheISA::Max_DepTag) {
|
break;
|
||||||
|
|
||||||
|
case MiscRegClass:
|
||||||
flat_src_reg = src_reg - TheISA::Ctrl_Base_DepTag +
|
flat_src_reg = src_reg - TheISA::Ctrl_Base_DepTag +
|
||||||
TheISA::NumFloatRegs + TheISA::NumIntRegs;
|
TheISA::NumFloatRegs + TheISA::NumIntRegs;
|
||||||
DPRINTF(Rename, "Adjusting reg index from %d to %d.\n",
|
DPRINTF(Rename, "Adjusting reg index from %d to %d.\n",
|
||||||
src_reg, flat_src_reg);
|
src_reg, flat_src_reg);
|
||||||
} else {
|
break;
|
||||||
|
|
||||||
|
default:
|
||||||
panic("Reg index is out of bound: %d.", src_reg);
|
panic("Reg index is out of bound: %d.", src_reg);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -1005,25 +1014,32 @@ DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid)
|
||||||
for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
|
for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
|
||||||
RegIndex dest_reg = inst->destRegIdx(dest_idx);
|
RegIndex dest_reg = inst->destRegIdx(dest_idx);
|
||||||
RegIndex flat_dest_reg = dest_reg;
|
RegIndex flat_dest_reg = dest_reg;
|
||||||
if (dest_reg < TheISA::FP_Base_DepTag) {
|
switch (regIdxToClass(dest_reg)) {
|
||||||
|
case IntRegClass:
|
||||||
// Integer registers are flattened.
|
// Integer registers are flattened.
|
||||||
flat_dest_reg = inst->tcBase()->flattenIntIndex(dest_reg);
|
flat_dest_reg = inst->tcBase()->flattenIntIndex(dest_reg);
|
||||||
DPRINTF(Rename, "Flattening index %d to %d.\n",
|
DPRINTF(Rename, "Flattening index %d to %d.\n",
|
||||||
(int)dest_reg, (int)flat_dest_reg);
|
(int)dest_reg, (int)flat_dest_reg);
|
||||||
} else if (dest_reg < TheISA::Ctrl_Base_DepTag) {
|
break;
|
||||||
|
|
||||||
|
case FloatRegClass:
|
||||||
dest_reg = dest_reg - TheISA::FP_Base_DepTag;
|
dest_reg = dest_reg - TheISA::FP_Base_DepTag;
|
||||||
flat_dest_reg = inst->tcBase()->flattenFloatIndex(dest_reg);
|
flat_dest_reg = inst->tcBase()->flattenFloatIndex(dest_reg);
|
||||||
DPRINTF(Rename, "Flattening index %d to %d.\n",
|
DPRINTF(Rename, "Flattening index %d to %d.\n",
|
||||||
(int)dest_reg, (int)flat_dest_reg);
|
(int)dest_reg, (int)flat_dest_reg);
|
||||||
flat_dest_reg += TheISA::NumIntRegs;
|
flat_dest_reg += TheISA::NumIntRegs;
|
||||||
} else if (dest_reg < TheISA::Max_DepTag) {
|
break;
|
||||||
|
|
||||||
|
case MiscRegClass:
|
||||||
// Floating point and Miscellaneous registers need their indexes
|
// Floating point and Miscellaneous registers need their indexes
|
||||||
// adjusted to account for the expanded number of flattened int regs.
|
// adjusted to account for the expanded number of flattened int regs.
|
||||||
flat_dest_reg = dest_reg - TheISA::Ctrl_Base_DepTag +
|
flat_dest_reg = dest_reg - TheISA::Ctrl_Base_DepTag +
|
||||||
TheISA::NumIntRegs + TheISA::NumFloatRegs;
|
TheISA::NumIntRegs + TheISA::NumFloatRegs;
|
||||||
DPRINTF(Rename, "Adjusting reg index from %d to %d.\n",
|
DPRINTF(Rename, "Adjusting reg index from %d to %d.\n",
|
||||||
dest_reg, flat_dest_reg);
|
dest_reg, flat_dest_reg);
|
||||||
} else {
|
break;
|
||||||
|
|
||||||
|
default:
|
||||||
panic("Reg index is out of bound: %d.", dest_reg);
|
panic("Reg index is out of bound: %d.", dest_reg);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -1034,7 +1050,7 @@ DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid)
|
||||||
rename_result = renameMap[tid]->rename(flat_dest_reg);
|
rename_result = renameMap[tid]->rename(flat_dest_reg);
|
||||||
|
|
||||||
//Mark Scoreboard entry as not ready
|
//Mark Scoreboard entry as not ready
|
||||||
if (dest_reg < TheISA::Ctrl_Base_DepTag)
|
if (regIdxToClass(dest_reg) != MiscRegClass)
|
||||||
scoreboard->unsetReg(rename_result.first);
|
scoreboard->unsetReg(rename_result.first);
|
||||||
|
|
||||||
DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical "
|
DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical "
|
||||||
|
|
37
src/cpu/reg_class.cc
Normal file
37
src/cpu/reg_class.cc
Normal file
|
@ -0,0 +1,37 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2013 Advanced Micro Devices, Inc.
|
||||||
|
* All rights reserved
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
* Authors: Steve Reinhardt
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "cpu/reg_class.hh"
|
||||||
|
|
||||||
|
const char *RegClassStrings[] = {
|
||||||
|
"IntRegClass",
|
||||||
|
"FloatRegClass",
|
||||||
|
"MiscRegClass"
|
||||||
|
};
|
92
src/cpu/reg_class.hh
Normal file
92
src/cpu/reg_class.hh
Normal file
|
@ -0,0 +1,92 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2013 Advanced Micro Devices, Inc.
|
||||||
|
* All rights reserved
|
||||||
|
*.
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
* Authors: Steve Reinhardt
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CPU__REG_CLASS_HH__
|
||||||
|
#define __CPU__REG_CLASS_HH__
|
||||||
|
|
||||||
|
#include <cassert>
|
||||||
|
#include <cstddef>
|
||||||
|
|
||||||
|
#include "arch/registers.hh"
|
||||||
|
#include "config/the_isa.hh"
|
||||||
|
|
||||||
|
/// Enumerate the classes of registers.
|
||||||
|
enum RegClass {
|
||||||
|
IntRegClass, ///< Integer register
|
||||||
|
FloatRegClass, ///< Floating-point register
|
||||||
|
MiscRegClass ///< Control (misc) register
|
||||||
|
};
|
||||||
|
|
||||||
|
/// Number of register classes. This value is not part of the enum,
|
||||||
|
/// because putting it there makes the compiler complain about
|
||||||
|
/// unhandled cases in some switch statements.
|
||||||
|
const int NumRegClasses = MiscRegClass + 1;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Map a 'unified' architectural register index to its register class.
|
||||||
|
* The unified architectural register index space is used to represent
|
||||||
|
* all architectural register identifiers in a single contiguous
|
||||||
|
* index space. See http://gem5.org/Register_Indexing.
|
||||||
|
*
|
||||||
|
* @param reg_idx Unified-space register index
|
||||||
|
* @param rel_reg_idx Optional output param pointer; if non-NULL, location
|
||||||
|
* will be written with the relative register index for reg_idx
|
||||||
|
*
|
||||||
|
* @return Register class of reg_idx
|
||||||
|
*/
|
||||||
|
inline
|
||||||
|
RegClass regIdxToClass(TheISA::RegIndex reg_idx,
|
||||||
|
TheISA::RegIndex *rel_reg_idx = NULL)
|
||||||
|
{
|
||||||
|
assert(reg_idx < TheISA::Max_DepTag);
|
||||||
|
RegClass cl;
|
||||||
|
int offset;
|
||||||
|
|
||||||
|
if (reg_idx < TheISA::FP_Base_DepTag) {
|
||||||
|
cl = IntRegClass;
|
||||||
|
offset = 0;
|
||||||
|
} else if (reg_idx < TheISA::Ctrl_Base_DepTag) {
|
||||||
|
cl = FloatRegClass;
|
||||||
|
offset = TheISA::FP_Base_DepTag;
|
||||||
|
} else {
|
||||||
|
cl = MiscRegClass;
|
||||||
|
offset = TheISA::Ctrl_Base_DepTag;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (rel_reg_idx)
|
||||||
|
*rel_reg_idx = reg_idx - offset;
|
||||||
|
return cl;
|
||||||
|
}
|
||||||
|
|
||||||
|
/// Map enum values to strings for debugging
|
||||||
|
extern const char *RegClassStrings[];
|
||||||
|
|
||||||
|
|
||||||
|
#endif // __CPU__REG_CLASS_HH__
|
Loading…
Reference in a new issue