sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

added some comments

Browse source 
--HG--
extra : convert_revision : b33c94984f8d9ac2baf8d7b45fa79460846b1755
This commit is contained in:
Ali Saidi 2004-02-05 13:05:20 -05:00
parent 69e1e10f5d
commit 7a6a435983
4 changed files with 33 additions and 9 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
dev/tsunami.cc
View file

@ -80,7 +80,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(Tsunami)
INIT_PARAM(ethernet, "ethernet controller"), INIT_PARAM(ethernet, "ethernet controller"),
INIT_PARAM(cons, "system console"), INIT_PARAM(cons, "system console"),
INIT_PARAM(intrctrl, "interrupt controller"), INIT_PARAM(intrctrl, "interrupt controller"),
INIT_PARAM_DFLT(interrupt_frequency, "frequency of interrupts", 1200) INIT_PARAM_DFLT(interrupt_frequency, "frequency of interrupts", 1024)
END_INIT_SIM_OBJECT_PARAMS(Tsunami) END_INIT_SIM_OBJECT_PARAMS(Tsunami)

16
dev/tsunami.hh
View file

@ -28,8 +28,8 @@
/** /**
* @file * @file
* Declaration of top level class for the Tsunami chipset. This class just retains pointers * Declaration of top level class for the Tsunami chipset. This class just
* to all its children so the children can communicate * retains pointers to all its children so the children can communicate.
*/ */
#ifndef __TSUNAMI_HH__ #ifndef __TSUNAMI_HH__
@ -45,7 +45,7 @@ class TlaserClock;
class EtherDev; class EtherDev;
class TsunamiCChip; class TsunamiCChip;
class TsunamiPChip; class TsunamiPChip;
class TsunamiPCIConfig; class PCIConfigAll;
/** /**
* Top level class for Tsunami Chipset emulation. * Top level class for Tsunami Chipset emulation.
@ -87,7 +87,7 @@ class Tsunami : public SimObject
* The config space in tsunami all needs to return * The config space in tsunami all needs to return
* -1 if a device is not there. * -1 if a device is not there.
*/ */
TsunamiPCIConfig *pciconfig; PCIConfigAll *pciconfig;
int intr_sum_type[Tsunami::Max_CPUs]; int intr_sum_type[Tsunami::Max_CPUs];
int ipi_pending[Tsunami::Max_CPUs]; int ipi_pending[Tsunami::Max_CPUs];
@ -97,11 +97,15 @@ class Tsunami : public SimObject
public: public:
/** /**
* Constructor for the Tsunami Class. * Constructor for the Tsunami Class.
* @param * @param name name of the object
* @param scsi pointer to scsi controller object
* @param con pointer to the console
* @param intrcontrol pointer to the interrupt controller
* @param intrFreq frequency that interrupts happen
*/ */
Tsunami(const std::string &name, AdaptecController *scsi, Tsunami(const std::string &name, AdaptecController *scsi,
EtherDev *ethernet, EtherDev *ethernet,
SimConsole *, IntrControl *intctrl, int intrFreq); SimConsole *con, IntrControl *intctrl, int intrFreq);
virtual void serialize(std::ostream &os); virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string &section); virtual void unserialize(Checkpoint *cp, const std::string &section);

2
dev/tsunami_cchip.cc
View file

@ -1,7 +1,7 @@
/* $Id$ */ /* $Id$ */
/* @file /* @file
* Tsunami CChip (processor, memory, or IO) * Emulation of the Tsunami CChip CSRs
*/ */
#include <deque> #include <deque>

22
dev/tsunami_cchip.hh
View file

@ -27,7 +27,7 @@
*/ */
/* @file /* @file
* Turbolaser system bus node (processor, memory, or IO) * Emulation of the Tsunami CChip CSRs
*/ */
#ifndef __TSUNAMI_CCHIP_HH__ #ifndef __TSUNAMI_CCHIP_HH__
@ -44,10 +44,30 @@ class TsunamiCChip : public MmapDevice
public: public:
protected: protected:
/**
* pointer to the tsunami object.
* This is our access to all the other tsunami
* devices.
*/
Tsunami *tsunami; Tsunami *tsunami;
/**
* The dims are device interrupt mask registers.
* One exists for each CPU, the DRIR X DIM = DIR
*/
uint64_t dim[Tsunami::Max_CPUs]; uint64_t dim[Tsunami::Max_CPUs];
/**
* The dirs are device interrupt registers.
* One exists for each CPU, the DRIR X DIM = DIR
*/
uint64_t dir[Tsunami::Max_CPUs]; uint64_t dir[Tsunami::Max_CPUs];
bool dirInterrupting[Tsunami::Max_CPUs]; bool dirInterrupting[Tsunami::Max_CPUs];
/**
* This register contains bits for each PCI interrupt
* that can occur.
*/
uint64_t drir; uint64_t drir;
public: public: