Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/z/stever/bk/multiarch arch/isa_parser.py: SCCS merged --HG-- extra : convert_revision : 080cca7616b37db3bf18976b63b3dbcb47d8b918
This commit is contained in:
commit
7a37037358
19 changed files with 479 additions and 273 deletions
163
SConscript
163
SConscript
|
@ -86,31 +86,7 @@ base_sources = Split('''
|
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cpu/exetrace.cc
|
cpu/exetrace.cc
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||||||
cpu/pc_event.cc
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cpu/pc_event.cc
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cpu/static_inst.cc
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cpu/static_inst.cc
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cpu/o3/2bit_local_pred.cc
|
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cpu/o3/alpha_dyn_inst.cc
|
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cpu/o3/alpha_cpu.cc
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cpu/o3/alpha_cpu_builder.cc
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cpu/o3/bpred_unit.cc
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cpu/o3/btb.cc
|
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cpu/o3/commit.cc
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cpu/o3/decode.cc
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cpu/o3/fetch.cc
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cpu/o3/free_list.cc
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cpu/o3/cpu.cc
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cpu/o3/iew.cc
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cpu/o3/inst_queue.cc
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cpu/o3/ldstq.cc
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cpu/o3/mem_dep_unit.cc
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cpu/o3/ras.cc
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cpu/o3/rename.cc
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cpu/o3/rename_map.cc
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cpu/o3/rob.cc
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cpu/o3/sat_counter.cc
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cpu/o3/store_set.cc
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cpu/o3/tournament_pred.cc
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cpu/fast/cpu.cc
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cpu/sampler/sampler.cc
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cpu/sampler/sampler.cc
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cpu/simple/cpu.cc
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cpu/trace/reader/mem_trace_reader.cc
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cpu/trace/reader/mem_trace_reader.cc
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cpu/trace/reader/ibm_reader.cc
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cpu/trace/reader/ibm_reader.cc
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cpu/trace/reader/itx_reader.cc
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cpu/trace/reader/itx_reader.cc
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|
@ -118,41 +94,6 @@ base_sources = Split('''
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cpu/trace/opt_cpu.cc
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cpu/trace/opt_cpu.cc
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cpu/trace/trace_cpu.cc
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cpu/trace/trace_cpu.cc
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|
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encumbered/cpu/full/bpred.cc
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encumbered/cpu/full/commit.cc
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encumbered/cpu/full/cpu.cc
|
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encumbered/cpu/full/create_vector.cc
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encumbered/cpu/full/cv_spec_state.cc
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encumbered/cpu/full/dd_queue.cc
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encumbered/cpu/full/dep_link.cc
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encumbered/cpu/full/dispatch.cc
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encumbered/cpu/full/dyn_inst.cc
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encumbered/cpu/full/execute.cc
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encumbered/cpu/full/fetch.cc
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encumbered/cpu/full/floss_reasons.cc
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encumbered/cpu/full/fu_pool.cc
|
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encumbered/cpu/full/inst_fifo.cc
|
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encumbered/cpu/full/instpipe.cc
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encumbered/cpu/full/issue.cc
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encumbered/cpu/full/ls_queue.cc
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encumbered/cpu/full/machine_queue.cc
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encumbered/cpu/full/pipetrace.cc
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encumbered/cpu/full/readyq.cc
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encumbered/cpu/full/reg_info.cc
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encumbered/cpu/full/rob_station.cc
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encumbered/cpu/full/spec_memory.cc
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encumbered/cpu/full/spec_state.cc
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encumbered/cpu/full/storebuffer.cc
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encumbered/cpu/full/writeback.cc
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encumbered/cpu/full/iq/iq_station.cc
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encumbered/cpu/full/iq/iqueue.cc
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encumbered/cpu/full/iq/segmented/chain_info.cc
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encumbered/cpu/full/iq/segmented/chain_wire.cc
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encumbered/cpu/full/iq/segmented/iq_seg.cc
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encumbered/cpu/full/iq/segmented/iq_segmented.cc
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encumbered/cpu/full/iq/segmented/seg_chain.cc
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encumbered/cpu/full/iq/seznec/iq_seznec.cc
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encumbered/cpu/full/iq/standard/iq_standard.cc
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encumbered/mem/functional/main.cc
|
encumbered/mem/functional/main.cc
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||||||
|
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mem/base_hier.cc
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mem/base_hier.cc
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|
@ -224,6 +165,45 @@ base_sources = Split('''
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sim/trace_context.cc
|
sim/trace_context.cc
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''')
|
''')
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|
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|
# Old FullCPU sources
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||||||
|
full_cpu_sources = Split('''
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||||||
|
encumbered/cpu/full/bpred.cc
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||||||
|
encumbered/cpu/full/commit.cc
|
||||||
|
encumbered/cpu/full/cpu.cc
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|
encumbered/cpu/full/create_vector.cc
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||||||
|
encumbered/cpu/full/cv_spec_state.cc
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|
encumbered/cpu/full/dd_queue.cc
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|
encumbered/cpu/full/dep_link.cc
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|
encumbered/cpu/full/dispatch.cc
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|
encumbered/cpu/full/dyn_inst.cc
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|
encumbered/cpu/full/execute.cc
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|
encumbered/cpu/full/fetch.cc
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|
encumbered/cpu/full/floss_reasons.cc
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|
encumbered/cpu/full/fu_pool.cc
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||||||
|
encumbered/cpu/full/inst_fifo.cc
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||||||
|
encumbered/cpu/full/instpipe.cc
|
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|
encumbered/cpu/full/issue.cc
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|
encumbered/cpu/full/ls_queue.cc
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|
encumbered/cpu/full/machine_queue.cc
|
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|
encumbered/cpu/full/pipetrace.cc
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|
encumbered/cpu/full/readyq.cc
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|
encumbered/cpu/full/reg_info.cc
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||||||
|
encumbered/cpu/full/rob_station.cc
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|
encumbered/cpu/full/spec_memory.cc
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||||||
|
encumbered/cpu/full/spec_state.cc
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|
encumbered/cpu/full/storebuffer.cc
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||||||
|
encumbered/cpu/full/writeback.cc
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||||||
|
encumbered/cpu/full/iq/iq_station.cc
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||||||
|
encumbered/cpu/full/iq/iqueue.cc
|
||||||
|
encumbered/cpu/full/iq/segmented/chain_info.cc
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||||||
|
encumbered/cpu/full/iq/segmented/chain_wire.cc
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|
encumbered/cpu/full/iq/segmented/iq_seg.cc
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|
encumbered/cpu/full/iq/segmented/iq_segmented.cc
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|
encumbered/cpu/full/iq/segmented/seg_chain.cc
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|
encumbered/cpu/full/iq/seznec/iq_seznec.cc
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|
encumbered/cpu/full/iq/standard/iq_standard.cc
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|
''')
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|
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# MySql sources
|
# MySql sources
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||||||
mysql_sources = Split('''
|
mysql_sources = Split('''
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||||||
base/mysql.cc
|
base/mysql.cc
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||||||
|
@ -320,6 +300,11 @@ syscall_emulation_sources = Split('''
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sim/syscall_emul.cc
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sim/syscall_emul.cc
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||||||
''')
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''')
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|
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# The following stuff (targetarch code and global define of THE_ISA)
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# are legacy things that assume we're only compiling one ISA at a
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# time. These will have to go away if we want to build a binary that
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# supports multiple ISAs.
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|
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targetarch_files = Split('''
|
targetarch_files = Split('''
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alpha_linux_process.hh
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alpha_linux_process.hh
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alpha_memory.hh
|
alpha_memory.hh
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@ -338,18 +323,22 @@ for f in targetarch_files:
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env.Command('targetarch/' + f, 'arch/%s/%s' % (env['TARGET_ISA'], f),
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env.Command('targetarch/' + f, 'arch/%s/%s' % (env['TARGET_ISA'], f),
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||||||
'''echo '#include "arch/%s/%s"' > $TARGET''' % (env['TARGET_ISA'], f))
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'''echo '#include "arch/%s/%s"' > $TARGET''' % (env['TARGET_ISA'], f))
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||||||
|
|
||||||
# Let the target architecture define what sources it needs
|
|
||||||
arch_source = SConscript('arch/%s/SConscript' % env['TARGET_ISA'],
|
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||||||
build_dir = 'build/%s/' % env['BUILD_DIR'],
|
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||||||
exports = 'env', duplicate = False)
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|
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# Add a flag defining what THE_ISA should be for all compilation
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# Add a flag defining what THE_ISA should be for all compilation
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env.Append(CPPDEFINES=[('THE_ISA','%s_ISA' % env['TARGET_ISA'].upper())])
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env.Append(CPPDEFINES=[('THE_ISA','%s_ISA' % env['TARGET_ISA'].upper())])
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|
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SConscript('arch/SConscript', exports = 'env', duplicate = False)
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arch_sources = SConscript('arch/SConscript',
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|
exports = 'env', duplicate = False)
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|
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|
cpu_sources = SConscript('cpu/SConscript',
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|
exports = 'env', duplicate = False)
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|
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||||||
|
# This is outside of cpu/SConscript since the source directory isn't
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|
# underneath 'cpu'.
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|
if 'FullCPU' in env['CPU_MODELS']:
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|
cpu_sources += full_cpu_sources
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|
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||||||
# Set up complete list of sources based on configuration.
|
# Set up complete list of sources based on configuration.
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||||||
sources = base_sources + arch_source
|
sources = base_sources + arch_sources + cpu_sources
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||||||
|
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if env['FULL_SYSTEM']:
|
if env['FULL_SYSTEM']:
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sources += full_system_sources
|
sources += full_system_sources
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||||||
|
@ -364,27 +353,6 @@ if env['USE_MYSQL']:
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for opt in env.ExportOptions:
|
for opt in env.ExportOptions:
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env.ConfigFile(opt)
|
env.ConfigFile(opt)
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|
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||||||
###################################################
|
|
||||||
#
|
|
||||||
# Add an SCons scanner for ISA files
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#
|
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###################################################
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import SCons.Scanner
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def ISAScan():
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return SCons.Scanner.Classic("ISAScan",
|
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"$ISASUFFIXES",
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"SRCDIR",
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'^[ \t]*##[ \t]*include[ \t]*"([^>"]+)"')
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|
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def ISAPath(env, dir, target=None, source=None, a=None):
|
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return (Dir(env['SRCDIR']), Dir('.'))
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iscan = Scanner(function = ISAScan().scan, skeys = [".isa", ".ISA"],
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path_function = ISAPath)
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env.Append(SCANNERS = iscan)
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|
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|
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###################################################
|
###################################################
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#
|
#
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# Special build rules.
|
# Special build rules.
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|
@ -397,27 +365,6 @@ env.Command(Split('base/traceflags.hh base/traceflags.cc'),
|
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'base/traceflags.py',
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'base/traceflags.py',
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'python $SOURCE $TARGET.base')
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'python $SOURCE $TARGET.base')
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# several files are generated from arch/$TARGET_ISA/isa_desc.
|
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env.Command(Split('''
|
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arch/%s/decoder.cc
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arch/%s/decoder.hh
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arch/%s/alpha_o3_exec.cc
|
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arch/%s/fast_cpu_exec.cc
|
|
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arch/%s/simple_cpu_exec.cc
|
|
||||||
arch/%s/full_cpu_exec.cc''' %
|
|
||||||
(env['TARGET_ISA'],
|
|
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env['TARGET_ISA'],
|
|
||||||
env['TARGET_ISA'],
|
|
||||||
env['TARGET_ISA'],
|
|
||||||
env['TARGET_ISA'],
|
|
||||||
env['TARGET_ISA'])),
|
|
||||||
Split('''
|
|
||||||
arch/%s/isa/main.isa
|
|
||||||
arch/isa_parser.py''' %
|
|
||||||
env['TARGET_ISA']),
|
|
||||||
'$SRCDIR/arch/isa_parser.py $SOURCE $TARGET.dir arch/%s' % env['TARGET_ISA'])
|
|
||||||
|
|
||||||
|
|
||||||
# libelf build is described in its own SConscript file.
|
# libelf build is described in its own SConscript file.
|
||||||
# SConscript-local is the per-config build, which just copies some
|
# SConscript-local is the per-config build, which just copies some
|
||||||
# header files into a place where they can be found.
|
# header files into a place where they can be found.
|
||||||
|
|
|
@ -31,11 +31,17 @@ import os.path
|
||||||
# Import build environment variable from SConstruct.
|
# Import build environment variable from SConstruct.
|
||||||
Import('env')
|
Import('env')
|
||||||
|
|
||||||
|
# Right now there are no source files immediately in this directory
|
||||||
|
sources = []
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||||||
|
|
||||||
|
#################################################################
|
||||||
#
|
#
|
||||||
# ISA "switch header" generation.
|
# ISA "switch header" generation.
|
||||||
#
|
#
|
||||||
# Auto-generate arch headers that include the right ISA-specific
|
# Auto-generate arch headers that include the right ISA-specific
|
||||||
# header based on the setting of THE_ISA preprocessor variable.
|
# header based on the setting of THE_ISA preprocessor variable.
|
||||||
|
#
|
||||||
|
#################################################################
|
||||||
|
|
||||||
# List of headers to generate
|
# List of headers to generate
|
||||||
isa_switch_hdrs = Split('''
|
isa_switch_hdrs = Split('''
|
||||||
|
@ -72,3 +78,70 @@ switch_hdr_action = Action(gen_switch_hdr, gen_switch_hdr_string,
|
||||||
# Instantiate actions for each header
|
# Instantiate actions for each header
|
||||||
for hdr in isa_switch_hdrs:
|
for hdr in isa_switch_hdrs:
|
||||||
env.Command(hdr, [], switch_hdr_action)
|
env.Command(hdr, [], switch_hdr_action)
|
||||||
|
|
||||||
|
#################################################################
|
||||||
|
#
|
||||||
|
# Include architecture-specific files.
|
||||||
|
#
|
||||||
|
#################################################################
|
||||||
|
|
||||||
|
#
|
||||||
|
# Build a SCons scanner for ISA files
|
||||||
|
#
|
||||||
|
import SCons.Scanner
|
||||||
|
|
||||||
|
def ISAScan():
|
||||||
|
return SCons.Scanner.Classic("ISAScan",
|
||||||
|
"$ISASUFFIXES",
|
||||||
|
"SRCDIR",
|
||||||
|
'^[ \t]*##[ \t]*include[ \t]*"([^>"]+)"')
|
||||||
|
|
||||||
|
def ISAPath(env, dir, target=None, source=None, a=None):
|
||||||
|
return (Dir(env['SRCDIR']), Dir('.'))
|
||||||
|
|
||||||
|
iscan = Scanner(function = ISAScan().scan, skeys = [".isa", ".ISA"],
|
||||||
|
path_function = ISAPath)
|
||||||
|
env.Append(SCANNERS = iscan)
|
||||||
|
|
||||||
|
#
|
||||||
|
# Now create a Builder object that uses isa_parser.py to generate C++
|
||||||
|
# output from the ISA description (*.isa) files.
|
||||||
|
#
|
||||||
|
|
||||||
|
# Convert to File node to fix path
|
||||||
|
isa_parser = File('isa_parser.py')
|
||||||
|
cpu_models_file = File('#m5/cpu/cpu_models.py')
|
||||||
|
|
||||||
|
# This sucks in the defintions of the CpuModel objects.
|
||||||
|
execfile(cpu_models_file.srcnode().abspath)
|
||||||
|
|
||||||
|
# Several files are generated from the ISA description.
|
||||||
|
# We always get the basic decoder and header file.
|
||||||
|
isa_desc_gen_files = Split('decoder.cc decoder.hh')
|
||||||
|
# We also get an execute file for each selected CPU model.
|
||||||
|
isa_desc_gen_files += [CpuModel.dict[cpu].filename
|
||||||
|
for cpu in env['CPU_MODELS']]
|
||||||
|
|
||||||
|
# The emitter patches up the sources & targets to include the
|
||||||
|
# autogenerated files as targets and isa parser itself as a source.
|
||||||
|
def isa_desc_emitter(target, source, env):
|
||||||
|
return (isa_desc_gen_files, [isa_parser, cpu_models_file] + source)
|
||||||
|
|
||||||
|
# Pieces are in place, so create the builder.
|
||||||
|
isa_desc_builder = Builder(action='$SOURCES $TARGET.dir $CPU_MODELS',
|
||||||
|
source_scanner = iscan,
|
||||||
|
emitter = isa_desc_emitter)
|
||||||
|
|
||||||
|
env.Append(BUILDERS = { 'ISADesc' : isa_desc_builder })
|
||||||
|
|
||||||
|
#
|
||||||
|
# Now include other ISA-specific sources from the ISA subdirectories.
|
||||||
|
#
|
||||||
|
|
||||||
|
isa = env['TARGET_ISA'] # someday this may be a list of ISAs
|
||||||
|
|
||||||
|
# Let the target architecture define what additional sources it needs
|
||||||
|
sources += SConscript(os.path.join(isa, 'SConscript'),
|
||||||
|
exports = 'env', duplicate = False)
|
||||||
|
|
||||||
|
Return('sources')
|
||||||
|
|
|
@ -43,40 +43,45 @@ Import('env')
|
||||||
###################################################
|
###################################################
|
||||||
|
|
||||||
# Base sources used by all configurations.
|
# Base sources used by all configurations.
|
||||||
arch_base_sources = Split('''
|
base_sources = Split('''
|
||||||
arch/alpha/decoder.cc
|
faults.cc
|
||||||
arch/alpha/alpha_o3_exec.cc
|
isa_traits.cc
|
||||||
arch/alpha/fast_cpu_exec.cc
|
|
||||||
arch/alpha/simple_cpu_exec.cc
|
|
||||||
arch/alpha/full_cpu_exec.cc
|
|
||||||
arch/alpha/faults.cc
|
|
||||||
arch/alpha/isa_traits.cc
|
|
||||||
''')
|
''')
|
||||||
|
|
||||||
# Full-system sources
|
# Full-system sources
|
||||||
arch_full_system_sources = Split('''
|
full_system_sources = Split('''
|
||||||
arch/alpha/alpha_memory.cc
|
alpha_memory.cc
|
||||||
arch/alpha/arguments.cc
|
arguments.cc
|
||||||
arch/alpha/ev5.cc
|
ev5.cc
|
||||||
arch/alpha/osfpal.cc
|
osfpal.cc
|
||||||
arch/alpha/stacktrace.cc
|
stacktrace.cc
|
||||||
arch/alpha/vtophys.cc
|
vtophys.cc
|
||||||
''')
|
''')
|
||||||
|
|
||||||
|
|
||||||
# Syscall emulation (non-full-system) sources
|
# Syscall emulation (non-full-system) sources
|
||||||
arch_syscall_emulation_sources = Split('''
|
syscall_emulation_sources = Split('''
|
||||||
arch/alpha/alpha_common_syscall_emul.cc
|
alpha_common_syscall_emul.cc
|
||||||
arch/alpha/alpha_linux_process.cc
|
alpha_linux_process.cc
|
||||||
arch/alpha/alpha_tru64_process.cc
|
alpha_tru64_process.cc
|
||||||
''')
|
''')
|
||||||
|
|
||||||
# Set up complete list of sources based on configuration.
|
# Set up complete list of sources based on configuration.
|
||||||
sources = arch_base_sources
|
sources = base_sources
|
||||||
|
|
||||||
if env['FULL_SYSTEM']:
|
if env['FULL_SYSTEM']:
|
||||||
sources += arch_full_system_sources
|
sources += full_system_sources
|
||||||
else:
|
else:
|
||||||
sources += arch_syscall_emulation_sources
|
sources += syscall_emulation_sources
|
||||||
|
|
||||||
|
# Convert file names to SCons File objects. This takes care of the
|
||||||
|
# path relative to the top of the directory tree.
|
||||||
|
sources = [File(s) for s in sources]
|
||||||
|
|
||||||
|
# Add in files generated by the ISA description.
|
||||||
|
isa_desc_files = env.ISADesc('isa/main.isa')
|
||||||
|
# Only non-header files need to be compiled.
|
||||||
|
isa_desc_sources = [f for f in isa_desc_files if not f.path.endswith('.hh')]
|
||||||
|
sources += isa_desc_sources
|
||||||
|
|
||||||
Return('sources')
|
Return('sources')
|
||||||
|
|
|
@ -41,6 +41,31 @@
|
||||||
using namespace std;
|
using namespace std;
|
||||||
using namespace AlphaISA;
|
using namespace AlphaISA;
|
||||||
|
|
||||||
|
/// Target pipe() handler. Even though this is a generic Posix call,
|
||||||
|
/// the Alpha return convention is funky, so that makes it
|
||||||
|
/// Alpha-specific.
|
||||||
|
SyscallReturn
|
||||||
|
pipeFunc(SyscallDesc *desc, int callnum, Process *process,
|
||||||
|
ExecContext *xc)
|
||||||
|
{
|
||||||
|
int fds[2], sim_fds[2];
|
||||||
|
int pipe_retval = pipe(fds);
|
||||||
|
|
||||||
|
if (pipe_retval < 0) {
|
||||||
|
// error
|
||||||
|
return pipe_retval;
|
||||||
|
}
|
||||||
|
|
||||||
|
sim_fds[0] = process->alloc_fd(fds[0]);
|
||||||
|
sim_fds[1] = process->alloc_fd(fds[1]);
|
||||||
|
|
||||||
|
// Alpha Linux convention for pipe() is that fd[0] is returned as
|
||||||
|
// the return value of the function, and fd[1] is returned in r20.
|
||||||
|
xc->regs.intRegFile[20] = sim_fds[1];
|
||||||
|
return sim_fds[0];
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
/// Target uname() handler.
|
/// Target uname() handler.
|
||||||
static SyscallReturn
|
static SyscallReturn
|
||||||
unameFunc(SyscallDesc *desc, int callnum, Process *process,
|
unameFunc(SyscallDesc *desc, int callnum, Process *process,
|
||||||
|
@ -159,7 +184,7 @@ SyscallDesc AlphaLinuxProcess::syscallDescs[] = {
|
||||||
/* 39 */ SyscallDesc("setpgid", unimplementedFunc),
|
/* 39 */ SyscallDesc("setpgid", unimplementedFunc),
|
||||||
/* 40 */ SyscallDesc("osf_old_lstat", unimplementedFunc),
|
/* 40 */ SyscallDesc("osf_old_lstat", unimplementedFunc),
|
||||||
/* 41 */ SyscallDesc("dup", unimplementedFunc),
|
/* 41 */ SyscallDesc("dup", unimplementedFunc),
|
||||||
/* 42 */ SyscallDesc("pipe", unimplementedFunc),
|
/* 42 */ SyscallDesc("pipe", pipeFunc),
|
||||||
/* 43 */ SyscallDesc("osf_set_program_attributes", unimplementedFunc),
|
/* 43 */ SyscallDesc("osf_set_program_attributes", unimplementedFunc),
|
||||||
/* 44 */ SyscallDesc("osf_profil", unimplementedFunc),
|
/* 44 */ SyscallDesc("osf_profil", unimplementedFunc),
|
||||||
/* 45 */ SyscallDesc("open", openFunc<Linux>),
|
/* 45 */ SyscallDesc("open", openFunc<Linux>),
|
||||||
|
|
|
@ -70,12 +70,15 @@ AlphaISA::swap_palshadow(RegFile *regs, bool use_shadow)
|
||||||
// Machine dependent functions
|
// Machine dependent functions
|
||||||
//
|
//
|
||||||
void
|
void
|
||||||
AlphaISA::initCPU(RegFile *regs)
|
AlphaISA::initCPU(RegFile *regs, int cpuId)
|
||||||
{
|
{
|
||||||
initIPRs(regs);
|
initIPRs(regs, cpuId);
|
||||||
// CPU comes up with PAL regs enabled
|
// CPU comes up with PAL regs enabled
|
||||||
swap_palshadow(regs, true);
|
swap_palshadow(regs, true);
|
||||||
|
|
||||||
|
regs->intRegFile[16] = cpuId;
|
||||||
|
regs->intRegFile[0] = cpuId;
|
||||||
|
|
||||||
regs->pc = regs->ipr[IPR_PAL_BASE] + fault_addr(ResetFault);
|
regs->pc = regs->ipr[IPR_PAL_BASE] + fault_addr(ResetFault);
|
||||||
regs->npc = regs->pc + sizeof(MachInst);
|
regs->npc = regs->pc + sizeof(MachInst);
|
||||||
}
|
}
|
||||||
|
@ -106,13 +109,14 @@ const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = {
|
||||||
//
|
//
|
||||||
//
|
//
|
||||||
void
|
void
|
||||||
AlphaISA::initIPRs(RegFile *regs)
|
AlphaISA::initIPRs(RegFile *regs, int cpuId)
|
||||||
{
|
{
|
||||||
uint64_t *ipr = regs->ipr;
|
uint64_t *ipr = regs->ipr;
|
||||||
|
|
||||||
bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg));
|
bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg));
|
||||||
ipr[IPR_PAL_BASE] = PalBase;
|
ipr[IPR_PAL_BASE] = PalBase;
|
||||||
ipr[IPR_MCSR] = 0x6;
|
ipr[IPR_MCSR] = 0x6;
|
||||||
|
ipr[IPR_PALtemp16] = cpuId;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
|
@ -712,44 +712,6 @@ yacc.yacc()
|
||||||
#
|
#
|
||||||
#####################################################################
|
#####################################################################
|
||||||
|
|
||||||
################
|
|
||||||
# CpuModel class
|
|
||||||
#
|
|
||||||
# The CpuModel class encapsulates everything we need to know about a
|
|
||||||
# particular CPU model.
|
|
||||||
|
|
||||||
class CpuModel:
|
|
||||||
# List of all CPU models. Accessible as CpuModel.list.
|
|
||||||
list = []
|
|
||||||
|
|
||||||
# Constructor. Automatically adds models to CpuModel.list.
|
|
||||||
def __init__(self, name, filename, includes, strings):
|
|
||||||
self.name = name
|
|
||||||
self.filename = filename # filename for output exec code
|
|
||||||
self.includes = includes # include files needed in exec file
|
|
||||||
# The 'strings' dict holds all the per-CPU symbols we can
|
|
||||||
# substitute into templates etc.
|
|
||||||
self.strings = strings
|
|
||||||
# Add self to list.
|
|
||||||
CpuModel.list.append(self)
|
|
||||||
|
|
||||||
# Define CPU models. The following lines should contain the only
|
|
||||||
# CPU-model-specific information in this file. Note that the ISA
|
|
||||||
# description itself should have *no* CPU-model-specific content.
|
|
||||||
CpuModel('SimpleCPU', 'simple_cpu_exec.cc',
|
|
||||||
'#include "cpu/simple/cpu.hh"',
|
|
||||||
{ 'CPU_exec_context': 'SimpleCPU' })
|
|
||||||
CpuModel('FastCPU', 'fast_cpu_exec.cc',
|
|
||||||
'#include "cpu/fast/cpu.hh"',
|
|
||||||
{ 'CPU_exec_context': 'FastCPU' })
|
|
||||||
CpuModel('FullCPU', 'full_cpu_exec.cc',
|
|
||||||
'#include "encumbered/cpu/full/dyn_inst.hh"',
|
|
||||||
{ 'CPU_exec_context': 'DynInst' })
|
|
||||||
|
|
||||||
CpuModel('AlphaFullCPU', 'alpha_o3_exec.cc',
|
|
||||||
'#include "cpu/o3/alpha_dyn_inst.hh"',
|
|
||||||
{ 'CPU_exec_context': 'AlphaDynInst<AlphaSimpleImpl>' })
|
|
||||||
|
|
||||||
# Expand template with CPU-specific references into a dictionary with
|
# Expand template with CPU-specific references into a dictionary with
|
||||||
# an entry for each CPU model name. The entry key is the model name
|
# an entry for each CPU model name. The entry key is the model name
|
||||||
# and the corresponding value is the template with the CPU-specific
|
# and the corresponding value is the template with the CPU-specific
|
||||||
|
@ -758,7 +720,7 @@ def expand_cpu_symbols_to_dict(template):
|
||||||
# Protect '%'s that don't go with CPU-specific terms
|
# Protect '%'s that don't go with CPU-specific terms
|
||||||
t = re.sub(r'%(?!\(CPU_)', '%%', template)
|
t = re.sub(r'%(?!\(CPU_)', '%%', template)
|
||||||
result = {}
|
result = {}
|
||||||
for cpu in CpuModel.list:
|
for cpu in cpu_models:
|
||||||
result[cpu.name] = t % cpu.strings
|
result[cpu.name] = t % cpu.strings
|
||||||
return result
|
return result
|
||||||
|
|
||||||
|
@ -817,7 +779,7 @@ class GenCode:
|
||||||
# concatenates all the individual strings in the operands.
|
# concatenates all the individual strings in the operands.
|
||||||
def __add__(self, other):
|
def __add__(self, other):
|
||||||
exec_output = {}
|
exec_output = {}
|
||||||
for cpu in CpuModel.list:
|
for cpu in cpu_models:
|
||||||
n = cpu.name
|
n = cpu.name
|
||||||
exec_output[n] = self.exec_output[n] + other.exec_output[n]
|
exec_output[n] = self.exec_output[n] + other.exec_output[n]
|
||||||
return GenCode(self.header_output + other.header_output,
|
return GenCode(self.header_output + other.header_output,
|
||||||
|
@ -831,7 +793,7 @@ class GenCode:
|
||||||
self.header_output = pre + self.header_output
|
self.header_output = pre + self.header_output
|
||||||
self.decoder_output = pre + self.decoder_output
|
self.decoder_output = pre + self.decoder_output
|
||||||
self.decode_block = pre + self.decode_block
|
self.decode_block = pre + self.decode_block
|
||||||
for cpu in CpuModel.list:
|
for cpu in cpu_models:
|
||||||
self.exec_output[cpu.name] = pre + self.exec_output[cpu.name]
|
self.exec_output[cpu.name] = pre + self.exec_output[cpu.name]
|
||||||
|
|
||||||
# Wrap the decode block in a pair of strings (e.g., 'case foo:'
|
# Wrap the decode block in a pair of strings (e.g., 'case foo:'
|
||||||
|
@ -1752,7 +1714,7 @@ def preprocess_isa_desc(isa_desc):
|
||||||
#
|
#
|
||||||
# Read in and parse the ISA description.
|
# Read in and parse the ISA description.
|
||||||
#
|
#
|
||||||
def parse_isa_desc(isa_desc_file, output_dir, include_path):
|
def parse_isa_desc(isa_desc_file, output_dir):
|
||||||
# set a global var for the input filename... used in error messages
|
# set a global var for the input filename... used in error messages
|
||||||
global input_filename
|
global input_filename
|
||||||
input_filename = isa_desc_file
|
input_filename = isa_desc_file
|
||||||
|
@ -1782,7 +1744,7 @@ def parse_isa_desc(isa_desc_file, output_dir, include_path):
|
||||||
update_if_needed(output_dir + '/decoder.hh', file_template % vars())
|
update_if_needed(output_dir + '/decoder.hh', file_template % vars())
|
||||||
|
|
||||||
# generate decoder.cc
|
# generate decoder.cc
|
||||||
includes = '#include "%s/decoder.hh"' % include_path
|
includes = '#include "decoder.hh"'
|
||||||
global_output = global_code.decoder_output
|
global_output = global_code.decoder_output
|
||||||
namespace_output = namespace_code.decoder_output
|
namespace_output = namespace_code.decoder_output
|
||||||
# namespace_output += namespace_code.decode_block
|
# namespace_output += namespace_code.decode_block
|
||||||
|
@ -1790,8 +1752,8 @@ def parse_isa_desc(isa_desc_file, output_dir, include_path):
|
||||||
update_if_needed(output_dir + '/decoder.cc', file_template % vars())
|
update_if_needed(output_dir + '/decoder.cc', file_template % vars())
|
||||||
|
|
||||||
# generate per-cpu exec files
|
# generate per-cpu exec files
|
||||||
for cpu in CpuModel.list:
|
for cpu in cpu_models:
|
||||||
includes = '#include "%s/decoder.hh"\n' % include_path
|
includes = '#include "decoder.hh"\n'
|
||||||
includes += cpu.includes
|
includes += cpu.includes
|
||||||
global_output = global_code.exec_output[cpu.name]
|
global_output = global_code.exec_output[cpu.name]
|
||||||
namespace_output = namespace_code.exec_output[cpu.name]
|
namespace_output = namespace_code.exec_output[cpu.name]
|
||||||
|
@ -1799,6 +1761,12 @@ def parse_isa_desc(isa_desc_file, output_dir, include_path):
|
||||||
update_if_needed(output_dir + '/' + cpu.filename,
|
update_if_needed(output_dir + '/' + cpu.filename,
|
||||||
file_template % vars())
|
file_template % vars())
|
||||||
|
|
||||||
|
# global list of CpuModel objects (see cpu_models.py)
|
||||||
|
cpu_models = []
|
||||||
|
|
||||||
# Called as script: get args from command line.
|
# Called as script: get args from command line.
|
||||||
|
# Args are: <path to cpu_models.py> <isa desc file> <output dir> <cpu models>
|
||||||
if __name__ == '__main__':
|
if __name__ == '__main__':
|
||||||
parse_isa_desc(sys.argv[1], sys.argv[2], sys.argv[3])
|
execfile(sys.argv[1]) # read in CpuModel definitions
|
||||||
|
cpu_models = [CpuModel.dict[cpu] for cpu in sys.argv[4:]]
|
||||||
|
parse_isa_desc(sys.argv[2], sys.argv[3])
|
||||||
|
|
|
@ -40,42 +40,44 @@ Import('env')
|
||||||
###################################################
|
###################################################
|
||||||
|
|
||||||
# Base sources used by all configurations.
|
# Base sources used by all configurations.
|
||||||
arch_base_sources = Split('''
|
base_sources = Split('''
|
||||||
arch/mips/decoder.cc
|
faults.cc
|
||||||
arch/mips/mips_o3_exec.cc
|
isa_traits.cc
|
||||||
arch/mips/fast_cpu_exec.cc
|
|
||||||
arch/mips/simple_cpu_exec.cc
|
|
||||||
arch/mips/full_cpu_exec.cc
|
|
||||||
arch/mips/faults.cc
|
|
||||||
arch/mips/isa_traits.cc
|
|
||||||
''')
|
''')
|
||||||
|
|
||||||
# Full-system sources
|
# Full-system sources
|
||||||
arch_full_system_sources = Split('''
|
full_system_sources = Split('''
|
||||||
arch/mips/memory.cc
|
memory.cc
|
||||||
arch/mips/arguments.cc
|
arguments.cc
|
||||||
arch/mips/mips34k.cc
|
mips34k.cc
|
||||||
arch/mips/osfpal.cc
|
osfpal.cc
|
||||||
arch/mips/stacktrace.cc
|
stacktrace.cc
|
||||||
arch/mips/vtophys.cc
|
vtophys.cc
|
||||||
''')
|
''')
|
||||||
|
|
||||||
# Syscall emulation (non-full-system) sources
|
# Syscall emulation (non-full-system) sources
|
||||||
arch_syscall_emulation_sources = Split('''
|
syscall_emulation_sources = Split('''
|
||||||
arch/mips/common_syscall_emul.cc
|
common_syscall_emul.cc
|
||||||
arch/mips/linux_process.cc
|
linux_process.cc
|
||||||
arch/mips/tru64_process.cc
|
tru64_process.cc
|
||||||
''')
|
''')
|
||||||
|
|
||||||
# Set up complete list of sources based on configuration.
|
# Set up complete list of sources based on configuration.
|
||||||
sources = arch_base_sources
|
sources = base_sources
|
||||||
|
|
||||||
if env['FULL_SYSTEM']:
|
if env['FULL_SYSTEM']:
|
||||||
sources += arch_full_system_sources
|
sources += full_system_sources
|
||||||
else:
|
else:
|
||||||
sources += arch_syscall_emulation_sources
|
sources += syscall_emulation_sources
|
||||||
|
|
||||||
for opt in env.ExportOptions:
|
# Convert file names to SCons File objects. This takes care of the
|
||||||
env.ConfigFile(opt)
|
# path relative to the top of the directory tree.
|
||||||
|
sources = [File(s) for s in sources]
|
||||||
|
|
||||||
|
# Add in files generated by the ISA description.
|
||||||
|
isa_desc_files = env.ISADesc('isa/main.isa')
|
||||||
|
# Only non-header files need to be compiled.
|
||||||
|
isa_desc_sources = [f for f in isa_desc_files if not f.path.endswith('.hh')]
|
||||||
|
sources += isa_desc_sources
|
||||||
|
|
||||||
Return('sources')
|
Return('sources')
|
||||||
|
|
|
@ -40,43 +40,43 @@ Import('env')
|
||||||
###################################################
|
###################################################
|
||||||
|
|
||||||
# Base sources used by all configurations.
|
# Base sources used by all configurations.
|
||||||
arch_base_sources = Split('''
|
base_sources = Split('''
|
||||||
arch/sparc/decoder.cc
|
faults.cc
|
||||||
arch/sparc/alpha_o3_exec.cc
|
isa_traits.cc
|
||||||
arch/sparc/fast_cpu_exec.cc
|
|
||||||
arch/sparc/simple_cpu_exec.cc
|
|
||||||
arch/sparc/full_cpu_exec.cc
|
|
||||||
arch/sparc/faults.cc
|
|
||||||
arch/sparc/isa_traits.cc
|
|
||||||
''')
|
''')
|
||||||
|
|
||||||
# Full-system sources
|
# Full-system sources
|
||||||
arch_full_system_sources = Split('''
|
full_system_sources = Split('''
|
||||||
arch/sparc/alpha_memory.cc
|
alpha_memory.cc
|
||||||
arch/sparc/arguments.cc
|
arguments.cc
|
||||||
arch/sparc/ev5.cc
|
ev5.cc
|
||||||
arch/sparc/osfpal.cc
|
osfpal.cc
|
||||||
arch/sparc/stacktrace.cc
|
stacktrace.cc
|
||||||
arch/sparc/vtophys.cc
|
vtophys.cc
|
||||||
''')
|
''')
|
||||||
|
|
||||||
# Syscall emulation (non-full-system) sources
|
# Syscall emulation (non-full-system) sources
|
||||||
arch_syscall_emulation_sources = Split('''
|
syscall_emulation_sources = Split('''
|
||||||
arch/sparc/alpha_common_syscall_emul.cc
|
alpha_common_syscall_emul.cc
|
||||||
arch/sparc/alpha_linux_process.cc
|
alpha_linux_process.cc
|
||||||
arch/sparc/alpha_tru64_process.cc
|
alpha_tru64_process.cc
|
||||||
''')
|
''')
|
||||||
|
|
||||||
sources = arch_base_sources
|
sources = base_sources
|
||||||
|
|
||||||
if env['FULL_SYSTEM']:
|
if env['FULL_SYSTEM']:
|
||||||
sources += arch_full_system_sources
|
sources += full_system_sources
|
||||||
if env['ALPHA_TLASER']:
|
|
||||||
sources += arch_turbolaser_sources
|
|
||||||
else:
|
else:
|
||||||
sources += arch_syscall_emulation_sources
|
sources += syscall_emulation_sources
|
||||||
|
|
||||||
for opt in env.ExportOptions:
|
# Convert file names to SCons File objects. This takes care of the
|
||||||
env.ConfigFile(opt)
|
# path relative to the top of the directory tree.
|
||||||
|
sources = [File(s) for s in sources]
|
||||||
|
|
||||||
|
# Add in files generated by the ISA description.
|
||||||
|
isa_desc_files = env.ISADesc('isa/main.isa')
|
||||||
|
# Only non-header files need to be compiled.
|
||||||
|
isa_desc_sources = [f for f in isa_desc_files if not f.path.endswith('.hh')]
|
||||||
|
sources += isa_desc_sources
|
||||||
|
|
||||||
Return('sources')
|
Return('sources')
|
||||||
|
|
|
@ -221,6 +221,9 @@ env = conf.Finish()
|
||||||
# Define the universe of supported ISAs
|
# Define the universe of supported ISAs
|
||||||
env['ALL_ISA_LIST'] = ['alpha', 'sparc', 'mips']
|
env['ALL_ISA_LIST'] = ['alpha', 'sparc', 'mips']
|
||||||
|
|
||||||
|
# Define the universe of supported CPU models
|
||||||
|
env['ALL_CPU_LIST'] = ['SimpleCPU', 'FastCPU', 'FullCPU', 'AlphaFullCPU']
|
||||||
|
|
||||||
# Sticky options get saved in the options file so they persist from
|
# Sticky options get saved in the options file so they persist from
|
||||||
# one invocation to the next (unless overridden, in which case the new
|
# one invocation to the next (unless overridden, in which case the new
|
||||||
# value becomes sticky).
|
# value becomes sticky).
|
||||||
|
@ -251,6 +254,12 @@ sticky_opts.AddOptions(
|
||||||
# Non-sticky options only apply to the current build.
|
# Non-sticky options only apply to the current build.
|
||||||
nonsticky_opts = Options(args=ARGUMENTS)
|
nonsticky_opts = Options(args=ARGUMENTS)
|
||||||
nonsticky_opts.AddOptions(
|
nonsticky_opts.AddOptions(
|
||||||
|
# This really should be a sticky option, but there's a bug in
|
||||||
|
# scons 0.96.1 that causes ListOptions not to be able to be
|
||||||
|
# restored from a saved option file. It looks like this is fixed
|
||||||
|
# in 0.96.9, but there's a different bug in that version that means we
|
||||||
|
# can't just upgrade.
|
||||||
|
ListOption('CPU_MODELS', 'CPU models', 'all', env['ALL_CPU_LIST']),
|
||||||
BoolOption('update_ref', 'Update test reference outputs', False)
|
BoolOption('update_ref', 'Update test reference outputs', False)
|
||||||
)
|
)
|
||||||
|
|
||||||
|
|
99
cpu/SConscript
Normal file
99
cpu/SConscript
Normal file
|
@ -0,0 +1,99 @@
|
||||||
|
# -*- mode:python -*-
|
||||||
|
|
||||||
|
# Copyright (c) 2006 The Regents of The University of Michigan
|
||||||
|
# All rights reserved.
|
||||||
|
#
|
||||||
|
# Redistribution and use in source and binary forms, with or without
|
||||||
|
# modification, are permitted provided that the following conditions are
|
||||||
|
# met: redistributions of source code must retain the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer;
|
||||||
|
# redistributions in binary form must reproduce the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer in the
|
||||||
|
# documentation and/or other materials provided with the distribution;
|
||||||
|
# neither the name of the copyright holders nor the names of its
|
||||||
|
# contributors may be used to endorse or promote products derived from
|
||||||
|
# this software without specific prior written permission.
|
||||||
|
#
|
||||||
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
|
||||||
|
import os
|
||||||
|
import os.path
|
||||||
|
|
||||||
|
# Import build environment variable from SConstruct.
|
||||||
|
Import('env')
|
||||||
|
|
||||||
|
models_db = File('cpu_models.py')
|
||||||
|
execfile(models_db.srcnode().abspath)
|
||||||
|
|
||||||
|
exec_sig_template = '''
|
||||||
|
virtual Fault execute(%s *xc, Trace::InstRecord *traceData) const = 0;
|
||||||
|
'''
|
||||||
|
|
||||||
|
def gen_cpu_exec_signatures(target, source, env):
|
||||||
|
f = open(str(target[0]), 'w')
|
||||||
|
print >> f, '''
|
||||||
|
#ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__
|
||||||
|
#define __CPU_STATIC_INST_EXEC_SIGS_HH__
|
||||||
|
'''
|
||||||
|
for cpu in env['CPU_MODELS']:
|
||||||
|
xc_type = CpuModel.dict[cpu].strings['CPU_exec_context']
|
||||||
|
print >> f, exec_sig_template % xc_type
|
||||||
|
print >> f, '''
|
||||||
|
#endif // __CPU_STATIC_INST_EXEC_SIGS_HH__
|
||||||
|
'''
|
||||||
|
|
||||||
|
env.Command('static_inst_exec_sigs.hh', models_db, gen_cpu_exec_signatures)
|
||||||
|
|
||||||
|
sources = []
|
||||||
|
|
||||||
|
if 'SimpleCPU' in env['CPU_MODELS']:
|
||||||
|
sources += Split('simple/cpu.cc')
|
||||||
|
|
||||||
|
if 'FastCPU' in env['CPU_MODELS']:
|
||||||
|
sources += Split('fast/cpu.cc')
|
||||||
|
|
||||||
|
if 'AlphaFullCPU' in env['CPU_MODELS']:
|
||||||
|
sources += Split('''
|
||||||
|
o3/2bit_local_pred.cc
|
||||||
|
o3/alpha_dyn_inst.cc
|
||||||
|
o3/alpha_cpu.cc
|
||||||
|
o3/alpha_cpu_builder.cc
|
||||||
|
o3/bpred_unit.cc
|
||||||
|
o3/btb.cc
|
||||||
|
o3/commit.cc
|
||||||
|
o3/decode.cc
|
||||||
|
o3/fetch.cc
|
||||||
|
o3/free_list.cc
|
||||||
|
o3/cpu.cc
|
||||||
|
o3/iew.cc
|
||||||
|
o3/inst_queue.cc
|
||||||
|
o3/ldstq.cc
|
||||||
|
o3/mem_dep_unit.cc
|
||||||
|
o3/ras.cc
|
||||||
|
o3/rename.cc
|
||||||
|
o3/rename_map.cc
|
||||||
|
o3/rob.cc
|
||||||
|
o3/sat_counter.cc
|
||||||
|
o3/store_set.cc
|
||||||
|
o3/tournament_pred.cc
|
||||||
|
''')
|
||||||
|
|
||||||
|
# FullCPU sources are included from m5/SConscript since they're not
|
||||||
|
# below this point in the file hierarchy.
|
||||||
|
|
||||||
|
# Convert file names to SCons File objects. This takes care of the
|
||||||
|
# path relative to the top of the directory tree.
|
||||||
|
sources = [File(s) for s in sources]
|
||||||
|
|
||||||
|
Return('sources')
|
||||||
|
|
71
cpu/cpu_models.py
Normal file
71
cpu/cpu_models.py
Normal file
|
@ -0,0 +1,71 @@
|
||||||
|
# Copyright (c) 2003-2006 The Regents of The University of Michigan
|
||||||
|
# All rights reserved.
|
||||||
|
#
|
||||||
|
# Redistribution and use in source and binary forms, with or without
|
||||||
|
# modification, are permitted provided that the following conditions are
|
||||||
|
# met: redistributions of source code must retain the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer;
|
||||||
|
# redistributions in binary form must reproduce the above copyright
|
||||||
|
# notice, this list of conditions and the following disclaimer in the
|
||||||
|
# documentation and/or other materials provided with the distribution;
|
||||||
|
# neither the name of the copyright holders nor the names of its
|
||||||
|
# contributors may be used to endorse or promote products derived from
|
||||||
|
# this software without specific prior written permission.
|
||||||
|
#
|
||||||
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
|
||||||
|
################
|
||||||
|
# CpuModel class
|
||||||
|
#
|
||||||
|
# The CpuModel class encapsulates everything the ISA parser needs to
|
||||||
|
# know about a particular CPU model.
|
||||||
|
|
||||||
|
class CpuModel:
|
||||||
|
# Dict of available CPU model objects. Accessible as CpuModel.dict.
|
||||||
|
dict = {}
|
||||||
|
|
||||||
|
# Constructor. Automatically adds models to CpuModel.dict.
|
||||||
|
def __init__(self, name, filename, includes, strings):
|
||||||
|
self.name = name
|
||||||
|
self.filename = filename # filename for output exec code
|
||||||
|
self.includes = includes # include files needed in exec file
|
||||||
|
# The 'strings' dict holds all the per-CPU symbols we can
|
||||||
|
# substitute into templates etc.
|
||||||
|
self.strings = strings
|
||||||
|
# Add self to dict
|
||||||
|
CpuModel.dict[name] = self
|
||||||
|
|
||||||
|
|
||||||
|
#
|
||||||
|
# Define CPU models.
|
||||||
|
#
|
||||||
|
# Parameters are:
|
||||||
|
# - name of model
|
||||||
|
# - filename for generated ISA execution file
|
||||||
|
# - includes needed for generated ISA execution file
|
||||||
|
# - substitution strings for ISA description templates
|
||||||
|
#
|
||||||
|
|
||||||
|
CpuModel('SimpleCPU', 'simple_cpu_exec.cc',
|
||||||
|
'#include "cpu/simple/cpu.hh"',
|
||||||
|
{ 'CPU_exec_context': 'SimpleCPU' })
|
||||||
|
CpuModel('FastCPU', 'fast_cpu_exec.cc',
|
||||||
|
'#include "cpu/fast/cpu.hh"',
|
||||||
|
{ 'CPU_exec_context': 'FastCPU' })
|
||||||
|
CpuModel('FullCPU', 'full_cpu_exec.cc',
|
||||||
|
'#include "encumbered/cpu/full/dyn_inst.hh"',
|
||||||
|
{ 'CPU_exec_context': 'DynInst' })
|
||||||
|
CpuModel('AlphaFullCPU', 'alpha_o3_exec.cc',
|
||||||
|
'#include "cpu/o3/alpha_dyn_inst.hh"',
|
||||||
|
{ 'CPU_exec_context': 'AlphaDynInst<AlphaSimpleImpl>' })
|
||||||
|
|
|
@ -137,8 +137,6 @@ FullO3CPU<Impl>::FullO3CPU(Params ¶ms)
|
||||||
system->execContexts[i] =
|
system->execContexts[i] =
|
||||||
new ExecContext(this, i, system, itb, dtb, mem);
|
new ExecContext(this, i, system, itb, dtb, mem);
|
||||||
|
|
||||||
// initialize CPU, including PC
|
|
||||||
TheISA::initCPU(&system->execContexts[i]->regs);
|
|
||||||
execContexts.push_back(system->execContexts[i]);
|
execContexts.push_back(system->execContexts[i]);
|
||||||
#else
|
#else
|
||||||
if (i < params.workload.size()) {
|
if (i < params.workload.size()) {
|
||||||
|
@ -250,6 +248,7 @@ FullO3CPU<Impl>::init()
|
||||||
// that it can start properly.
|
// that it can start properly.
|
||||||
#if FULL_SYSTEM
|
#if FULL_SYSTEM
|
||||||
ExecContext *src_xc = system->execContexts[0];
|
ExecContext *src_xc = system->execContexts[0];
|
||||||
|
TheISA::initCPU(&src_xc->regs, src_xc->cpu_id);
|
||||||
#else
|
#else
|
||||||
ExecContext *src_xc = thread[0];
|
ExecContext *src_xc = thread[0];
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -84,6 +84,21 @@ SimpleCPU::TickEvent::TickEvent(SimpleCPU *c, int w)
|
||||||
{
|
{
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
void
|
||||||
|
SimpleCPU::init()
|
||||||
|
{
|
||||||
|
BaseCPU::init();
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
for (int i = 0; i < execContexts.size(); ++i) {
|
||||||
|
ExecContext *xc = execContexts[i];
|
||||||
|
|
||||||
|
// initialize CPU, including PC
|
||||||
|
TheISA::initCPU(&xc->regs, xc->cpu_id);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
void
|
void
|
||||||
SimpleCPU::TickEvent::process()
|
SimpleCPU::TickEvent::process()
|
||||||
{
|
{
|
||||||
|
@ -124,8 +139,6 @@ SimpleCPU::SimpleCPU(Params *p)
|
||||||
#if FULL_SYSTEM
|
#if FULL_SYSTEM
|
||||||
xc = new ExecContext(this, 0, p->system, p->itb, p->dtb, p->mem);
|
xc = new ExecContext(this, 0, p->system, p->itb, p->dtb, p->mem);
|
||||||
|
|
||||||
// initialize CPU, including PC
|
|
||||||
initCPU(&xc->regs);
|
|
||||||
#else
|
#else
|
||||||
xc = new ExecContext(this, /* thread_num */ 0, p->process, /* asid */ 0);
|
xc = new ExecContext(this, /* thread_num */ 0, p->process, /* asid */ 0);
|
||||||
#endif // !FULL_SYSTEM
|
#endif // !FULL_SYSTEM
|
||||||
|
|
|
@ -68,6 +68,7 @@ class SimpleCPU : public BaseCPU
|
||||||
public:
|
public:
|
||||||
// main simulation loop (one cycle)
|
// main simulation loop (one cycle)
|
||||||
void tick();
|
void tick();
|
||||||
|
virtual void init();
|
||||||
|
|
||||||
private:
|
private:
|
||||||
struct TickEvent : public Event
|
struct TickEvent : public Event
|
||||||
|
|
|
@ -316,7 +316,11 @@ class StaticInst : public StaticInstBase
|
||||||
delete cachedDisassembly;
|
delete cachedDisassembly;
|
||||||
}
|
}
|
||||||
|
|
||||||
#include "static_inst_impl.hh"
|
/**
|
||||||
|
* The execute() signatures are auto-generated by scons based on the
|
||||||
|
* set of CPU models we are compiling in today.
|
||||||
|
*/
|
||||||
|
#include "cpu/static_inst_exec_sigs.hh"
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Return the target address for a PC-relative branch.
|
* Return the target address for a PC-relative branch.
|
||||||
|
|
|
@ -33,7 +33,7 @@
|
||||||
* System Console Memory Mapped Register Definition
|
* System Console Memory Mapped Register Definition
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#define ALPHA_ACCESS_VERSION (1303)
|
#define ALPHA_ACCESS_VERSION (1305)
|
||||||
|
|
||||||
#ifdef CONSOLE
|
#ifdef CONSOLE
|
||||||
typedef unsigned uint32_t;
|
typedef unsigned uint32_t;
|
||||||
|
@ -67,9 +67,7 @@ struct AlphaAccess
|
||||||
uint64_t inputChar; // 68: Placeholder for input
|
uint64_t inputChar; // 68: Placeholder for input
|
||||||
|
|
||||||
// MP boot
|
// MP boot
|
||||||
uint64_t bootStrapImpure; // 70:
|
uint64_t cpuStack[64]; // 70:
|
||||||
uint32_t bootStrapCPU; // 78:
|
|
||||||
uint32_t align2; // 7C: Dummy placeholder for alignment
|
|
||||||
};
|
};
|
||||||
|
|
||||||
#endif // __ALPHA_ACCESS_H__
|
#endif // __ALPHA_ACCESS_H__
|
||||||
|
|
|
@ -81,9 +81,7 @@ AlphaConsole::AlphaConsole(const string &name, SimConsole *cons, SimpleDisk *d,
|
||||||
alphaAccess->diskOperation = 0;
|
alphaAccess->diskOperation = 0;
|
||||||
alphaAccess->outputChar = 0;
|
alphaAccess->outputChar = 0;
|
||||||
alphaAccess->inputChar = 0;
|
alphaAccess->inputChar = 0;
|
||||||
alphaAccess->bootStrapImpure = 0;
|
bzero(alphaAccess->cpuStack, sizeof(alphaAccess->cpuStack));
|
||||||
alphaAccess->bootStrapCPU = 0;
|
|
||||||
alphaAccess->align2 = 0;
|
|
||||||
|
|
||||||
system->setAlphaAccess(addr);
|
system->setAlphaAccess(addr);
|
||||||
}
|
}
|
||||||
|
@ -123,9 +121,6 @@ AlphaConsole::read(MemReqPtr &req, uint8_t *data)
|
||||||
case offsetof(AlphaAccess, numCPUs):
|
case offsetof(AlphaAccess, numCPUs):
|
||||||
*(uint32_t*)data = alphaAccess->numCPUs;
|
*(uint32_t*)data = alphaAccess->numCPUs;
|
||||||
break;
|
break;
|
||||||
case offsetof(AlphaAccess, bootStrapCPU):
|
|
||||||
*(uint32_t*)data = alphaAccess->bootStrapCPU;
|
|
||||||
break;
|
|
||||||
case offsetof(AlphaAccess, intrClockFrequency):
|
case offsetof(AlphaAccess, intrClockFrequency):
|
||||||
*(uint32_t*)data = alphaAccess->intrClockFrequency;
|
*(uint32_t*)data = alphaAccess->intrClockFrequency;
|
||||||
break;
|
break;
|
||||||
|
@ -176,10 +171,13 @@ AlphaConsole::read(MemReqPtr &req, uint8_t *data)
|
||||||
case offsetof(AlphaAccess, outputChar):
|
case offsetof(AlphaAccess, outputChar):
|
||||||
*(uint64_t*)data = alphaAccess->outputChar;
|
*(uint64_t*)data = alphaAccess->outputChar;
|
||||||
break;
|
break;
|
||||||
case offsetof(AlphaAccess, bootStrapImpure):
|
|
||||||
*(uint64_t*)data = alphaAccess->bootStrapImpure;
|
|
||||||
break;
|
|
||||||
default:
|
default:
|
||||||
|
int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) /
|
||||||
|
sizeof(alphaAccess->cpuStack[0]);
|
||||||
|
|
||||||
|
if (cpunum >= 0 && cpunum < 64)
|
||||||
|
*(uint64_t*)data = alphaAccess->cpuStack[cpunum];
|
||||||
|
else
|
||||||
panic("Unknown 64bit access, %#x\n", daddr);
|
panic("Unknown 64bit access, %#x\n", daddr);
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
|
@ -240,24 +238,18 @@ AlphaConsole::write(MemReqPtr &req, const uint8_t *data)
|
||||||
console->out((char)(val & 0xff));
|
console->out((char)(val & 0xff));
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case offsetof(AlphaAccess, bootStrapImpure):
|
|
||||||
alphaAccess->bootStrapImpure = val;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case offsetof(AlphaAccess, bootStrapCPU):
|
|
||||||
warn("%d: Trying to launch another CPU!", curTick);
|
|
||||||
assert(val > 0 && "Must not access primary cpu");
|
|
||||||
|
|
||||||
other_xc = req->xc->system->execContexts[val];
|
|
||||||
other_xc->regs.intRegFile[16] = val;
|
|
||||||
other_xc->regs.ipr[TheISA::IPR_PALtemp16] = val;
|
|
||||||
other_xc->regs.intRegFile[0] = val;
|
|
||||||
other_xc->regs.intRegFile[30] = alphaAccess->bootStrapImpure;
|
|
||||||
other_xc->activate(); //Start the cpu
|
other_xc->activate(); //Start the cpu
|
||||||
break;
|
break;
|
||||||
|
|
||||||
default:
|
default:
|
||||||
return MachineCheckFault;
|
int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) /
|
||||||
|
sizeof(alphaAccess->cpuStack[0]);
|
||||||
|
warn("%d: Trying to launch CPU number %d!", curTick, cpunum);
|
||||||
|
assert(val > 0 && "Must not access primary cpu");
|
||||||
|
if (cpunum >= 0 && cpunum < 64)
|
||||||
|
alphaAccess->cpuStack[cpunum] = val;
|
||||||
|
else
|
||||||
|
panic("Unknown 64bit access, %#x\n", daddr);
|
||||||
}
|
}
|
||||||
|
|
||||||
return NoFault;
|
return NoFault;
|
||||||
|
@ -288,8 +280,7 @@ AlphaConsole::Access::serialize(ostream &os)
|
||||||
SERIALIZE_SCALAR(diskOperation);
|
SERIALIZE_SCALAR(diskOperation);
|
||||||
SERIALIZE_SCALAR(outputChar);
|
SERIALIZE_SCALAR(outputChar);
|
||||||
SERIALIZE_SCALAR(inputChar);
|
SERIALIZE_SCALAR(inputChar);
|
||||||
SERIALIZE_SCALAR(bootStrapImpure);
|
SERIALIZE_ARRAY(cpuStack,64);
|
||||||
SERIALIZE_SCALAR(bootStrapCPU);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
void
|
||||||
|
@ -311,8 +302,7 @@ AlphaConsole::Access::unserialize(Checkpoint *cp, const std::string §ion)
|
||||||
UNSERIALIZE_SCALAR(diskOperation);
|
UNSERIALIZE_SCALAR(diskOperation);
|
||||||
UNSERIALIZE_SCALAR(outputChar);
|
UNSERIALIZE_SCALAR(outputChar);
|
||||||
UNSERIALIZE_SCALAR(inputChar);
|
UNSERIALIZE_SCALAR(inputChar);
|
||||||
UNSERIALIZE_SCALAR(bootStrapImpure);
|
UNSERIALIZE_ARRAY(cpuStack, 64);
|
||||||
UNSERIALIZE_SCALAR(bootStrapCPU);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
void
|
||||||
|
|
|
@ -96,7 +96,7 @@ class AlphaConsole : public PioDevice
|
||||||
BaseCPU *cpu;
|
BaseCPU *cpu;
|
||||||
|
|
||||||
Addr addr;
|
Addr addr;
|
||||||
static const Addr size = 0x80; // equal to sizeof(alpha_access);
|
static const Addr size = sizeof(struct AlphaAccess);
|
||||||
|
|
||||||
public:
|
public:
|
||||||
/** Standard Constructor */
|
/** Standard Constructor */
|
||||||
|
|
|
@ -307,11 +307,9 @@ System::registerExecContext(ExecContext *xc, int id)
|
||||||
void
|
void
|
||||||
System::startup()
|
System::startup()
|
||||||
{
|
{
|
||||||
if (!execContexts.empty()) {
|
int i;
|
||||||
// activate with zero delay so that we start ticking right
|
for (i = 0; i < execContexts.size(); i++)
|
||||||
// away on cycle 0
|
execContexts[i]->activate(0);
|
||||||
execContexts[0]->activate(0);
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
void
|
||||||
|
|
Loading…
Reference in a new issue