From 789b3191b93dc78713c0ae80e592b4d2c43676d8 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Sun, 19 Apr 2009 04:56:14 -0700
Subject: [PATCH] X86: Implement a locking version of AND.

---
 .../x86/isa/insts/general_purpose/logical.py  | 32 +++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/src/arch/x86/isa/insts/general_purpose/logical.py b/src/arch/x86/isa/insts/general_purpose/logical.py
index ef860215c..97b09fb01 100644
--- a/src/arch/x86/isa/insts/general_purpose/logical.py
+++ b/src/arch/x86/isa/insts/general_purpose/logical.py
@@ -239,6 +239,23 @@ def macroop AND_P_I
     st t2, seg, riprel, disp
 };
 
+def macroop AND_LOCKED_M_I
+{
+    ldstl t2, seg, sib, disp
+    limm t1, imm
+    and t2, t2, t1, flags=(OF,SF,ZF,PF,CF)
+    stul t2, seg, sib, disp
+};
+
+def macroop AND_LOCKED_P_I
+{
+    rdip t7
+    ldstl t2, seg, riprel, disp
+    limm t1, imm
+    and t2, t2, t1, flags=(OF,SF,ZF,PF,CF)
+    stul t2, seg, riprel, disp
+};
+
 def macroop AND_M_R
 {
     ldst t1, seg, sib, disp
@@ -254,6 +271,21 @@ def macroop AND_P_R
     st t1, seg, riprel, disp
 };
 
+def macroop AND_LOCKED_M_R
+{
+    ldstl t1, seg, sib, disp
+    and t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
+    stul t1, seg, sib, disp
+};
+
+def macroop AND_LOCKED_P_R
+{
+    rdip t7
+    ldstl t1, seg, riprel, disp
+    and t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
+    stul t1, seg, riprel, disp
+};
+
 def macroop NOT_R
 {
     limm t1, -1