x86 work that hadn't been checked in.
src/arch/x86/isa/decoder/one_byte_opcodes.isa: Give the "MOV" instruction the format of it's arguments. This will likely need to be completely overhauled in the near future. src/arch/x86/predecoder.cc: src/arch/x86/predecoder.hh: Make the predecoder explicitly reset itself rather than counting on it happening naturally. src/arch/x86/predecoder_tables.cc: Fix the immediate size table src/arch/x86/regfile.cc: nextnpc is bogus --HG-- extra : convert_revision : 0926701fedaab41817e64bb05410a25174484a5a
This commit is contained in:
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a3ae9486d5
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7860c045e2
5 changed files with 49 additions and 24 deletions
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@ -237,11 +237,11 @@
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0x7: xchg_Ev_Gv();
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}
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0x11: decode OPCODE_OP_BOTTOM3 {
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0x0: Inst::MOV(); //mov_Eb_Gb();
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0x1: Inst::MOV(); //mov_Ev_Gv();
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0x2: Inst::MOV(); //mov_Gb_Eb();
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0x3: Inst::MOV(); //mov_Gv_Ev();
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0x4: Inst::MOV(); //mov_MwRv_Sw();
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0x0: Inst::MOV(Eb, Gb);
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0x1: Inst::MOV(Ev, Gv);
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0x2: Inst::MOV(Gb, Eb);
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0x3: Inst::MOV(Gv, Ev);
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0x4: mov_MwRv_Sw(); //What to do with this one?
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0x5: lea_Gv_M();
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0x6: mov_Sw_MwRv();
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0x7: group10_Ev(); //Make sure this is Ev
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@ -62,6 +62,21 @@
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namespace X86ISA
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{
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void Predecoder::reset()
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{
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origPC = basePC + offset;
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DPRINTF(Predecoder, "Setting origPC to %#x\n", origPC);
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emi.opcode.num = 0;
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immediateCollected = 0;
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emi.immediate = 0;
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displacementCollected = 0;
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emi.displacement = 0;
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emi.modRM = 0;
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emi.sib = 0;
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}
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void Predecoder::process()
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{
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//This function drives the predecoder state machine.
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@ -78,6 +93,9 @@ namespace X86ISA
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uint8_t nextByte = getNextByte();
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switch(state)
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{
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case ResetState:
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reset();
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state = PrefixState;
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case PrefixState:
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state = doPrefixState(nextByte);
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break;
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@ -150,7 +168,6 @@ namespace X86ISA
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emi.rex = nextByte;
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break;
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case 0:
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emi.opcode.num = 0;
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nextState = OpcodeState;
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break;
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default:
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@ -188,12 +205,6 @@ namespace X86ISA
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DPRINTF(Predecoder, "Found opcode %#x.\n", nextByte);
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emi.opcode.op = nextByte;
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//Prepare for any immediate/displacement we might need
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immediateCollected = 0;
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emi.immediate = 0;
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displacementCollected = 0;
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emi.displacement = 0;
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//Figure out the effective operand size. This can be overriden to
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//a fixed value at the decoder level.
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if(/*FIXME long mode*/1)
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@ -229,14 +240,11 @@ namespace X86ISA
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if (UsesModRM[emi.opcode.num - 1][nextByte]) {
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nextState = ModRMState;
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} else {
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//If there's no modRM byte, set it to 0 so we can detect
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//that later.
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emi.modRM = 0;
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if(immediateSize) {
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nextState = ImmediateState;
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} else {
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emiIsReady = true;
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nextState = PrefixState;
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nextState = ResetState;
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}
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}
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}
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@ -282,7 +290,7 @@ namespace X86ISA
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nextState = ImmediateState;
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} else {
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emiIsReady = true;
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nextState = PrefixState;
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nextState = ResetState;
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}
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//The ModRM byte is consumed no matter what
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consumeByte();
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@ -304,7 +312,7 @@ namespace X86ISA
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nextState = ImmediateState;
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} else {
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emiIsReady = true;
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nextState = PrefixState;
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nextState = ResetState;
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}
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return nextState;
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}
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@ -344,7 +352,7 @@ namespace X86ISA
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nextState = ImmediateState;
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} else {
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emiIsReady = true;
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nextState = PrefixState;
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nextState = ResetState;
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}
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}
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else
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@ -380,7 +388,7 @@ namespace X86ISA
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DPRINTF(Predecoder, "Collected immediate %#x.\n",
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emi.immediate);
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emiIsReady = true;
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nextState = PrefixState;
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nextState = ResetState;
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}
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else
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nextState = ImmediateState;
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@ -60,6 +60,8 @@
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#include "arch/x86/types.hh"
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#include "base/bitfield.hh"
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#include "base/misc.hh"
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#include "base/trace.hh"
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#include "sim/host.hh"
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class ThreadContext;
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@ -81,6 +83,8 @@ namespace X86ISA
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MachInst fetchChunk;
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//The pc of the start of fetchChunk
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Addr basePC;
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//The pc the current instruction started at
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Addr origPC;
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//The offset into fetchChunk of current processing
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int offset;
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//The extended machine instruction being generated
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@ -130,6 +134,8 @@ namespace X86ISA
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outOfBytes = true;
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}
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void reset();
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//State machine state
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protected:
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//Whether or not we're out of bytes
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int immediateCollected;
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enum State {
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ResetState,
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PrefixState,
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OpcodeState,
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ModRMState,
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public:
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Predecoder(ThreadContext * _tc) :
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tc(_tc), basePC(0), offset(0),
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tc(_tc), basePC(0), origPC(0), offset(0),
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outOfBytes(true), emiIsReady(false),
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state(PrefixState)
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state(ResetState)
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{}
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ThreadContext * getTC()
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emiIsReady = false;
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return emi;
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}
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int getInstSize()
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{
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DPRINTF(Predecoder,
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"Calculating the instruction size: "
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"basePC: %#x offset: %#x origPC: %#x\n",
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basePC, offset, origPC);
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return basePC + offset - origPC;
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}
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};
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};
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// noimm byte word dword qword oword vword zword enter pointer
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{0, 1, 2, 4, 8, 16, 2, 2, 3, 4 }, //16 bit
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{0, 1, 2, 4, 8, 16, 4, 4, 3, 6 }, //32 bit
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{0, 1, 2, 4, 8, 16, 4, 8, 3, 0 } //64 bit
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{0, 1, 2, 4, 8, 16, 8, 4, 3, 0 } //64 bit
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};
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//This table determines the immediate type. The first index is the
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@ -117,7 +117,8 @@ void RegFile::setNextPC(Addr val)
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Addr RegFile::readNextNPC()
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{
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return nextRip + sizeof(MachInst);
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//There's no way to know how big the -next- instruction will be.
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return nextRip + 1;
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}
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void RegFile::setNextNPC(Addr val)
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