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Fix corner case on assertion.

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I need to move over to using the fixPacket function so I don't have to make the same changes everywhere.
Still a functional access bug someplace I need to track down in timing mode.

src/mem/cache/base_cache.cc:
src/mem/cache/cache_impl.hh:
    Fix corner case on assertion
tests/configs/memtest.py:
    Updated memtester with uncacheable addresses and functional accesses

--HG--
extra : convert_revision : e6fa851621700ff9227b83cc5cac20af4fc8444f
This commit is contained in:
Ron Dreslinski 2006-10-19 21:26:46 -04:00
parent cc1feb9f6d
commit 780aa0a0eb
3 changed files with 6 additions and 6 deletions
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2
src/mem/cache/base_cache.cc vendored
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@ -132,7 +132,7 @@ BaseCache::CachePort::recvFunctional(Packet *pkt)
pkt_data = pkt->getPtr<uint8_t>() + offset;
write_data = target->getPtr<uint8_t>();
data_size = pkt->getSize() - offset;
assert(data_size > pkt->getSize());
assert(data_size >= pkt->getSize());
if (data_size > target->getSize())
data_size = target->getSize();
}

4
src/mem/cache/cache_impl.hh vendored
View file

@ -585,7 +585,7 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update,
pkt_data = pkt->getPtr<uint8_t>() + offset;
write_data = target->getPtr<uint8_t>();
data_size = pkt->getSize() - offset;
assert(data_size > pkt->getSize());
assert(data_size >= pkt->getSize());
if (data_size > target->getSize())
data_size = target->getSize();
}
@ -620,7 +620,7 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update,
pkt_data = pkt->getPtr<uint8_t>() + offset;
write_data = write->getPtr<uint8_t>();
data_size = pkt->getSize() - offset;
assert(data_size > pkt->getSize());
assert(data_size >= pkt->getSize());
if (data_size > write->getSize())
data_size = write->getSize();
}

6
tests/configs/memtest.py
View file

@ -53,7 +53,7 @@ class L2(BaseCache):
#MAX CORES IS 8 with the fals sharing method
nb_cores = 8
cpus = [ MemTest(max_loads=1e12, percent_uncacheable=0, progress_interval=1000) for i in xrange(nb_cores) ]
cpus = [ MemTest(atomic=False, max_loads=1e12, percent_uncacheable=10, progress_interval=1000) for i in xrange(nb_cores) ]
# system simulated
system = System(cpu = cpus, funcmem = PhysicalMemory(),
@ -90,6 +90,6 @@ system.physmem.port = system.membus.port
root = Root( system = system )
root.system.mem_mode = 'timing'
#root.trace.flags="Cache CachePort Bus"
#root.trace.cycle=3810800
#root.trace.flags="Cache CachePort MemoryAccess"
#root.trace.cycle=1