diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc index ccdcf7502..019e83dd4 100644 --- a/arch/alpha/ev5.cc +++ b/arch/alpha/ev5.cc @@ -541,6 +541,14 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc) return NoFault; } +void +AlphaISA::MiscRegFile::copyIprs(ExecContext *xc) +{ + for (int i = IPR_Base_DepTag; i < NumInternalProcRegs; ++i) { + ipr[i] = xc->readMiscReg(i); + } +} + /** * Check for special simulator handling of specific PAL calls. * If return value is false, actual PAL call will be suppressed. diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh index b719b12b0..8e1f21a35 100644 --- a/arch/alpha/isa_traits.hh +++ b/arch/alpha/isa_traits.hh @@ -169,6 +169,8 @@ extern const int reg_redir[NumIntRegs]; Fault setRegWithEffect(int misc_reg, const MiscReg &val, ExecContext *xc); + void copyMiscRegs(ExecContext *xc); + #if FULL_SYSTEM protected: InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs @@ -177,6 +179,8 @@ extern const int reg_redir[NumIntRegs]; MiscReg readIpr(int idx, Fault &fault, ExecContext *xc); Fault setIpr(int idx, uint64_t val, ExecContext *xc); + + void copyIprs(ExecContext *xc); #endif friend class RegFile; }; diff --git a/cpu/cpu_exec_context.cc b/cpu/cpu_exec_context.cc index 683d07787..b7238e73a 100644 --- a/cpu/cpu_exec_context.cc +++ b/cpu/cpu_exec_context.cc @@ -289,15 +289,7 @@ CPUExecContext::copyArchRegs(ExecContext *xc) } // Copy misc. registers - setMiscReg(AlphaISA::Fpcr_DepTag, xc->readMiscReg(AlphaISA::Fpcr_DepTag)); - setMiscReg(AlphaISA::Uniq_DepTag, xc->readMiscReg(AlphaISA::Uniq_DepTag)); - setMiscReg(AlphaISA::Lock_Flag_DepTag, - xc->readMiscReg(AlphaISA::Lock_Flag_DepTag)); - setMiscReg(AlphaISA::Lock_Addr_DepTag, - xc->readMiscReg(AlphaISA::Lock_Addr_DepTag)); - - // Also need to copy all the IPRs. Probably should just have a copy misc - // regs function defined on the misc regs. + regs.miscRegs.copyMiscRegs(xc); // Lastly copy PC/NPC setPC(xc->readPC());