Update #defines for the O3CPU. Also include the copyright.
base/timebuf.hh: Updated copyright. cpu/o3/2bit_local_pred.hh: cpu/o3/alpha_cpu.hh: cpu/o3/alpha_cpu_impl.hh: cpu/o3/alpha_dyn_inst.hh: cpu/o3/alpha_impl.hh: cpu/o3/alpha_params.hh: cpu/o3/btb.hh: cpu/o3/comm.hh: cpu/o3/commit.hh: cpu/o3/cpu.cc: cpu/o3/cpu.hh: cpu/o3/cpu_policy.hh: cpu/o3/decode.hh: cpu/o3/fetch.hh: cpu/o3/free_list.hh: cpu/o3/iew.hh: cpu/o3/inst_queue.hh: cpu/o3/mem_dep_unit.hh: cpu/o3/ras.hh: cpu/o3/regfile.hh: cpu/o3/rename.hh: cpu/o3/rename_map.hh: cpu/o3/rob.cc: cpu/o3/rob.hh: cpu/o3/rob_impl.hh: cpu/o3/sat_counter.hh: cpu/o3/store_set.hh: cpu/o3/tournament_pred.hh: Updated #define to have correct path. docs/footer.html: Remove e-mail addr. --HG-- extra : convert_revision : 68d7af52674621dc3b6d6ac0d564790ffd595fe3
This commit is contained in:
parent
7d367f4cc4
commit
77b9829f13
29 changed files with 176 additions and 123 deletions
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@ -26,8 +26,8 @@
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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*/
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#ifndef __CPU_BETA_CPU_2BIT_LOCAL_PRED_HH__
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#ifndef __CPU_O3_CPU_2BIT_LOCAL_PRED_HH__
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#define __CPU_BETA_CPU_2BIT_LOCAL_PRED_HH__
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#define __CPU_O3_CPU_2BIT_LOCAL_PRED_HH__
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// For Addr type.
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// For Addr type.
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#include "arch/alpha/isa_traits.hh"
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#include "arch/alpha/isa_traits.hh"
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@ -83,4 +83,4 @@ class DefaultBP
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unsigned indexMask;
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unsigned indexMask;
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};
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};
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#endif // __CPU_BETA_CPU_2BIT_LOCAL_PRED_HH__
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#endif // __CPU_O3_CPU_2BIT_LOCAL_PRED_HH__
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@ -29,13 +29,13 @@
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// Todo: Find all the stuff in ExecContext and ev5 that needs to be
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// Todo: Find all the stuff in ExecContext and ev5 that needs to be
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// specifically designed for this CPU.
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// specifically designed for this CPU.
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#ifndef __CPU_BETA_CPU_ALPHA_FULL_CPU_HH__
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#ifndef __CPU_O3_CPU_ALPHA_FULL_CPU_HH__
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#define __CPU_BETA_CPU_ALPHA_FULL_CPU_HH__
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#define __CPU_O3_CPU_ALPHA_FULL_CPU_HH__
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#include "cpu/o3/cpu.hh"
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#include "cpu/o3/cpu.hh"
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template <class Impl>
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template <class Impl>
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class AlphaFullCPU : public FullBetaCPU<Impl>
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class AlphaFullCPU : public FullO3CPU<Impl>
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{
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{
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public:
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public:
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typedef typename Impl::ISA AlphaISA;
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typedef typename Impl::ISA AlphaISA;
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@ -288,4 +288,4 @@ class AlphaFullCPU : public FullBetaCPU<Impl>
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};
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};
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#endif // __CPU_BETA_CPU_ALPHA_FULL_CPU_HH__
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#endif // __CPU_O3_CPU_ALPHA_FULL_CPU_HH__
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@ -1,3 +1,30 @@
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/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "base/cprintf.hh"
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#include "base/cprintf.hh"
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#include "base/statistics.hh"
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#include "base/statistics.hh"
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@ -22,7 +49,7 @@
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template <class Impl>
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template <class Impl>
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AlphaFullCPU<Impl>::AlphaFullCPU(Params ¶ms)
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AlphaFullCPU<Impl>::AlphaFullCPU(Params ¶ms)
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: FullBetaCPU<Impl>(params)
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: FullO3CPU<Impl>(params)
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{
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{
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DPRINTF(FullCPU, "AlphaFullCPU: Creating AlphaFullCPU object.\n");
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DPRINTF(FullCPU, "AlphaFullCPU: Creating AlphaFullCPU object.\n");
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@ -26,8 +26,8 @@
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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*/
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#ifndef __CPU_BETA_CPU_ALPHA_DYN_INST_HH__
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#ifndef __CPU_O3_CPU_ALPHA_DYN_INST_HH__
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#define __CPU_BETA_CPU_ALPHA_DYN_INST_HH__
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#define __CPU_O3_CPU_ALPHA_DYN_INST_HH__
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#include "cpu/base_dyn_inst.hh"
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#include "cpu/base_dyn_inst.hh"
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#include "cpu/o3/alpha_cpu.hh"
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#include "cpu/o3/alpha_cpu.hh"
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@ -231,5 +231,5 @@ class AlphaDynInst : public BaseDynInst<Impl>
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}
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}
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};
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};
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#endif // __CPU_BETA_CPU_ALPHA_DYN_INST_HH__
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#endif // __CPU_O3_CPU_ALPHA_DYN_INST_HH__
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@ -26,8 +26,8 @@
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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*/
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#ifndef __CPU_BETA_CPU_ALPHA_IMPL_HH__
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#ifndef __CPU_O3_CPU_ALPHA_IMPL_HH__
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#define __CPU_BETA_CPU_ALPHA_IMPL_HH__
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#define __CPU_O3_CPU_ALPHA_IMPL_HH__
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#include "arch/alpha/isa_traits.hh"
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#include "arch/alpha/isa_traits.hh"
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@ -79,4 +79,4 @@ struct AlphaSimpleImpl
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};
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};
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};
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};
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#endif // __CPU_BETA_CPU_ALPHA_IMPL_HH__
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#endif // __CPU_O3_CPU_ALPHA_IMPL_HH__
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@ -26,8 +26,8 @@
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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*/
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#ifndef __CPU_BETA_CPU_ALPHA_SIMPLE_PARAMS_HH__
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#ifndef __CPU_O3_CPU_ALPHA_SIMPLE_PARAMS_HH__
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#define __CPU_BETA_CPU_ALPHA_SIMPLE_PARAMS_HH__
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#define __CPU_O3_CPU_ALPHA_SIMPLE_PARAMS_HH__
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#include "cpu/o3/cpu.hh"
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#include "cpu/o3/cpu.hh"
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@ -160,4 +160,4 @@ class AlphaSimpleParams : public BaseFullCPU::Params
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bool defReg;
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bool defReg;
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};
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};
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#endif // __CPU_BETA_CPU_ALPHA_PARAMS_HH__
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#endif // __CPU_O3_CPU_ALPHA_PARAMS_HH__
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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*/
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#ifndef __CPU_BETA_CPU_BTB_HH__
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#ifndef __CPU_O3_CPU_BTB_HH__
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#define __CPU_BETA_CPU_BTB_HH__
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#define __CPU_O3_CPU_BTB_HH__
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// For Addr type.
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// For Addr type.
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#include "arch/alpha/isa_traits.hh"
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#include "arch/alpha/isa_traits.hh"
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@ -77,4 +77,4 @@ class DefaultBTB
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unsigned tagShiftAmt;
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unsigned tagShiftAmt;
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};
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};
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#endif // __CPU_BETA_CPU_BTB_HH__
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#endif // __CPU_O3_CPU_BTB_HH__
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@ -26,8 +26,8 @@
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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*/
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#ifndef __CPU_BETA_CPU_COMM_HH__
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#ifndef __CPU_O3_CPU_COMM_HH__
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#define __CPU_BETA_CPU_COMM_HH__
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#define __CPU_O3_CPU_COMM_HH__
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#include <vector>
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#include <vector>
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@ -160,4 +160,4 @@ struct TimeBufStruct {
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commitComm commitInfo;
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commitComm commitInfo;
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};
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};
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#endif //__CPU_BETA_CPU_COMM_HH__
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#endif //__CPU_O3_CPU_COMM_HH__
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// Probably not a big deal if the IPR stuff isn't cycle accurate. Can just
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// Probably not a big deal if the IPR stuff isn't cycle accurate. Can just
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// have the original function handle writing to the IPR register.
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// have the original function handle writing to the IPR register.
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#ifndef __CPU_BETA_CPU_SIMPLE_COMMIT_HH__
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#ifndef __CPU_O3_CPU_SIMPLE_COMMIT_HH__
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#define __CPU_BETA_CPU_SIMPLE_COMMIT_HH__
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#define __CPU_O3_CPU_SIMPLE_COMMIT_HH__
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#include "base/statistics.hh"
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#include "base/statistics.hh"
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#include "base/timebuf.hh"
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#include "base/timebuf.hh"
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@ -178,4 +178,4 @@ class SimpleCommit
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Stats::Distribution<> n_committed_dist;
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Stats::Distribution<> n_committed_dist;
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};
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};
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#endif // __CPU_BETA_CPU_SIMPLE_COMMIT_HH__
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#endif // __CPU_O3_CPU_SIMPLE_COMMIT_HH__
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@ -46,28 +46,28 @@ BaseFullCPU::BaseFullCPU(Params ¶ms)
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}
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}
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template <class Impl>
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template <class Impl>
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FullBetaCPU<Impl>::TickEvent::TickEvent(FullBetaCPU<Impl> *c)
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FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
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: Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
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: Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
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{
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{
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}
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}
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template <class Impl>
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template <class Impl>
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void
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void
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FullBetaCPU<Impl>::TickEvent::process()
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FullO3CPU<Impl>::TickEvent::process()
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{
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{
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cpu->tick();
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cpu->tick();
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}
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}
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template <class Impl>
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template <class Impl>
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const char *
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const char *
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FullBetaCPU<Impl>::TickEvent::description()
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FullO3CPU<Impl>::TickEvent::description()
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{
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{
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return "FullBetaCPU tick event";
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return "FullO3CPU tick event";
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}
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}
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//Call constructor to all the pipeline stages here
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//Call constructor to all the pipeline stages here
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template <class Impl>
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template <class Impl>
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FullBetaCPU<Impl>::FullBetaCPU(Params ¶ms)
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FullO3CPU<Impl>::FullO3CPU(Params ¶ms)
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#ifdef FULL_SYSTEM
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#ifdef FULL_SYSTEM
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: BaseFullCPU(params),
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: BaseFullCPU(params),
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#else
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#else
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// The stages also need their CPU pointer setup. However this must be
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// The stages also need their CPU pointer setup. However this must be
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// done at the upper level CPU because they have pointers to the upper
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// done at the upper level CPU because they have pointers to the upper
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// level CPU, and not this FullBetaCPU.
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// level CPU, and not this FullO3CPU.
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// Give each of the stages the time buffer they will use.
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// Give each of the stages the time buffer they will use.
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fetch.setTimeBuffer(&timeBuffer);
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fetch.setTimeBuffer(&timeBuffer);
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}
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}
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template <class Impl>
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template <class Impl>
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FullBetaCPU<Impl>::~FullBetaCPU()
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FullO3CPU<Impl>::~FullO3CPU()
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{
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{
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}
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}
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template <class Impl>
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template <class Impl>
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void
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void
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FullBetaCPU<Impl>::fullCPURegStats()
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FullO3CPU<Impl>::fullCPURegStats()
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{
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{
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// Register any of the FullCPU's stats here.
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// Register any of the FullCPU's stats here.
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}
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}
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template <class Impl>
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template <class Impl>
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void
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void
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FullBetaCPU<Impl>::tick()
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FullO3CPU<Impl>::tick()
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{
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{
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DPRINTF(FullCPU, "\n\nFullCPU: Ticking main, FullBetaCPU.\n");
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DPRINTF(FullCPU, "\n\nFullCPU: Ticking main, FullO3CPU.\n");
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//Tick each of the stages if they're actually running.
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//Tick each of the stages if they're actually running.
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//Will want to figure out a way to unschedule itself if they're all
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//Will want to figure out a way to unschedule itself if they're all
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template <class Impl>
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template <class Impl>
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void
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void
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FullBetaCPU<Impl>::init()
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FullO3CPU<Impl>::init()
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{
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{
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if(!deferRegistration)
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if(!deferRegistration)
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{
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{
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@ -278,7 +278,7 @@ FullBetaCPU<Impl>::init()
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template <class Impl>
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template <class Impl>
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void
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void
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FullBetaCPU<Impl>::activateContext(int thread_num, int delay)
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FullO3CPU<Impl>::activateContext(int thread_num, int delay)
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{
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{
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// Needs to set each stage to running as well.
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// Needs to set each stage to running as well.
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|
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@ -289,35 +289,35 @@ FullBetaCPU<Impl>::activateContext(int thread_num, int delay)
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|
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template <class Impl>
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template <class Impl>
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void
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void
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FullBetaCPU<Impl>::suspendContext(int thread_num)
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FullO3CPU<Impl>::suspendContext(int thread_num)
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{
|
{
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panic("suspendContext unimplemented!");
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panic("suspendContext unimplemented!");
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}
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}
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|
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template <class Impl>
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template <class Impl>
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void
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void
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FullBetaCPU<Impl>::deallocateContext(int thread_num)
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FullO3CPU<Impl>::deallocateContext(int thread_num)
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{
|
{
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panic("deallocateContext unimplemented!");
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panic("deallocateContext unimplemented!");
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}
|
}
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|
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template <class Impl>
|
template <class Impl>
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void
|
void
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FullBetaCPU<Impl>::haltContext(int thread_num)
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FullO3CPU<Impl>::haltContext(int thread_num)
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{
|
{
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panic("haltContext unimplemented!");
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panic("haltContext unimplemented!");
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}
|
}
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|
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template <class Impl>
|
template <class Impl>
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void
|
void
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FullBetaCPU<Impl>::switchOut()
|
FullO3CPU<Impl>::switchOut()
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{
|
{
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panic("FullBetaCPU does not have a switch out function.\n");
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panic("FullO3CPU does not have a switch out function.\n");
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}
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}
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|
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template <class Impl>
|
template <class Impl>
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void
|
void
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FullBetaCPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
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FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
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{
|
{
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BaseCPU::takeOverFrom(oldCPU);
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BaseCPU::takeOverFrom(oldCPU);
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|
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|
@ -336,7 +336,7 @@ FullBetaCPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
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|
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template <class Impl>
|
template <class Impl>
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InstSeqNum
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InstSeqNum
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FullBetaCPU<Impl>::getAndIncrementInstSeq()
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FullO3CPU<Impl>::getAndIncrementInstSeq()
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{
|
{
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// Hopefully this works right.
|
// Hopefully this works right.
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return globalSeqNum++;
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return globalSeqNum++;
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|
@ -344,91 +344,91 @@ FullBetaCPU<Impl>::getAndIncrementInstSeq()
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|
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template <class Impl>
|
template <class Impl>
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uint64_t
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uint64_t
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FullBetaCPU<Impl>::readIntReg(int reg_idx)
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FullO3CPU<Impl>::readIntReg(int reg_idx)
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{
|
{
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return regFile.readIntReg(reg_idx);
|
return regFile.readIntReg(reg_idx);
|
||||||
}
|
}
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
float
|
float
|
||||||
FullBetaCPU<Impl>::readFloatRegSingle(int reg_idx)
|
FullO3CPU<Impl>::readFloatRegSingle(int reg_idx)
|
||||||
{
|
{
|
||||||
return regFile.readFloatRegSingle(reg_idx);
|
return regFile.readFloatRegSingle(reg_idx);
|
||||||
}
|
}
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
double
|
double
|
||||||
FullBetaCPU<Impl>::readFloatRegDouble(int reg_idx)
|
FullO3CPU<Impl>::readFloatRegDouble(int reg_idx)
|
||||||
{
|
{
|
||||||
return regFile.readFloatRegDouble(reg_idx);
|
return regFile.readFloatRegDouble(reg_idx);
|
||||||
}
|
}
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
uint64_t
|
uint64_t
|
||||||
FullBetaCPU<Impl>::readFloatRegInt(int reg_idx)
|
FullO3CPU<Impl>::readFloatRegInt(int reg_idx)
|
||||||
{
|
{
|
||||||
return regFile.readFloatRegInt(reg_idx);
|
return regFile.readFloatRegInt(reg_idx);
|
||||||
}
|
}
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
void
|
void
|
||||||
FullBetaCPU<Impl>::setIntReg(int reg_idx, uint64_t val)
|
FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
|
||||||
{
|
{
|
||||||
regFile.setIntReg(reg_idx, val);
|
regFile.setIntReg(reg_idx, val);
|
||||||
}
|
}
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
void
|
void
|
||||||
FullBetaCPU<Impl>::setFloatRegSingle(int reg_idx, float val)
|
FullO3CPU<Impl>::setFloatRegSingle(int reg_idx, float val)
|
||||||
{
|
{
|
||||||
regFile.setFloatRegSingle(reg_idx, val);
|
regFile.setFloatRegSingle(reg_idx, val);
|
||||||
}
|
}
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
void
|
void
|
||||||
FullBetaCPU<Impl>::setFloatRegDouble(int reg_idx, double val)
|
FullO3CPU<Impl>::setFloatRegDouble(int reg_idx, double val)
|
||||||
{
|
{
|
||||||
regFile.setFloatRegDouble(reg_idx, val);
|
regFile.setFloatRegDouble(reg_idx, val);
|
||||||
}
|
}
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
void
|
void
|
||||||
FullBetaCPU<Impl>::setFloatRegInt(int reg_idx, uint64_t val)
|
FullO3CPU<Impl>::setFloatRegInt(int reg_idx, uint64_t val)
|
||||||
{
|
{
|
||||||
regFile.setFloatRegInt(reg_idx, val);
|
regFile.setFloatRegInt(reg_idx, val);
|
||||||
}
|
}
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
uint64_t
|
uint64_t
|
||||||
FullBetaCPU<Impl>::readPC()
|
FullO3CPU<Impl>::readPC()
|
||||||
{
|
{
|
||||||
return regFile.readPC();
|
return regFile.readPC();
|
||||||
}
|
}
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
void
|
void
|
||||||
FullBetaCPU<Impl>::setNextPC(uint64_t val)
|
FullO3CPU<Impl>::setNextPC(uint64_t val)
|
||||||
{
|
{
|
||||||
regFile.setNextPC(val);
|
regFile.setNextPC(val);
|
||||||
}
|
}
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
void
|
void
|
||||||
FullBetaCPU<Impl>::setPC(Addr new_PC)
|
FullO3CPU<Impl>::setPC(Addr new_PC)
|
||||||
{
|
{
|
||||||
regFile.setPC(new_PC);
|
regFile.setPC(new_PC);
|
||||||
}
|
}
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
void
|
void
|
||||||
FullBetaCPU<Impl>::addInst(DynInstPtr &inst)
|
FullO3CPU<Impl>::addInst(DynInstPtr &inst)
|
||||||
{
|
{
|
||||||
instList.push_back(inst);
|
instList.push_back(inst);
|
||||||
}
|
}
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
void
|
void
|
||||||
FullBetaCPU<Impl>::instDone()
|
FullO3CPU<Impl>::instDone()
|
||||||
{
|
{
|
||||||
// Keep an instruction count.
|
// Keep an instruction count.
|
||||||
numInsts++;
|
numInsts++;
|
||||||
|
@ -439,7 +439,7 @@ FullBetaCPU<Impl>::instDone()
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
void
|
void
|
||||||
FullBetaCPU<Impl>::removeBackInst(DynInstPtr &inst)
|
FullO3CPU<Impl>::removeBackInst(DynInstPtr &inst)
|
||||||
{
|
{
|
||||||
DynInstPtr inst_to_delete;
|
DynInstPtr inst_to_delete;
|
||||||
|
|
||||||
|
@ -465,7 +465,7 @@ FullBetaCPU<Impl>::removeBackInst(DynInstPtr &inst)
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
void
|
void
|
||||||
FullBetaCPU<Impl>::removeFrontInst(DynInstPtr &inst)
|
FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
|
||||||
{
|
{
|
||||||
DynInstPtr inst_to_remove;
|
DynInstPtr inst_to_remove;
|
||||||
|
|
||||||
|
@ -482,7 +482,7 @@ FullBetaCPU<Impl>::removeFrontInst(DynInstPtr &inst)
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
void
|
void
|
||||||
FullBetaCPU<Impl>::removeInstsNotInROB()
|
FullO3CPU<Impl>::removeInstsNotInROB()
|
||||||
{
|
{
|
||||||
DPRINTF(FullCPU, "FullCPU: Deleting instructions from instruction "
|
DPRINTF(FullCPU, "FullCPU: Deleting instructions from instruction "
|
||||||
"list.\n");
|
"list.\n");
|
||||||
|
@ -494,7 +494,7 @@ FullBetaCPU<Impl>::removeInstsNotInROB()
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
void
|
void
|
||||||
FullBetaCPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num)
|
FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num)
|
||||||
{
|
{
|
||||||
DPRINTF(FullCPU, "FullCPU: Deleting instructions from instruction "
|
DPRINTF(FullCPU, "FullCPU: Deleting instructions from instruction "
|
||||||
"list.\n");
|
"list.\n");
|
||||||
|
@ -522,14 +522,14 @@ FullBetaCPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num)
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
void
|
void
|
||||||
FullBetaCPU<Impl>::removeAllInsts()
|
FullO3CPU<Impl>::removeAllInsts()
|
||||||
{
|
{
|
||||||
instList.clear();
|
instList.clear();
|
||||||
}
|
}
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
void
|
void
|
||||||
FullBetaCPU<Impl>::dumpInsts()
|
FullO3CPU<Impl>::dumpInsts()
|
||||||
{
|
{
|
||||||
int num = 0;
|
int num = 0;
|
||||||
typename list<DynInstPtr>::iterator inst_list_it = instList.begin();
|
typename list<DynInstPtr>::iterator inst_list_it = instList.begin();
|
||||||
|
@ -546,10 +546,10 @@ FullBetaCPU<Impl>::dumpInsts()
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
void
|
void
|
||||||
FullBetaCPU<Impl>::wakeDependents(DynInstPtr &inst)
|
FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
|
||||||
{
|
{
|
||||||
iew.wakeDependents(inst);
|
iew.wakeDependents(inst);
|
||||||
}
|
}
|
||||||
|
|
||||||
// Forward declaration of FullBetaCPU.
|
// Forward declaration of FullO3CPU.
|
||||||
template class FullBetaCPU<AlphaSimpleImpl>;
|
template class FullO3CPU<AlphaSimpleImpl>;
|
||||||
|
|
|
@ -33,8 +33,8 @@
|
||||||
//itself properly. Threads!
|
//itself properly. Threads!
|
||||||
// Avoid running stages and advancing queues if idle/stalled.
|
// Avoid running stages and advancing queues if idle/stalled.
|
||||||
|
|
||||||
#ifndef __CPU_BETA_CPU_FULL_CPU_HH__
|
#ifndef __CPU_O3_CPU_FULL_CPU_HH__
|
||||||
#define __CPU_BETA_CPU_FULL_CPU_HH__
|
#define __CPU_O3_CPU_FULL_CPU_HH__
|
||||||
|
|
||||||
#include <iostream>
|
#include <iostream>
|
||||||
#include <list>
|
#include <list>
|
||||||
|
@ -73,7 +73,7 @@ class BaseFullCPU : public BaseCPU
|
||||||
};
|
};
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
class FullBetaCPU : public BaseFullCPU
|
class FullO3CPU : public BaseFullCPU
|
||||||
{
|
{
|
||||||
public:
|
public:
|
||||||
//Put typedefs from the Impl here.
|
//Put typedefs from the Impl here.
|
||||||
|
@ -96,10 +96,10 @@ class FullBetaCPU : public BaseFullCPU
|
||||||
class TickEvent : public Event
|
class TickEvent : public Event
|
||||||
{
|
{
|
||||||
private:
|
private:
|
||||||
FullBetaCPU<Impl> *cpu;
|
FullO3CPU<Impl> *cpu;
|
||||||
|
|
||||||
public:
|
public:
|
||||||
TickEvent(FullBetaCPU<Impl> *c);
|
TickEvent(FullO3CPU<Impl> *c);
|
||||||
void process();
|
void process();
|
||||||
const char *description();
|
const char *description();
|
||||||
};
|
};
|
||||||
|
@ -123,8 +123,8 @@ class FullBetaCPU : public BaseFullCPU
|
||||||
}
|
}
|
||||||
|
|
||||||
public:
|
public:
|
||||||
FullBetaCPU(Params ¶ms);
|
FullO3CPU(Params ¶ms);
|
||||||
~FullBetaCPU();
|
~FullO3CPU();
|
||||||
|
|
||||||
void fullCPURegStats();
|
void fullCPURegStats();
|
||||||
|
|
||||||
|
|
|
@ -26,8 +26,8 @@
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef __CPU_BETA_CPU_CPU_POLICY_HH__
|
#ifndef __CPU_O3_CPU_CPU_POLICY_HH__
|
||||||
#define __CPU_BETA_CPU_CPU_POLICY_HH__
|
#define __CPU_O3_CPU_CPU_POLICY_HH__
|
||||||
|
|
||||||
#include "cpu/o3/bpred_unit.hh"
|
#include "cpu/o3/bpred_unit.hh"
|
||||||
#include "cpu/o3/free_list.hh"
|
#include "cpu/o3/free_list.hh"
|
||||||
|
@ -85,4 +85,4 @@ struct SimpleCPUPolicy
|
||||||
|
|
||||||
};
|
};
|
||||||
|
|
||||||
#endif //__CPU_BETA_CPU_CPU_POLICY_HH__
|
#endif //__CPU_O3_CPU_CPU_POLICY_HH__
|
||||||
|
|
|
@ -26,8 +26,8 @@
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef __CPU_BETA_CPU_SIMPLE_DECODE_HH__
|
#ifndef __CPU_O3_CPU_SIMPLE_DECODE_HH__
|
||||||
#define __CPU_BETA_CPU_SIMPLE_DECODE_HH__
|
#define __CPU_O3_CPU_SIMPLE_DECODE_HH__
|
||||||
|
|
||||||
#include <queue>
|
#include <queue>
|
||||||
|
|
||||||
|
@ -166,4 +166,4 @@ class SimpleDecode
|
||||||
Stats::Scalar<> decodeSquashedInsts;
|
Stats::Scalar<> decodeSquashedInsts;
|
||||||
};
|
};
|
||||||
|
|
||||||
#endif // __CPU_BETA_CPU_SIMPLE_DECODE_HH__
|
#endif // __CPU_O3_CPU_SIMPLE_DECODE_HH__
|
||||||
|
|
|
@ -29,8 +29,8 @@
|
||||||
// Todo: SMT fetch,
|
// Todo: SMT fetch,
|
||||||
// Add a way to get a stage's current status.
|
// Add a way to get a stage's current status.
|
||||||
|
|
||||||
#ifndef __CPU_BETA_CPU_SIMPLE_FETCH_HH__
|
#ifndef __CPU_O3_CPU_SIMPLE_FETCH_HH__
|
||||||
#define __CPU_BETA_CPU_SIMPLE_FETCH_HH__
|
#define __CPU_O3_CPU_SIMPLE_FETCH_HH__
|
||||||
|
|
||||||
#include "base/statistics.hh"
|
#include "base/statistics.hh"
|
||||||
#include "base/timebuf.hh"
|
#include "base/timebuf.hh"
|
||||||
|
@ -221,4 +221,4 @@ class SimpleFetch
|
||||||
Stats::Distribution<> fetch_nisn_dist;
|
Stats::Distribution<> fetch_nisn_dist;
|
||||||
};
|
};
|
||||||
|
|
||||||
#endif //__CPU_BETA_CPU_SIMPLE_FETCH_HH__
|
#endif //__CPU_O3_CPU_SIMPLE_FETCH_HH__
|
||||||
|
|
|
@ -26,8 +26,8 @@
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef __CPU_BETA_CPU_FREE_LIST_HH__
|
#ifndef __CPU_O3_CPU_FREE_LIST_HH__
|
||||||
#define __CPU_BETA_CPU_FREE_LIST_HH__
|
#define __CPU_O3_CPU_FREE_LIST_HH__
|
||||||
|
|
||||||
#include <iostream>
|
#include <iostream>
|
||||||
#include <queue>
|
#include <queue>
|
||||||
|
@ -192,4 +192,4 @@ SimpleFreeList::addFloatReg(PhysRegIndex freed_reg)
|
||||||
freeFloatRegs.push(freed_reg);
|
freeFloatRegs.push(freed_reg);
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif // __CPU_BETA_CPU_FREE_LIST_HH__
|
#endif // __CPU_O3_CPU_FREE_LIST_HH__
|
||||||
|
|
|
@ -30,8 +30,8 @@
|
||||||
//Need to handle delaying writes to the writeback bus if it's full at the
|
//Need to handle delaying writes to the writeback bus if it's full at the
|
||||||
//given time.
|
//given time.
|
||||||
|
|
||||||
#ifndef __CPU_BETA_CPU_SIMPLE_IEW_HH__
|
#ifndef __CPU_O3_CPU_SIMPLE_IEW_HH__
|
||||||
#define __CPU_BETA_CPU_SIMPLE_IEW_HH__
|
#define __CPU_O3_CPU_SIMPLE_IEW_HH__
|
||||||
|
|
||||||
#include <queue>
|
#include <queue>
|
||||||
|
|
||||||
|
@ -236,4 +236,4 @@ class SimpleIEW
|
||||||
Stats::Scalar<> predictedTakenIncorrect;
|
Stats::Scalar<> predictedTakenIncorrect;
|
||||||
};
|
};
|
||||||
|
|
||||||
#endif // __CPU_BETA_CPU_IEW_HH__
|
#endif // __CPU_O3_CPU_IEW_HH__
|
||||||
|
|
|
@ -26,8 +26,8 @@
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef __CPU_BETA_CPU_INST_QUEUE_HH__
|
#ifndef __CPU_O3_CPU_INST_QUEUE_HH__
|
||||||
#define __CPU_BETA_CPU_INST_QUEUE_HH__
|
#define __CPU_O3_CPU_INST_QUEUE_HH__
|
||||||
|
|
||||||
#include <list>
|
#include <list>
|
||||||
#include <map>
|
#include <map>
|
||||||
|
@ -333,4 +333,4 @@ class InstructionQueue
|
||||||
|
|
||||||
};
|
};
|
||||||
|
|
||||||
#endif //__CPU_BETA_CPU_INST_QUEUE_HH__
|
#endif //__CPU_O3_CPU_INST_QUEUE_HH__
|
||||||
|
|
|
@ -26,8 +26,8 @@
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef __CPU_BETA_CPU_MEM_DEP_UNIT_HH__
|
#ifndef __CPU_O3_CPU_MEM_DEP_UNIT_HH__
|
||||||
#define __CPU_BETA_CPU_MEM_DEP_UNIT_HH__
|
#define __CPU_O3_CPU_MEM_DEP_UNIT_HH__
|
||||||
|
|
||||||
#include <map>
|
#include <map>
|
||||||
#include <set>
|
#include <set>
|
||||||
|
@ -161,4 +161,4 @@ class MemDepUnit {
|
||||||
Stats::Scalar<> conflictingStores;
|
Stats::Scalar<> conflictingStores;
|
||||||
};
|
};
|
||||||
|
|
||||||
#endif // __CPU_BETA_CPU_MEM_DEP_UNIT_HH__
|
#endif // __CPU_O3_CPU_MEM_DEP_UNIT_HH__
|
||||||
|
|
|
@ -26,8 +26,8 @@
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef __CPU_BETA_CPU_RAS_HH__
|
#ifndef __CPU_O3_CPU_RAS_HH__
|
||||||
#define __CPU_BETA_CPU_RAS_HH__
|
#define __CPU_O3_CPU_RAS_HH__
|
||||||
|
|
||||||
// For Addr type.
|
// For Addr type.
|
||||||
#include "arch/alpha/isa_traits.hh"
|
#include "arch/alpha/isa_traits.hh"
|
||||||
|
@ -65,4 +65,4 @@ class ReturnAddrStack
|
||||||
unsigned tos;
|
unsigned tos;
|
||||||
};
|
};
|
||||||
|
|
||||||
#endif // __CPU_BETA_CPU_RAS_HH__
|
#endif // __CPU_O3_CPU_RAS_HH__
|
||||||
|
|
|
@ -26,8 +26,8 @@
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef __CPU_BETA_CPU_REGFILE_HH__
|
#ifndef __CPU_O3_CPU_REGFILE_HH__
|
||||||
#define __CPU_BETA_CPU_REGFILE_HH__
|
#define __CPU_O3_CPU_REGFILE_HH__
|
||||||
|
|
||||||
// @todo: Destructor
|
// @todo: Destructor
|
||||||
|
|
||||||
|
@ -631,4 +631,4 @@ PhysRegFile<Impl>::setIpr(int idx, uint64_t val)
|
||||||
|
|
||||||
#endif // #ifdef FULL_SYSTEM
|
#endif // #ifdef FULL_SYSTEM
|
||||||
|
|
||||||
#endif // __CPU_BETA_CPU_REGFILE_HH__
|
#endif // __CPU_O3_CPU_REGFILE_HH__
|
||||||
|
|
|
@ -31,8 +31,8 @@
|
||||||
// May want to have different statuses to differentiate the different stall
|
// May want to have different statuses to differentiate the different stall
|
||||||
// conditions.
|
// conditions.
|
||||||
|
|
||||||
#ifndef __CPU_BETA_CPU_SIMPLE_RENAME_HH__
|
#ifndef __CPU_O3_CPU_SIMPLE_RENAME_HH__
|
||||||
#define __CPU_BETA_CPU_SIMPLE_RENAME_HH__
|
#define __CPU_O3_CPU_SIMPLE_RENAME_HH__
|
||||||
|
|
||||||
#include <list>
|
#include <list>
|
||||||
|
|
||||||
|
@ -231,4 +231,4 @@ class SimpleRename
|
||||||
Stats::Scalar<> renameValidUndoneMaps;
|
Stats::Scalar<> renameValidUndoneMaps;
|
||||||
};
|
};
|
||||||
|
|
||||||
#endif // __CPU_BETA_CPU_SIMPLE_RENAME_HH__
|
#endif // __CPU_O3_CPU_SIMPLE_RENAME_HH__
|
||||||
|
|
|
@ -30,8 +30,8 @@
|
||||||
// Have it so that there's a more meaningful name given to the variable
|
// Have it so that there's a more meaningful name given to the variable
|
||||||
// that marks the beginning of the FP registers.
|
// that marks the beginning of the FP registers.
|
||||||
|
|
||||||
#ifndef __CPU_BETA_CPU_RENAME_MAP_HH__
|
#ifndef __CPU_O3_CPU_RENAME_MAP_HH__
|
||||||
#define __CPU_BETA_CPU_RENAME_MAP_HH__
|
#define __CPU_O3_CPU_RENAME_MAP_HH__
|
||||||
|
|
||||||
#include <iostream>
|
#include <iostream>
|
||||||
#include <utility>
|
#include <utility>
|
||||||
|
@ -167,4 +167,4 @@ class SimpleRenameMap
|
||||||
std::vector<bool> miscScoreboard;
|
std::vector<bool> miscScoreboard;
|
||||||
};
|
};
|
||||||
|
|
||||||
#endif //__CPU_BETA_CPU_RENAME_MAP_HH__
|
#endif //__CPU_O3_CPU_RENAME_MAP_HH__
|
||||||
|
|
|
@ -1,3 +1,30 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2004-2005 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
#include "cpu/o3/alpha_dyn_inst.hh"
|
#include "cpu/o3/alpha_dyn_inst.hh"
|
||||||
#include "cpu/o3/alpha_impl.hh"
|
#include "cpu/o3/alpha_impl.hh"
|
||||||
|
|
|
@ -32,8 +32,8 @@
|
||||||
// all instructions after the instruction, and all instructions after *and*
|
// all instructions after the instruction, and all instructions after *and*
|
||||||
// including that instruction.
|
// including that instruction.
|
||||||
|
|
||||||
#ifndef __CPU_BETA_CPU_ROB_HH__
|
#ifndef __CPU_O3_CPU_ROB_HH__
|
||||||
#define __CPU_BETA_CPU_ROB_HH__
|
#define __CPU_O3_CPU_ROB_HH__
|
||||||
|
|
||||||
#include <utility>
|
#include <utility>
|
||||||
#include <vector>
|
#include <vector>
|
||||||
|
@ -159,4 +159,4 @@ class ROB
|
||||||
bool doneSquashing;
|
bool doneSquashing;
|
||||||
};
|
};
|
||||||
|
|
||||||
#endif //__CPU_BETA_CPU_ROB_HH__
|
#endif //__CPU_O3_CPU_ROB_HH__
|
||||||
|
|
|
@ -26,8 +26,8 @@
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef __CPU_BETA_CPU_ROB_IMPL_HH__
|
#ifndef __CPU_O3_CPU_ROB_IMPL_HH__
|
||||||
#define __CPU_BETA_CPU_ROB_IMPL_HH__
|
#define __CPU_O3_CPU_ROB_IMPL_HH__
|
||||||
|
|
||||||
#include "cpu/o3/rob.hh"
|
#include "cpu/o3/rob.hh"
|
||||||
|
|
||||||
|
@ -308,4 +308,4 @@ ROB<Impl>::readTailSeqNum()
|
||||||
return (*tail)->seqNum;
|
return (*tail)->seqNum;
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif // __CPU_BETA_CPU_ROB_IMPL_HH__
|
#endif // __CPU_O3_CPU_ROB_IMPL_HH__
|
||||||
|
|
|
@ -26,8 +26,8 @@
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef __CPU_BETA_CPU_SAT_COUNTER_HH__
|
#ifndef __CPU_O3_CPU_SAT_COUNTER_HH__
|
||||||
#define __CPU_BETA_CPU_SAT_COUNTER_HH__
|
#define __CPU_O3_CPU_SAT_COUNTER_HH__
|
||||||
|
|
||||||
#include "sim/host.hh"
|
#include "sim/host.hh"
|
||||||
|
|
||||||
|
@ -87,4 +87,4 @@ class SatCounter
|
||||||
uint8_t counter;
|
uint8_t counter;
|
||||||
};
|
};
|
||||||
|
|
||||||
#endif // __CPU_BETA_CPU_SAT_COUNTER_HH__
|
#endif // __CPU_O3_CPU_SAT_COUNTER_HH__
|
||||||
|
|
|
@ -26,8 +26,8 @@
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef __CPU_BETA_CPU_STORE_SET_HH__
|
#ifndef __CPU_O3_CPU_STORE_SET_HH__
|
||||||
#define __CPU_BETA_CPU_STORE_SET_HH__
|
#define __CPU_O3_CPU_STORE_SET_HH__
|
||||||
|
|
||||||
#include <vector>
|
#include <vector>
|
||||||
|
|
||||||
|
@ -83,4 +83,4 @@ class StoreSet
|
||||||
int offset_bits;
|
int offset_bits;
|
||||||
};
|
};
|
||||||
|
|
||||||
#endif // __CPU_BETA_CPU_STORE_SET_HH__
|
#endif // __CPU_O3_CPU_STORE_SET_HH__
|
||||||
|
|
|
@ -26,8 +26,8 @@
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef __CPU_BETA_CPU_TOURNAMENT_PRED_HH__
|
#ifndef __CPU_O3_CPU_TOURNAMENT_PRED_HH__
|
||||||
#define __CPU_BETA_CPU_TOURNAMENT_PRED_HH__
|
#define __CPU_O3_CPU_TOURNAMENT_PRED_HH__
|
||||||
|
|
||||||
// For Addr type.
|
// For Addr type.
|
||||||
#include "arch/alpha/isa_traits.hh"
|
#include "arch/alpha/isa_traits.hh"
|
||||||
|
@ -140,4 +140,4 @@ class TournamentBP
|
||||||
unsigned threshold;
|
unsigned threshold;
|
||||||
};
|
};
|
||||||
|
|
||||||
#endif // __CPU_BETA_CPU_TOURNAMENT_PRED_HH__
|
#endif // __CPU_O3_CPU_TOURNAMENT_PRED_HH__
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
<hr size="1"><address style="align: right;"><small>
|
<hr size="1"><address style="align: right;"><small>
|
||||||
Generated on $datetime for $projectname by <a href="http://www.doxygen.org/index.html"> doxygen</a> $doxygenversion</small></address>
|
Generated on $datetime for $projectname by <a href="http://www.doxygen.org/index.html"> doxygen</a> $doxygenversion</small></address>
|
||||||
<address><a href="mailto:m5-dev@eecs.umich.edu">M5 Development Team</a></address>
|
|
||||||
|
|
||||||
</body>
|
</body>
|
||||||
</html>
|
</html>
|
||||||
|
|
Loading…
Reference in a new issue