fixed mapping of device memory and i/o space
--HG-- extra : convert_revision : 9236c7f0aeb4d555880bdfdfa7f55cedf1cbb950
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09c40bfe43
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@ -47,6 +47,7 @@
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#include "sim/builder.hh"
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#include "sim/builder.hh"
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#include "sim/param.hh"
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#include "sim/param.hh"
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#include "sim/universe.hh"
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#include "sim/universe.hh"
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#include "dev/tsunamireg.h"
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using namespace std;
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using namespace std;
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@ -176,20 +177,37 @@ PciDev::WriteConfig(int offset, int size, uint32_t data)
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if(config.data[offset] & 0x1) {
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if(config.data[offset] & 0x1) {
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*(uint32_t *)&config.data[offset] = (word_value & ~0x3) |
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*(uint32_t *)&config.data[offset] = (word_value & ~0x3) |
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(config.data[offset] & 0x3);
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(config.data[offset] & 0x3);
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if (word_value) {
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if (word_value & ~0x1) {
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// It's never been set
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// It's never been set
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if (BARAddrs[barnum] == 0)
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if (BARAddrs[barnum] == 0)
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AddMapping(word_value, BARSize[barnum]-1, MMU);
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AddMapping((word_value & ~0x1) + TSUNAMI_PCI0_IO,
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BARSize[barnum]-1, MMU);
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else
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else
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ChangeMapping(BARAddrs[barnum], BARSize[barnum]-1,
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ChangeMapping(BARAddrs[barnum], BARSize[barnum]-1,
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word_value, BARSize[barnum]-1, MMU);
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(word_value & ~0x1) + TSUNAMI_PCI0_IO,
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BARAddrs[barnum] = word_value;
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BARSize[barnum]-1, MMU);
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BARAddrs[barnum] = (word_value & ~0x1) + TSUNAMI_PCI0_IO;
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}
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}
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} else {
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} else {
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// This is memory space, bottom four bits are read only
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// This is memory space, bottom four bits are read only
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*(uint32_t *)&config.data[offset] = (word_value & ~0xF) |
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*(uint32_t *)&config.data[offset] = (word_value & ~0xF) |
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(config.data[offset] & 0xF);
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(config.data[offset] & 0xF);
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if (word_value & ~0x3) {
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// It's never been set
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if (BARAddrs[barnum] == 0)
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AddMapping((word_value & ~0x3) + TSUNAMI_PCI0_MEMORY,
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BARSize[barnum]-1, MMU);
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else
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ChangeMapping(BARAddrs[barnum], BARSize[barnum]-1,
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(word_value & ~0x3) +
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TSUNAMI_PCI0_MEMORY,
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BARSize[barnum]-1, MMU);
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BARAddrs[barnum] = (word_value & ~0x3) +
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TSUNAMI_PCI0_MEMORY;
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}
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}
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}
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}
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}
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break;
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break;
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@ -2,6 +2,8 @@
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#ifndef __TSUNAMIREG_H__
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#ifndef __TSUNAMIREG_H__
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#define __TSUNAMIREG_H__
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#define __TSUNAMIREG_H__
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#define ALPHA_K0SEG_BASE 0xfffffc0000000000
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// CChip Registers
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// CChip Registers
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#define TSDEV_CC_CSR 0x00
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#define TSDEV_CC_CSR 0x00
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#define TSDEV_CC_MTR 0x01
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#define TSDEV_CC_MTR 0x01
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@ -99,5 +101,10 @@
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#define RTC_CONTROL_REGISTERD 13 // control register D
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#define RTC_CONTROL_REGISTERD 13 // control register D
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#define RTC_REGNUMBER_RTC_CR1 0x6A // control register 1
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#define RTC_REGNUMBER_RTC_CR1 0x6A // control register 1
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#define PCHIP_PCI0_MEMORY 0x10000000000
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#define PCHIP_PCI0_IO 0x101FC000000
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#define TSUNAMI_PCI0_MEMORY ALPHA_K0SEG_BASE + PCHIP_PCI0_MEMORY
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#define TSUNAMI_PCI0_IO ALPHA_K0SEG_BASE + PCHIP_PCI0_IO
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#endif // __TSUNAMIREG_H__
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#endif // __TSUNAMIREG_H__
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