diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh index d3ccc0444..0304d1c3a 100644 --- a/src/arch/alpha/utility.hh +++ b/src/arch/alpha/utility.hh @@ -37,16 +37,17 @@ #include "arch/alpha/isa_traits.hh" #include "arch/alpha/regfile.hh" #include "base/misc.hh" +#include "cpu/thread_context.hh" namespace AlphaISA { static inline ExtMachInst - makeExtMI(MachInst inst, const uint64_t &pc) { + makeExtMI(MachInst inst, ThreadContext * xc) { #if FULL_SYSTEM ExtMachInst ext_inst = inst; - if (pc && 0x1) - return ext_inst|=(static_cast(pc & 0x1) << 32); + if (xc->readPC() && 0x1) + return ext_inst|=(static_cast(xc->readPC() & 0x1) << 32); else return ext_inst; #else diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh index ae2fe1aea..56689ba4d 100644 --- a/src/arch/mips/utility.hh +++ b/src/arch/mips/utility.hh @@ -35,6 +35,7 @@ #include "arch/mips/types.hh" #include "base/misc.hh" #include "config/full_system.hh" +#include "cpu/thread_context.hh" //XXX This is needed for size_t. We should use something other than size_t //#include "kern/linux/linux.hh" #include "sim/host.hh" @@ -86,11 +87,11 @@ namespace MipsISA { } static inline ExtMachInst - makeExtMI(MachInst inst, const uint64_t &pc) { + makeExtMI(MachInst inst, ThreadContext * xc) { #if FULL_SYSTEM ExtMachInst ext_inst = inst; - if (pc && 0x1) - return ext_inst|=(static_cast(pc & 0x1) << 32); + if (xc->readPC() && 0x1) + return ext_inst|=(static_cast(xc->readPC() & 0x1) << 32); else return ext_inst; #else diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh index 81f97726c..48458bb1a 100644 --- a/src/cpu/checker/cpu_impl.hh +++ b/src/cpu/checker/cpu_impl.hh @@ -200,7 +200,7 @@ Checker::verify(DynInstPtr &completed_inst) validateInst(inst); curStaticInst = StaticInst::decode(makeExtMI(machInst, - thread->readPC())); + thread->getTC())); #if FULL_SYSTEM thread->setInst(machInst); diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 1e080181c..80e429ae9 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -1109,7 +1109,7 @@ DefaultFetch::fetch(bool &status_change) inst = TheISA::gtoh(*reinterpret_cast (&cacheData[tid][offset])); - ext_inst = TheISA::makeExtMI(inst, fetch_PC); + ext_inst = TheISA::makeExtMI(inst, cpu->tcBase(tid)); // Create a new DynInst from the instruction fetched. DynInstPtr instruction = new DynInst(ext_inst, fetch_PC, diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh index 1b120460a..8a15378a7 100644 --- a/src/cpu/ozone/front_end_impl.hh +++ b/src/cpu/ozone/front_end_impl.hh @@ -842,7 +842,7 @@ FrontEnd::getInstFromCacheline() // Get the instruction from the array of the cache line. inst = htog(*reinterpret_cast(&cacheData[offset])); - ExtMachInst decode_inst = TheISA::makeExtMI(inst, PC); + ExtMachInst decode_inst = TheISA::makeExtMI(inst, tc); // Create a new DynInst from the instruction fetched. DynInstPtr instruction = new DynInst(decode_inst, PC, PC+sizeof(MachInst), diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index f801b93fa..025314fcb 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -396,7 +396,7 @@ BaseSimpleCPU::preExecute() // decode the instruction inst = gtoh(inst); - curStaticInst = StaticInst::decode(makeExtMI(inst, thread->readPC())); + curStaticInst = StaticInst::decode(makeExtMI(inst, thread->getTC())); traceData = Trace::getInstRecord(curTick, tc, curStaticInst, thread->readPC());