Clean up the code a little, fix (I think) a perceived problem with immediate sizes, and sign extend the 32-bit-acting-like-64-bit-immediates.
--HG-- extra : convert_revision : e59b747198cc79d50045bd2dc45b2e2b97bbffcc
This commit is contained in:
Gabe Black
parent
e633e23a3a
commit
75e8838ba4
5 changed files with 85 additions and 48 deletions
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@ -117,37 +117,33 @@ namespace X86ISA
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//Operand size override prefixes
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case OperandSizeOverride:
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DPRINTF(Predecoder, "Found operand size override prefix.\n");
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emi.legacy.op = true;
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break;
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case AddressSizeOverride:
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DPRINTF(Predecoder, "Found address size override prefix.\n");
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emi.legacy.addr = true;
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break;
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//Segment override prefixes
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case CSOverride:
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DPRINTF(Predecoder, "Found cs segment override.\n");
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break;
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case DSOverride:
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DPRINTF(Predecoder, "Found ds segment override.\n");
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break;
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case ESOverride:
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DPRINTF(Predecoder, "Found es segment override.\n");
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break;
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case FSOverride:
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DPRINTF(Predecoder, "Found fs segment override.\n");
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break;
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case GSOverride:
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DPRINTF(Predecoder, "Found gs segment override.\n");
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break;
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case SSOverride:
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DPRINTF(Predecoder, "Found ss segment override.\n");
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DPRINTF(Predecoder, "Found segment override.\n");
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emi.legacy.seg = prefix;
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break;
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case Lock:
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DPRINTF(Predecoder, "Found lock prefix.\n");
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emi.legacy.lock = true;
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break;
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case Rep:
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DPRINTF(Predecoder, "Found rep prefix.\n");
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emi.legacy.rep = true;
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break;
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case Repne:
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DPRINTF(Predecoder, "Found repne prefix.\n");
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emi.legacy.repne = true;
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break;
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case RexPrefix:
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DPRINTF(Predecoder, "Found Rex prefix %#x.\n", nextByte);
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@ -198,16 +194,36 @@ namespace X86ISA
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displacementCollected = 0;
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emi.displacement = 0;
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//Figure out the effective operand size. This can be overriden to
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//a fixed value at the decoder level.
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if(/*FIXME long mode*/1)
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{
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if(emi.rex && emi.rex.w)
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emi.opSize = 3; // 64 bit operand size
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else if(emi.legacy.op)
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emi.opSize = 1; // 16 bit operand size
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else
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emi.opSize = 2; // 32 bit operand size
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}
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else if(/*FIXME default 32*/1)
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{
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if(emi.legacy.op)
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emi.opSize = 1; // 16 bit operand size
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else
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emi.opSize = 2; // 32 bit operand size
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}
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else // 16 bit default operand size
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{
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if(emi.legacy.op)
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emi.opSize = 2; // 32 bit operand size
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else
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emi.opSize = 1; // 16 bit operand size
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}
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//Figure out how big of an immediate we'll retreive based
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//on the opcode.
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int immType = ImmediateType[
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emi.opcode.num - 1][nextByte];
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if(0) //16 bit mode
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immediateSize = ImmediateTypeToSize[0][immType];
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else if(!(emi.rex & 0x4)) //32 bit mode
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immediateSize = ImmediateTypeToSize[1][immType];
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else //64 bit mode
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immediateSize = ImmediateTypeToSize[2][immType];
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int immType = ImmediateType[emi.opcode.num - 1][nextByte];
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immediateSize = SizeTypeToSize[emi.opSize - 1][immType];
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//Determine what to expect next
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if (UsesModRM[emi.opcode.num - 1][nextByte]) {
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@ -351,6 +367,16 @@ namespace X86ISA
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if(immediateSize == immediateCollected)
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{
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//XXX Warning! The following is an observed pattern and might
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//not always be true!
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//Instructions which use 64 bit operands but 32 bit immediates
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//need to have the immediate sign extended to 64 bits.
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//Instructions which use true 64 bit immediates won't be
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//affected, and instructions that use true 32 bit immediates
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//won't notice.
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if(immediateSize == 4)
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emi.immediate = sext<32>(emi.immediate);
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DPRINTF(Predecoder, "Collected immediate %#x.\n",
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emi.immediate);
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emiIsReady = true;
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@ -73,7 +73,7 @@ namespace X86ISA
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static const uint8_t Prefixes[256];
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static const uint8_t UsesModRM[2][256];
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static const uint8_t ImmediateType[2][256];
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static const uint8_t ImmediateTypeToSize[3][10];
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static const uint8_t SizeTypeToSize[3][10];
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protected:
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ThreadContext * tc;
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@ -141,7 +141,7 @@ namespace X86ISA
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}
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};
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enum ImmediateTypes {
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enum SizeType {
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NoImm,
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NI = NoImm,
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ByteImm,
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@ -158,19 +158,19 @@ namespace X86ISA
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VW = VWordImm,
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ZWordImm,
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ZW = ZWordImm,
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Pointer,
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PO = Pointer,
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//The enter instruction takes -2- immediates for a total of 3 bytes
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Enter,
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EN = Enter
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EN = Enter,
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Pointer,
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PO = Pointer
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};
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const uint8_t Predecoder::ImmediateTypeToSize[3][10] =
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const uint8_t Predecoder::SizeTypeToSize[3][10] =
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{
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// noimm byte word dword qword oword vword zword enter
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{0, 1, 2, 4, 8, 16, 2, 2, 3, 4}, //16 bit
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{0, 1, 2, 4, 8, 16, 4, 4, 3, 6}, //32 bit
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{0, 1, 2, 4, 8, 16, 4, 8, 3, 0} //64 bit
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// noimm byte word dword qword oword vword zword enter pointer
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{0, 1, 2, 4, 8, 16, 2, 2, 3, 4 }, //16 bit
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{0, 1, 2, 4, 8, 16, 4, 4, 3, 6 }, //32 bit
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{0, 1, 2, 4, 8, 16, 4, 8, 3, 0 } //64 bit
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};
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//This table determines the immediate type. The first index is the
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@ -70,25 +70,31 @@ namespace X86ISA
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typedef uint64_t MachInst;
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enum Prefixes {
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NoOverride = 0,
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CSOverride = 1,
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DSOverride = 2,
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ESOverride = 3,
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FSOverride = 4,
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GSOverride = 5,
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SSOverride = 6,
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//The Rex prefix obviously doesn't fit in with the above, but putting
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//it here lets us save double the space the enums take up.
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RexPrefix = 7,
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NoOverride,
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CSOverride,
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DSOverride,
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ESOverride,
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FSOverride,
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GSOverride,
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SSOverride,
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RexPrefix,
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OperandSizeOverride,
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AddressSizeOverride,
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Lock,
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Rep,
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Repne
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};
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BitUnion8(LegacyPrefixVector)
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Bitfield<7> repne;
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Bitfield<6> rep;
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Bitfield<5> lock;
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Bitfield<4> addr;
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Bitfield<3> op;
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//There can be only one segment override, so they share the
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//first 3 bits in the legacyPrefixes bitfield.
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SegmentOverride = 0x7,
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OperandSizeOverride = 8,
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AddressSizeOverride = 16,
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Lock = 32,
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Rep = 64,
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Repne = 128
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};
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Bitfield<2,0> seg;
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EndBitUnion(LegacyPrefixVector)
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BitUnion8(ModRM)
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Bitfield<7,6> mod;
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@ -118,7 +124,7 @@ namespace X86ISA
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struct ExtMachInst
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{
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//Prefixes
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uint8_t legacy;
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LegacyPrefixVector legacy;
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Rex rex;
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//This holds all of the bytes of the opcode
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struct
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@ -140,6 +146,10 @@ namespace X86ISA
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//Immediate fields
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uint64_t immediate;
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uint64_t displacement;
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//The effective operand size.
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uint8_t opSize;
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//The
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};
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inline static std::ostream &
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@ -78,7 +78,8 @@ namespace __hash_namespace {
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((uint64_t)emi.opcode.prefixA << 16) |
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((uint64_t)emi.opcode.prefixB << 8) |
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((uint64_t)emi.opcode.op)) ^
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emi.immediate ^ emi.displacement;
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emi.immediate ^ emi.displacement ^
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emi.opSize;
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};
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};
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}
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