Flattening and syscallReturn fixes
src/cpu/o3/thread_context_impl.hh: Use flattened indices src/cpu/simple_thread.hh: Use flattened indices, and pass a thread context to setSyscallReturn rather than a register file. src/cpu/thread_context.hh: The SyscallReturn class is no longer in arch/syscallreturn.hh --HG-- extra : convert_revision : ed84bb8ac5ef0774526ecd0d7270b0c60cd3708e
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3 changed files with 13 additions and 6 deletions
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@ -29,6 +29,7 @@
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* Korey Sewell
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* Korey Sewell
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*/
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*/
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#include "arch/regfile.hh"
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#include "cpu/o3/thread_context.hh"
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#include "cpu/o3/thread_context.hh"
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#include "cpu/quiesce_event.hh"
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#include "cpu/quiesce_event.hh"
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@ -303,6 +304,7 @@ template <class Impl>
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uint64_t
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uint64_t
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O3ThreadContext<Impl>::readIntReg(int reg_idx)
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O3ThreadContext<Impl>::readIntReg(int reg_idx)
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{
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{
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reg_idx = TheISA::flattenIntIndex(this, reg_idx);
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return cpu->readArchIntReg(reg_idx, thread->readTid());
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return cpu->readArchIntReg(reg_idx, thread->readTid());
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}
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}
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@ -347,6 +349,7 @@ template <class Impl>
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void
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void
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O3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val)
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O3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val)
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{
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{
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reg_idx = TheISA::flattenIntIndex(this, reg_idx);
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cpu->setArchIntReg(reg_idx, val, thread->readTid());
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cpu->setArchIntReg(reg_idx, val, thread->readTid());
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// Squash if we're not already in a state update mode.
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// Squash if we're not already in a state update mode.
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@ -33,6 +33,8 @@
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#define __CPU_SIMPLE_THREAD_HH__
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#define __CPU_SIMPLE_THREAD_HH__
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#include "arch/isa_traits.hh"
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#include "arch/isa_traits.hh"
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#include "arch/regfile.hh"
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#include "arch/syscallreturn.hh"
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#include "config/full_system.hh"
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#include "config/full_system.hh"
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#include "cpu/thread_context.hh"
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#include "cpu/thread_context.hh"
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#include "cpu/thread_state.hh"
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#include "cpu/thread_state.hh"
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@ -319,7 +321,7 @@ class SimpleThread : public ThreadState
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//
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//
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uint64_t readIntReg(int reg_idx)
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uint64_t readIntReg(int reg_idx)
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{
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{
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return regs.readIntReg(reg_idx);
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return regs.readIntReg(TheISA::flattenIntIndex(getTC(), reg_idx));
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}
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}
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FloatReg readFloatReg(int reg_idx, int width)
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FloatReg readFloatReg(int reg_idx, int width)
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@ -344,7 +346,7 @@ class SimpleThread : public ThreadState
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void setIntReg(int reg_idx, uint64_t val)
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void setIntReg(int reg_idx, uint64_t val)
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{
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{
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regs.setIntReg(reg_idx, val);
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regs.setIntReg(TheISA::flattenIntIndex(getTC(), reg_idx), val);
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}
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}
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void setFloatReg(int reg_idx, FloatReg val, int width)
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void setFloatReg(int reg_idx, FloatReg val, int width)
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@ -445,18 +447,20 @@ class SimpleThread : public ThreadState
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#if !FULL_SYSTEM
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#if !FULL_SYSTEM
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TheISA::IntReg getSyscallArg(int i)
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TheISA::IntReg getSyscallArg(int i)
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{
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{
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return regs.readIntReg(TheISA::ArgumentReg0 + i);
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return regs.readIntReg(TheISA::flattenIntIndex(getTC(),
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TheISA::ArgumentReg0 + i));
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}
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}
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// used to shift args for indirect syscall
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// used to shift args for indirect syscall
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void setSyscallArg(int i, TheISA::IntReg val)
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void setSyscallArg(int i, TheISA::IntReg val)
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{
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{
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regs.setIntReg(TheISA::ArgumentReg0 + i, val);
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regs.setIntReg(TheISA::flattenIntIndex(getTC(),
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TheISA::ArgumentReg0 + i), val);
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}
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}
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void setSyscallReturn(SyscallReturn return_value)
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void setSyscallReturn(SyscallReturn return_value)
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{
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{
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TheISA::setSyscallReturn(return_value, ®s);
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TheISA::setSyscallReturn(return_value, getTC());
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}
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}
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void syscall(int64_t callnum)
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void syscall(int64_t callnum)
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@ -32,13 +32,13 @@
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#define __CPU_THREAD_CONTEXT_HH__
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#define __CPU_THREAD_CONTEXT_HH__
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#include "arch/regfile.hh"
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#include "arch/regfile.hh"
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#include "arch/syscallreturn.hh"
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#include "arch/types.hh"
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#include "arch/types.hh"
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#include "config/full_system.hh"
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#include "config/full_system.hh"
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#include "mem/request.hh"
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#include "mem/request.hh"
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#include "sim/faults.hh"
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#include "sim/faults.hh"
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#include "sim/host.hh"
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#include "sim/host.hh"
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#include "sim/serialize.hh"
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#include "sim/serialize.hh"
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#include "sim/syscallreturn.hh"
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#include "sim/byteswap.hh"
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#include "sim/byteswap.hh"
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// @todo: Figure out a more architecture independent way to obtain the ITB and
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// @todo: Figure out a more architecture independent way to obtain the ITB and
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