Get simple cpu to compile.
Now I need to fix linking errors, probably due to missing function details in new memory objects.
cpu/exec_context.cc:
cpu/exec_context.hh:
Fix constructor for SE mode
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
Fix compilation errors
--HG--
extra : convert_revision : 6a58c0906340e10b654369c36f528fc17e3f19be
This commit is contained in:
Ron Dreslinski
parent
3391354285
commit
75152fcaf7
4 changed files with 28 additions and 43 deletions
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@ -77,11 +77,10 @@ ExecContext::ExecContext(BaseCPU *_cpu, int _thread_num, System *_sys,
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profilePC = 3;
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}
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#else
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ExecContext::ExecContext(BaseCPU *_cpu, int _thread_num, System *_system,
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Memory *_mem, Process *_process, int _asid)
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ExecContext::ExecContext(BaseCPU *_cpu, int _thread_num,
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Process *_process, int _asid)
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: _status(ExecContext::Unallocated),
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cpu(_cpu), thread_num(_thread_num), cpu_id(-1),
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system(_system),
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process(_process),
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asid(_asid),
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func_exe_inst(0), storeCondFailures(0)
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@ -186,8 +186,8 @@ class ExecContext
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ExecContext(BaseCPU *_cpu, int _thread_num, System *_system,
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AlphaITB *_itb, AlphaDTB *_dtb, FunctionalMemory *_dem);
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#else
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ExecContext(BaseCPU *_cpu, int _thread_num, System *_system,
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Memory *_mem, Process *_process, int _asid);
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ExecContext(BaseCPU *_cpu, int _thread_num,
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Process *_process, int _asid);
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#endif
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virtual ~ExecContext();
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@ -52,8 +52,6 @@
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#include "cpu/smt.hh"
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#include "cpu/static_inst.hh"
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#include "kern/kernel_stats.hh"
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#include "mem/base_mem.hh"
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#include "mem/mem_interface.hh"
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#include "sim/builder.hh"
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#include "sim/debug.hh"
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#include "sim/host.hh"
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@ -70,7 +68,7 @@
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#include "targetarch/stacktrace.hh"
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#include "targetarch/vtophys.hh"
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#else // !FULL_SYSTEM
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#include "mem/functional/functional.hh"
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#include "mem/memory.hh"
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#endif // FULL_SYSTEM
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using namespace std;
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@ -97,12 +95,6 @@ SimpleCPU::TickEvent::description()
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}
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SimpleCPU::CacheCompletionEvent::CacheCompletionEvent(SimpleCPU *_cpu)
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: Event(&mainEventQueue), cpu(_cpu)
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{
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}
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bool
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SimpleCPU::CpuPort::recvTiming(Packet &pkt)
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{
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@ -139,8 +131,8 @@ SimpleCPU::CpuPort::recvRetry()
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SimpleCPU::SimpleCPU(Params *p)
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: BaseCPU(p), tickEvent(this, p->width), xc(NULL),
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cacheCompletionEvent(this), dcachePort(this), icachePort(this)
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: BaseCPU(p), icachePort(this),
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dcachePort(this), tickEvent(this, p->width), xc(NULL)
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{
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_status = Idle;
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#if FULL_SYSTEM
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@ -152,7 +144,7 @@ SimpleCPU::SimpleCPU(Params *p)
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xc = new ExecContext(this, /* thread_num */ 0, p->process, /* asid */ 0);
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#endif // !FULL_SYSTEM
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xc->memPort = dcachePort;
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memPort = &dcachePort;
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req = new CpuRequest;
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@ -324,7 +316,6 @@ SimpleCPU::serialize(ostream &os)
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nameOut(os, csprintf("%s.tickEvent", name()));
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tickEvent.serialize(os);
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nameOut(os, csprintf("%s.cacheCompletionEvent", name()));
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cacheCompletionEvent.serialize(os);
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}
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void
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@ -335,8 +326,6 @@ SimpleCPU::unserialize(Checkpoint *cp, const string §ion)
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UNSERIALIZE_SCALAR(inst);
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xc->unserialize(cp, csprintf("%s.xc", section));
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tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
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cacheCompletionEvent
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.unserialize(cp, csprintf("%s.cacheCompletionEvent", section));
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}
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void
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@ -365,7 +354,7 @@ SimpleCPU::copySrcTranslate(Addr src)
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memReq->reset(src & ~(blk_size - 1), blk_size);
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// translate to physical address
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Fault fault = xc->translateDataReadReq(memReq);
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Fault fault = xc->translateDataReadReq(req);
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assert(fault != Alignment_Fault);
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@ -378,7 +367,7 @@ SimpleCPU::copySrcTranslate(Addr src)
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}
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return fault;
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#else
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return No_Fault
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return No_Fault;
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#endif
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}
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@ -404,7 +393,7 @@ SimpleCPU::copy(Addr dest)
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memReq->reset(dest & ~(blk_size -1), blk_size);
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// translate to physical address
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Fault fault = xc->translateDataWriteReq(memReq);
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Fault fault = xc->translateDataWriteReq(req);
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assert(fault != Alignment_Fault);
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@ -456,7 +445,7 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags)
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// translate to physical address
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// NEED NEW TRANSLATION HERE
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Fault fault = xc->translateDataReadReq(memReq);
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Fault fault = xc->translateDataReadReq(req);
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// Now do the access.
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if (fault == No_Fault) {
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@ -496,7 +485,7 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags)
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}
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*/
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// This will need a new way to tell if it has a dcache attached.
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if (/*!dcacheInterface && */(memReq->flags & UNCACHEABLE))
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if (/*!dcacheInterface && */(req->flags & UNCACHEABLE))
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recordEvent("Uncached Read");
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return fault;
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@ -556,7 +545,7 @@ SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
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// translate to physical address
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// NEED NEW TRANSLATION HERE
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Fault fault = xc->translateDataWriteReq(memReq);
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Fault fault = xc->translateDataWriteReq(req);
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// Now do the access.
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if (fault == No_Fault) {
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@ -597,10 +586,10 @@ SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
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}
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*/
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if (res && (fault == No_Fault))
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*res = memReq->result;
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*res = pkt->result;
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// This will need a new way to tell if it's hooked up to a cache or not.
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if (/*!dcacheInterface && */(memReq->flags & UNCACHEABLE))
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if (/*!dcacheInterface && */(req->flags & UNCACHEABLE))
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recordEvent("Uncached Write");
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// If the write needs to have a fault on the access, consider calling
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@ -663,7 +652,7 @@ void
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SimpleCPU::sendIcacheRequest()
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{
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#if 1
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bool success = icachePort.sendTiming(pkt);
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bool success = icachePort.sendTiming(*pkt);
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unscheduleTickEvent();
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@ -697,7 +686,7 @@ SimpleCPU::sendDcacheRequest()
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unscheduleTickEvent();
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#if 1
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bool success = dcachePort.sendTiming(pkt);
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bool success = dcachePort.sendTiming(*pkt);
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lastDcacheStall = curTick;
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@ -722,12 +711,12 @@ SimpleCPU::sendDcacheRequest()
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}
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void
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SimpleCPU::processResponse(Packet *response)
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SimpleCPU::processResponse(Packet &response)
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{
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// For what things is the CPU the consumer of the packet it sent
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// out? This may create a memory leak if that's the case and it's
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// expected of the SimpleCPU to delete its own packet.
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pkt = response;
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pkt = &response;
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switch (status()) {
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case IcacheWaitResponse:
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@ -742,7 +731,7 @@ SimpleCPU::processResponse(Packet *response)
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delete pkt;
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break;
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case DcacheWaitResponse:
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if (req->cmd.isRead()) {
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if (pkt->cmd == Read) {
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curStaticInst->execute(this,traceData);
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if (traceData)
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traceData->finalize();
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@ -755,7 +744,7 @@ SimpleCPU::processResponse(Packet *response)
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scheduleTickEvent(1);
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break;
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case DcacheWaitSwitch:
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if (memReq->cmd.isRead()) {
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if (pkt->cmd == Read) {
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curStaticInst->execute(this,traceData);
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if (traceData)
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traceData->finalize();
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@ -893,7 +882,7 @@ SimpleCPU::tick()
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IFETCH_FLAGS(xc->regs.pc));
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*/
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//NEED NEW TRANSLATION HERE
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fault = xc->translateInstReq(memReq);
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fault = xc->translateInstReq(req);
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if (fault == No_Fault) {
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pkt = new Packet;
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@ -980,7 +969,7 @@ SimpleCPU::tick()
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// If we have a dcache miss, then we can't finialize the instruction
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// trace yet because we want to populate it with the data later
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if (traceData &&
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!(status() == DcacheWaitResponse && memReq->cmd.isRead())) {
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!(status() == DcacheWaitResponse && pkt->cmd == Read)) {
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traceData->finalize();
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}
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@ -1040,8 +1029,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
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#endif // FULL_SYSTEM
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Param<int> clock;
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SimObjectParam<BaseMem *> icache;
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SimObjectParam<BaseMem *> dcache;
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Param<bool> defer_registration;
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Param<int> width;
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@ -1073,8 +1060,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
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#endif // FULL_SYSTEM
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INIT_PARAM(clock, "clock speed"),
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INIT_PARAM(icache, "L1 instruction cache object"),
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INIT_PARAM(dcache, "L1 data cache object"),
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INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
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INIT_PARAM(width, "cpu width"),
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INIT_PARAM(function_trace, "Enable function trace"),
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@ -1096,8 +1081,6 @@ CREATE_SIM_OBJECT(SimpleCPU)
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params->clock = clock;
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params->functionTrace = function_trace;
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params->functionTraceStart = function_trace_start;
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params->icache_interface = (icache) ? icache->getInterface() : NULL;
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params->dcache_interface = (dcache) ? dcache->getInterface() : NULL;
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params->width = width;
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#if FULL_SYSTEM
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@ -248,7 +248,10 @@ class SimpleCPU : public BaseCPU
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void sendIcacheRequest();
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void sendDcacheRequest();
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void processResponse(Packet *response);
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void processResponse(Packet &response);
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Packet * processRetry();
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void recvStatusChange(Port::Status status) {}
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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