dev, arm: Add a platform with support for both aarch32 and aarch64
Add a platform with support for both aarch32 and aarch64. This
platform implements a subset of the devices in a real Versatile
Express and extends it with some gem5-specific functionality. It is in
many ways similar to the old VExpress_EMM64 platform, but supports the
following new features:
* Automatic PCI interrupt assignment
* PCI interrupts allocated in a contiguous range.
* Automatic boot loader selection (32-bit / 64-bit)
* Cleaner memory map where gem5-specific devices live in CS5 which
isn't used by current Versatile Express platforms.
* No fake devices. Devices that were previously faked will be
removed from the device tree instead.
* Support for 510 GiB contiguous memory
This commit is contained in:
Andreas Sandberg
parent
6d058a63b0
commit
745f8229f6
3 changed files with 218 additions and 7 deletions
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@ -220,6 +220,8 @@ def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None,
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"VExpress_EMM64": "vmlinux.aarch64.20140821",
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}
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pci_devices = []
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if bare_metal:
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self = ArmSystem()
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else:
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@ -257,16 +259,22 @@ def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None,
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print "Selected 64-bit ARM architecture, updating default disk image..."
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mdesc.diskname = 'linaro-minimal-aarch64.img'
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self.cf0 = CowIdeDisk(driveID='master')
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self.cf0.childImage(mdesc.disk())
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# Attach any PCI devices this platform supports
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self.realview.attachPciDevices()
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# default to an IDE controller rather than a CF one
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try:
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self.cf0 = CowIdeDisk(driveID='master')
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self.cf0.childImage(mdesc.disk())
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# Old platforms have a built-in IDE or CF controller. Default to
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# the IDE controller if both exist. New platforms expect the
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# storage controller to be added from the config script.
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if hasattr(self.realview, "ide"):
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self.realview.ide.disks = [self.cf0]
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except:
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elif hasattr(self.realview, "cf_ctrl"):
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self.realview.cf_ctrl.disks = [self.cf0]
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else:
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self.pci_ide = IdeController(disks=[self.cf0])
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pci_devices.append(self.pci_ide)
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self.mem_ranges = []
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size_remain = long(Addr(mdesc.mem()))
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@ -360,7 +368,13 @@ def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None,
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self.realview.attachOnChipIO(self.iobus)
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else:
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self.realview.attachOnChipIO(self.membus, self.bridge)
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# Attach off-chip devices
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self.realview.attachIO(self.iobus)
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for dev_id, dev in enumerate(pci_devices):
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dev.pci_bus, dev.pci_dev, dev.pci_func = (0, dev_id + 1, 0)
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self.realview.attachPciDevice(dev, self.iobus)
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self.intrctrl = IntrControl()
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self.terminal = Terminal()
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self.vncserver = VncServer()
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@ -48,6 +48,7 @@ _platform_classes = {}
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_platform_aliases_all = [
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("RealView_EB", "RealViewEB"),
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("RealView_PBX", "RealViewPBX"),
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("VExpress_GEM5", "VExpress_GEM5_V1"),
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]
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# Filtered list of aliases. Only aliases for existing platforms exist
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@ -271,6 +271,26 @@ class RealView(Platform):
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system = Param.System(Parent.any, "system")
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_mem_regions = [(Addr(0), Addr('256MB'))]
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def _on_chip_devices(self):
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return []
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def _off_chip_devices(self):
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return []
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_off_chip_ranges = []
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def _attach_io(self, devices, bus):
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for d in devices:
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if hasattr(d, "pio"):
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d.pio = bus.master
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if hasattr(d, "dma"):
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d.dma = bus.slave
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def _attach_clk(self, devices, clkdomain):
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for d in devices:
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if hasattr(d, "clk_domain"):
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d.clk_domain = clkdomain
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def attachPciDevices(self):
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pass
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@ -278,10 +298,19 @@ class RealView(Platform):
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pass
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def onChipIOClkDomain(self, clkdomain):
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pass
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self._attach_clk(self._on_chip_devices(), clkdomain)
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def offChipIOClkDomain(self, clkdomain):
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pass
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self._attach_clk(self._off_chip_devices(), clkdomain)
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def attachOnChipIO(self, bus, bridge=None):
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self._attach_io(self._on_chip_devices(), bus)
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if bridge:
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bridge.ranges = self._off_chip_ranges
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def attachIO(self, bus):
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self._attach_io(self._off_chip_devices(), bus)
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def setupBootLoader(self, mem_bus, cur_sys, loc):
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self.nvmem = SimpleMemory(range = AddrRange('2GB', size = '64MB'),
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@ -716,3 +745,170 @@ class VExpress_EMM64(VExpress_EMM):
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cur_sys.load_offset = 0x80000000
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class VExpress_GEM5_V1(RealView):
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"""
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The VExpress gem5 memory map is loosely based on a modified
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Versatile Express RS1 memory map.
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The gem5 platform has been designed to implement a subset of the
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original Versatile Express RS1 memory map. Off-chip peripherals should,
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when possible, adhere to the Versatile Express memory map. Non-PCI
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off-chip devices that are gem5-specific should live in the CS5 memory
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space to avoid conflicts with existing devices that we might want to
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model in the future. Such devices should normally have interrupts in
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the gem5-specific SPI range.
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On-chip peripherals are loosely modeled after the ARM CoreTile Express
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A15x2 A7x3 memory and interrupt map. In particular, the GIC and
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Generic Timer have the same interrupt lines and base addresses. Other
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on-chip devices are gem5 specific.
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Unlike the original Versatile Express RS2 extended platform, gem5 implements a
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large contigious DRAM space, without aliases or holes, starting at the
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2GiB boundary. This means that PCI memory is limited to 1GiB.
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Memory map:
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0x00000000-0x03ffffff: Boot memory (CS0)
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0x04000000-0x07ffffff: Reserved
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0x08000000-0x0bffffff: Reserved (CS0 alias)
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0x0c000000-0x0fffffff: Reserved (Off-chip, CS4)
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0x10000000-0x13ffffff: gem5-specific peripherals (Off-chip, CS5)
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0x10000000-0x1000ffff: gem5 energy controller
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0x14000000-0x17ffffff: Reserved (Off-chip, PSRAM, CS1)
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0x18000000-0x1bffffff: Reserved (Off-chip, Peripherals, CS2)
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0x1c000000-0x1fffffff: Peripheral block 1 (Off-chip, CS3):
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0x1c010000-0x1c01ffff: realview_io (VE system control regs.)
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0x1c060000-0x1c06ffff: KMI0 (keyboard)
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0x1c070000-0x1c07ffff: KMI1 (mouse)
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0x1c090000-0x1c09ffff: UART0
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0x1c0a0000-0x1c0affff: UART1 (reserved)
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0x1c0b0000-0x1c0bffff: UART2 (reserved)
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0x1c0c0000-0x1c0cffff: UART3 (reserved)
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0x1c170000-0x1c17ffff: RTC
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0x20000000-0x3fffffff: On-chip peripherals:
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0x2b000000-0x2b00ffff: HDLCD
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0x2c001000-0x2c001fff: GIC (distributor)
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0x2c002000-0x2c0020ff: GIC (CPU interface)
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0x2c004000-0x2c005fff: vGIC (HV)
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0x2c006000-0x2c007fff: vGIC (VCPU)
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0x2c1c0000-0x2c1cffff: GICv2m MSI frame 0
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0x2d000000-0x2d00ffff: GPU (reserved)
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0x2f000000-0x2fffffff: PCI IO space
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0x30000000-0x3fffffff: PCI config space
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0x40000000-0x7fffffff: Ext. AXI: Used as PCI memory
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0x80000000-X: DRAM
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Interrupts:
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0- 15: Software generated interrupts (SGIs)
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16- 31: On-chip private peripherals (PPIs)
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25 : vgic
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26 : generic_timer (hyp)
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27 : generic_timer (virt)
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28 : Reserved (Legacy FIQ)
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29 : generic_timer (phys, sec)
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30 : generic_timer (phys, non-sec)
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31 : Reserved (Legacy IRQ)
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32- 95: Mother board peripherals (SPIs)
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32 : Reserved (SP805)
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33 : Reserved (IOFPGA SW int)
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34-35: Reserved (SP804)
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36 : RTC
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37-40: uart0-uart3
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41-42: Reserved (PL180)
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43 : Reserved (AACI)
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44-45: kmi0-kmi1
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46 : Reserved (CLCD)
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47 : Reserved (Ethernet)
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48 : Reserved (USB)
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95-255: On-chip interrupt sources (we use these for
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gem5-specific devices, SPIs)
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95 : HDLCD
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96- 98: GPU (reserved)
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100-103: PCI
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256-319: MSI frame 0 (gem5-specific, SPIs)
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320-511: Unused
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"""
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# Everything above 2GiB is memory
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_mem_regions = [(Addr('2GB'), Addr('510GB'))]
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_off_chip_ranges = [
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# CS1-CS5
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AddrRange(0x0c000000, 0x1fffffff),
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# External AXI interface (PCI)
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AddrRange(0x2f000000, 0x7fffffff),
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]
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# Platform control device (off-chip)
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realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000,
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idreg=0x02250000, pio_addr=0x1c010000)
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mcc = VExpressMCC()
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dcc = CoreTile2A15DCC()
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### On-chip devices ###
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gic = Pl390(dist_addr=0x2c001000, cpu_addr=0x2c002000, it_lines=512)
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vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25)
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gicv2m = Gicv2m()
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gicv2m.frames = [
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Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2c1c0000),
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]
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generic_timer = GenericTimer(int_phys=29, int_virt=27)
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hdlcd = HDLcd(pxl_clk=dcc.osc_pxl,
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pio_addr=0x2b000000, int_num=95)
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def _on_chip_devices(self):
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return [
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self.gic, self.vgic, self.gicv2m,
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self.hdlcd,
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self.generic_timer,
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]
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### Off-chip devices ###
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uart0 = Pl011(pio_addr=0x1c090000, int_num=37)
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kmi0 = Pl050(pio_addr=0x1c060000, int_num=44)
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kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True)
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rtc = PL031(pio_addr=0x1c170000, int_num=36)
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### gem5-specific off-chip devices ###
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pci_host = GenericArmPciHost(
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conf_base=0x30000000, conf_size='256MB', conf_device_bits=12,
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pci_pio_base=0x2f000000,
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int_policy="ARM_PCI_INT_DEV", int_base=100, int_count=4)
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energy_ctrl = EnergyCtrl(pio_addr=0x10000000)
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def _off_chip_devices(self):
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return [
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self.realview_io,
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self.uart0,
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self.kmi0, self.kmi1,
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self.rtc,
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self.pci_host,
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self.energy_ctrl,
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]
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def attachPciDevice(self, device, bus):
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device.host = self.pci_host
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device.pio = bus.master
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device.dma = bus.slave
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def setupBootLoader(self, mem_bus, cur_sys, loc):
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self.nvmem = SimpleMemory(range=AddrRange(0, size='64MB'))
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self.nvmem.port = mem_bus.master
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cur_sys.boot_loader = [ loc('boot_emm.arm64'), loc('boot_emm.arm') ]
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cur_sys.atags_addr = 0x8000000
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cur_sys.load_addr_mask = 0xfffffff
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cur_sys.load_offset = 0x80000000
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