Cleaned up include files and got rid of many using directives in header files.
--HG-- extra : convert_revision : 6b11e039cbc061dab75195fa1aebe6ca2cdc6f91
This commit is contained in:
parent
741bc40cc3
commit
74546aac01
67 changed files with 159 additions and 204 deletions
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@ -30,6 +30,8 @@
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#include "arch/alpha/linux/linux.hh"
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#include <fcntl.h>
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// open(2) flags translation table
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OpenFlagTransTable AlphaLinux::openFlagTable[] = {
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#ifdef _MSC_VER
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@ -36,7 +36,6 @@
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output header {{
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#include <iostream>
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using namespace std;
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/**
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* Base class for instructions whose disassembly is not purely a
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@ -34,7 +34,6 @@
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//
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output header {{
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#include <iostream>
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using namespace std;
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/**
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* Base class for integer operations.
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*/
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@ -133,7 +133,7 @@ output decoder {{
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std::string inst2string(MachInst machInst)
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{
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string str = "";
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std::string str = "";
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uint32_t mask = 0x80000000;
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for(int i=0; i < 32; i++) {
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@ -30,6 +30,8 @@
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#include "arch/mips/linux/linux.hh"
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#include <fcntl.h>
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// open(2) flags translation table
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OpenFlagTransTable MipsLinux::openFlagTable[] = {
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#ifdef _MSC_VER
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@ -139,7 +139,6 @@ namespace MipsISA
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Fault setReg(int floatReg, const FloatRegVal &val, int width)
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{
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using namespace std;
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switch(width)
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{
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case SingleWidth:
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@ -168,7 +167,6 @@ namespace MipsISA
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Fault setRegBits(int floatReg, const FloatRegBits &val, int width)
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{
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using namespace std;
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switch(width)
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{
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@ -31,7 +31,6 @@
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#ifndef __ARCH_MIPS_REGFILE_MISC_REGFILE_HH__
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#define __ARCH_MIPS_REGFILE_MISC_REGFILE_HH__
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#include "arch/mips/isa_traits.hh"
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#include "arch/mips/types.hh"
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#include "sim/faults.hh"
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@ -32,7 +32,6 @@
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#define __ARCH_MIPS_REGFILE_REGFILE_HH__
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#include "arch/mips/types.hh"
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#include "arch/mips/isa_traits.hh"
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#include "arch/mips/regfile/int_regfile.hh"
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#include "arch/mips/regfile/float_regfile.hh"
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#include "arch/mips/regfile/misc_regfile.hh"
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@ -28,15 +28,12 @@
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* Authors: Korey Sewell
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*/
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#include "arch/mips/isa_traits.hh"
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#include "arch/mips/regfile.hh"
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#include "arch/mips/utility.hh"
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#include "config/full_system.hh"
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#include "cpu/static_inst.hh"
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#include "sim/serialize.hh"
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#include "base/misc.hh"
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#include "base/bitfield.hh"
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using namespace MipsISA;
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using namespace std;
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uint64_t
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MipsISA::fpConvert(ConvertType cvt_type, double fp_val)
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@ -33,12 +33,14 @@
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#define __ARCH_MIPS_UTILITY_HH__
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#include "arch/mips/types.hh"
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#include "arch/mips/isa_traits.hh"
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#include "base/misc.hh"
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#include "config/full_system.hh"
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//XXX This is needed for size_t. We should use something other than size_t
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#include "kern/linux/linux.hh"
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//#include "kern/linux/linux.hh"
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#include "sim/host.hh"
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class ThreadContext;
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namespace MipsISA {
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//Floating Point Utility Functions
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@ -29,6 +29,7 @@
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*/
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#include "arch/sparc/linux/linux.hh"
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#include <fcntl.h>
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// open(2) flags translation table
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OpenFlagTransTable SparcLinux::openFlagTable[] = {
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@ -32,6 +32,7 @@
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#define __SPARC_LINUX_PROCESS_HH__
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#include "arch/sparc/linux/linux.hh"
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#include "arch/sparc/syscallreturn.hh"
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#include "arch/sparc/process.hh"
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#include "sim/process.hh"
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@ -30,6 +30,8 @@
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#include "arch/sparc/solaris/solaris.hh"
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#include <fcntl.h>
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// open(2) flags translation table
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OpenFlagTransTable SparcSolaris::openFlagTable[] = {
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#ifdef _MSC_VER
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@ -33,6 +33,8 @@
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#include <inttypes.h>
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#include "arch/sparc/regfile.hh"
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class SyscallReturn
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{
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public:
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@ -36,15 +36,12 @@
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#include "base/cprintf.hh"
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#include "base/trace.hh"
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#include "arch/faults.hh"
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#include "sim/faults.hh"
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#include "cpu/exetrace.hh"
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#include "mem/request.hh"
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#include "cpu/base_dyn_inst.hh"
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using namespace std;
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using namespace TheISA;
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#define NOHASH
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#ifndef NOHASH
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@ -65,7 +62,7 @@ my_hash_t thishash;
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#endif
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template <class Impl>
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BaseDynInst<Impl>::BaseDynInst(ExtMachInst machInst, Addr inst_PC,
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BaseDynInst<Impl>::BaseDynInst(TheISA::ExtMachInst machInst, Addr inst_PC,
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Addr pred_PC, InstSeqNum seq_num,
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ImplCPU *cpu)
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: staticInst(machInst), traceData(NULL), cpu(cpu)
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seqNum = seq_num;
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PC = inst_PC;
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nextPC = PC + sizeof(MachInst);
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nextNPC = nextPC + sizeof(MachInst);
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nextPC = PC + sizeof(TheISA::MachInst);
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nextNPC = nextPC + sizeof(TheISA::MachInst);
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predPC = pred_PC;
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initVars();
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BaseDynInst<Impl>::dump()
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{
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cprintf("T%d : %#08d `", threadNumber, PC);
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cout << staticInst->disassemble(PC);
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std::cout << staticInst->disassemble(PC);
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cprintf("'\n");
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}
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@ -31,9 +31,8 @@
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#ifndef __CPU_O3_2BIT_LOCAL_PRED_HH__
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#define __CPU_O3_2BIT_LOCAL_PRED_HH__
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// For Addr type.
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#include "arch/isa_traits.hh"
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#include "cpu/o3/sat_counter.hh"
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#include "sim/host.hh"
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#include <vector>
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@ -31,7 +31,8 @@
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#ifndef __CPU_O3_ALPHA_CPU_HH__
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#define __CPU_O3_ALPHA_CPU_HH__
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#include "arch/isa_traits.hh"
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#include "arch/regfile.hh"
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#include "arch/types.hh"
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#include "cpu/thread_context.hh"
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#include "cpu/o3/cpu.hh"
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#include "sim/byteswap.hh"
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@ -53,8 +53,6 @@
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#include "sim/system.hh"
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#endif
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using namespace TheISA;
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template <class Impl>
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AlphaO3CPU<Impl>::AlphaO3CPU(Params *params)
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#if FULL_SYSTEM
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#ifndef __CPU_O3_BPRED_UNIT_HH__
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#define __CPU_O3_BPRED_UNIT_HH__
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// For Addr type.
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#include "arch/isa_traits.hh"
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#include "base/statistics.hh"
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#include "cpu/inst_seq.hh"
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#include "cpu/o3/ras.hh"
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#include "cpu/o3/tournament_pred.hh"
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#include "sim/host.hh"
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#include <list>
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/**
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* Authors: Kevin Lim
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*/
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#include <list>
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#include <vector>
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#include "arch/types.hh"
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#include "base/trace.hh"
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#include "base/traceflags.hh"
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#include "cpu/o3/bpred_unit.hh"
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using namespace std;
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template<class Impl>
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BPredUnit<Impl>::BPredUnit(Params *params)
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: BTB(params->BTBEntries,
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#include "base/trace.hh"
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#include "cpu/o3/btb.hh"
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using namespace TheISA;
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DefaultBTB::DefaultBTB(unsigned _numEntries,
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unsigned _tagBits,
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unsigned _instShiftAmt)
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#ifndef __CPU_O3_BTB_HH__
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#define __CPU_O3_BTB_HH__
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// For Addr type.
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#include "arch/isa_traits.hh"
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#include "base/misc.hh"
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#include "sim/host.hh"
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class DefaultBTB
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{
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#include <vector>
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#include "arch/faults.hh"
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#include "arch/isa_traits.hh"
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#include "sim/faults.hh"
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#include "cpu/inst_seq.hh"
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#include "sim/host.hh"
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#ifndef __CPU_O3_COMMIT_HH__
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#define __CPU_O3_COMMIT_HH__
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#include "arch/faults.hh"
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#include "base/statistics.hh"
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#include "base/timebuf.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/checker/cpu.hh"
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#endif
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using namespace std;
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template <class Impl>
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DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
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unsigned _tid)
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@ -87,7 +85,7 @@ DefaultCommit<Impl>::DefaultCommit(Params *params)
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{
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_status = Active;
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_nextStatus = Inactive;
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string policy = params->smtCommitPolicy;
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std::string policy = params->smtCommitPolicy;
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//Convert string to lowercase
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std::transform(policy.begin(), policy.end(), policy.begin(),
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@ -236,7 +234,7 @@ DefaultCommit<Impl>::setCPU(O3CPU *cpu_ptr)
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template <class Impl>
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void
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DefaultCommit<Impl>::setThreads(vector<Thread *> &threads)
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DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
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{
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thread = threads;
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}
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@ -297,7 +295,7 @@ DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
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template<class Impl>
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void
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DefaultCommit<Impl>::setActiveThreads(list<unsigned> *at_ptr)
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DefaultCommit<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
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{
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DPRINTF(Commit, "Commit: Setting active threads list pointer.\n");
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activeThreads = at_ptr;
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@ -391,7 +389,7 @@ void
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DefaultCommit<Impl>::updateStatus()
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{
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// reset ROB changed variable
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list<unsigned>::iterator threads = (*activeThreads).begin();
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std::list<unsigned>::iterator threads = (*activeThreads).begin();
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while (threads != (*activeThreads).end()) {
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unsigned tid = *threads++;
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changedROBNumEntries[tid] = false;
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@ -420,7 +418,7 @@ DefaultCommit<Impl>::setNextStatus()
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{
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int squashes = 0;
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list<unsigned>::iterator threads = (*activeThreads).begin();
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std::list<unsigned>::iterator threads = (*activeThreads).begin();
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while (threads != (*activeThreads).end()) {
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unsigned tid = *threads++;
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@ -443,7 +441,7 @@ template <class Impl>
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bool
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DefaultCommit<Impl>::changedROBEntries()
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{
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list<unsigned>::iterator threads = (*activeThreads).begin();
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std::list<unsigned>::iterator threads = (*activeThreads).begin();
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while (threads != (*activeThreads).end()) {
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unsigned tid = *threads++;
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@ -570,7 +568,7 @@ DefaultCommit<Impl>::tick()
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if ((*activeThreads).size() <= 0)
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return;
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list<unsigned>::iterator threads = (*activeThreads).begin();
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std::list<unsigned>::iterator threads = (*activeThreads).begin();
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// Check if any of the threads are done squashing. Change the
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// status if they are done.
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@ -688,7 +686,7 @@ DefaultCommit<Impl>::commit()
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// Check for any possible squashes, handle them first
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////////////////////////////////////
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list<unsigned>::iterator threads = (*activeThreads).begin();
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std::list<unsigned>::iterator threads = (*activeThreads).begin();
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while (threads != (*activeThreads).end()) {
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unsigned tid = *threads++;
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@ -1119,10 +1117,10 @@ DefaultCommit<Impl>::getInsts()
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#if THE_ISA == ALPHA_ISA
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// Read any renamed instructions and place them into the ROB.
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int insts_to_process = min((int)renameWidth, fromRename->size);
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int insts_to_process = std::min((int)renameWidth, fromRename->size);
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#else
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// Read any renamed instructions and place them into the ROB.
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int insts_to_process = min((int)renameWidth,
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int insts_to_process = std::min((int)renameWidth,
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(int)(fromRename->size + skidBuffer.size()));
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int rename_idx = 0;
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@ -1244,7 +1242,7 @@ template <class Impl>
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bool
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DefaultCommit<Impl>::robDoneSquashing()
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{
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list<unsigned>::iterator threads = (*activeThreads).begin();
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std::list<unsigned>::iterator threads = (*activeThreads).begin();
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while (threads != (*activeThreads).end()) {
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unsigned tid = *threads++;
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@ -1341,8 +1339,8 @@ template<class Impl>
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int
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DefaultCommit<Impl>::roundRobin()
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{
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list<unsigned>::iterator pri_iter = priority_list.begin();
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list<unsigned>::iterator end = priority_list.end();
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std::list<unsigned>::iterator pri_iter = priority_list.begin();
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std::list<unsigned>::iterator end = priority_list.end();
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while (pri_iter != end) {
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unsigned tid = *pri_iter;
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@ -1372,7 +1370,7 @@ DefaultCommit<Impl>::oldestReady()
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unsigned oldest = 0;
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bool first = true;
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list<unsigned>::iterator threads = (*activeThreads).begin();
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std::list<unsigned>::iterator threads = (*activeThreads).begin();
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while (threads != (*activeThreads).end()) {
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unsigned tid = *threads++;
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|
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|
@ -38,7 +38,7 @@
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#include <set>
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#include <vector>
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#include "arch/isa_traits.hh"
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#include "arch/types.hh"
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#include "base/statistics.hh"
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#include "base/timebuf.hh"
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#include "config/full_system.hh"
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@ -30,8 +30,6 @@
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#include "cpu/o3/decode.hh"
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using namespace std;
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template<class Impl>
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DefaultDecode<Impl>::DefaultDecode(Params *params)
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: renameToDecodeDelay(params->renameToDecodeDelay),
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@ -160,7 +158,7 @@ DefaultDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
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template<class Impl>
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void
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DefaultDecode<Impl>::setActiveThreads(list<unsigned> *at_ptr)
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DefaultDecode<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
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{
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DPRINTF(Decode, "Setting active threads list pointer.\n");
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activeThreads = at_ptr;
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@ -426,7 +424,7 @@ template<class Impl>
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bool
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DefaultDecode<Impl>::skidsEmpty()
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{
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list<unsigned>::iterator threads = (*activeThreads).begin();
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std::list<unsigned>::iterator threads = (*activeThreads).begin();
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|
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while (threads != (*activeThreads).end()) {
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if (!skidBuffer[*threads++].empty())
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@ -442,7 +440,7 @@ DefaultDecode<Impl>::updateStatus()
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{
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bool any_unblocking = false;
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list<unsigned>::iterator threads = (*activeThreads).begin();
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std::list<unsigned>::iterator threads = (*activeThreads).begin();
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threads = (*activeThreads).begin();
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|
@ -599,7 +597,7 @@ DefaultDecode<Impl>::tick()
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toRenameIndex = 0;
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list<unsigned>::iterator threads = (*activeThreads).begin();
|
||||
std::list<unsigned>::iterator threads = (*activeThreads).begin();
|
||||
|
||||
sortInsts();
|
||||
|
||||
|
|
|
@ -51,9 +51,6 @@
|
|||
|
||||
#include <algorithm>
|
||||
|
||||
using namespace std;
|
||||
using namespace TheISA;
|
||||
|
||||
template<class Impl>
|
||||
Tick
|
||||
DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt)
|
||||
|
@ -118,7 +115,7 @@ DefaultFetch<Impl>::DefaultFetch(Params *params)
|
|||
// Set fetch stage's status to inactive.
|
||||
_status = Inactive;
|
||||
|
||||
string policy = params->smtFetchPolicy;
|
||||
std::string policy = params->smtFetchPolicy;
|
||||
|
||||
// Convert string to lowercase
|
||||
std::transform(policy.begin(), policy.end(), policy.begin(),
|
||||
|
@ -177,7 +174,7 @@ DefaultFetch<Impl>::DefaultFetch(Params *params)
|
|||
}
|
||||
|
||||
// Get the size of an instruction.
|
||||
instSize = sizeof(MachInst);
|
||||
instSize = sizeof(TheISA::MachInst);
|
||||
}
|
||||
|
||||
template <class Impl>
|
||||
|
@ -317,7 +314,7 @@ DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
|
|||
|
||||
template<class Impl>
|
||||
void
|
||||
DefaultFetch<Impl>::setActiveThreads(list<unsigned> *at_ptr)
|
||||
DefaultFetch<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
|
||||
{
|
||||
DPRINTF(Fetch, "Setting active threads list pointer.\n");
|
||||
activeThreads = at_ptr;
|
||||
|
@ -739,7 +736,7 @@ typename DefaultFetch<Impl>::FetchStatus
|
|||
DefaultFetch<Impl>::updateFetchStatus()
|
||||
{
|
||||
//Check Running
|
||||
list<unsigned>::iterator threads = (*activeThreads).begin();
|
||||
std::list<unsigned>::iterator threads = (*activeThreads).begin();
|
||||
|
||||
while (threads != (*activeThreads).end()) {
|
||||
|
||||
|
@ -802,7 +799,7 @@ template <class Impl>
|
|||
void
|
||||
DefaultFetch<Impl>::tick()
|
||||
{
|
||||
list<unsigned>::iterator threads = (*activeThreads).begin();
|
||||
std::list<unsigned>::iterator threads = (*activeThreads).begin();
|
||||
bool status_change = false;
|
||||
|
||||
wroteToTimeBuffer = false;
|
||||
|
@ -1350,8 +1347,8 @@ template<class Impl>
|
|||
int
|
||||
DefaultFetch<Impl>::roundRobin()
|
||||
{
|
||||
list<unsigned>::iterator pri_iter = priorityList.begin();
|
||||
list<unsigned>::iterator end = priorityList.end();
|
||||
std::list<unsigned>::iterator pri_iter = priorityList.begin();
|
||||
std::list<unsigned>::iterator end = priorityList.end();
|
||||
|
||||
int high_pri;
|
||||
|
||||
|
@ -1380,9 +1377,9 @@ template<class Impl>
|
|||
int
|
||||
DefaultFetch<Impl>::iqCount()
|
||||
{
|
||||
priority_queue<unsigned> PQ;
|
||||
std::priority_queue<unsigned> PQ;
|
||||
|
||||
list<unsigned>::iterator threads = (*activeThreads).begin();
|
||||
std::list<unsigned>::iterator threads = (*activeThreads).begin();
|
||||
|
||||
while (threads != (*activeThreads).end()) {
|
||||
unsigned tid = *threads++;
|
||||
|
@ -1410,10 +1407,10 @@ template<class Impl>
|
|||
int
|
||||
DefaultFetch<Impl>::lsqCount()
|
||||
{
|
||||
priority_queue<unsigned> PQ;
|
||||
std::priority_queue<unsigned> PQ;
|
||||
|
||||
|
||||
list<unsigned>::iterator threads = (*activeThreads).begin();
|
||||
std::list<unsigned>::iterator threads = (*activeThreads).begin();
|
||||
|
||||
while (threads != (*activeThreads).end()) {
|
||||
unsigned tid = *threads++;
|
||||
|
@ -1441,7 +1438,7 @@ template<class Impl>
|
|||
int
|
||||
DefaultFetch<Impl>::branchCount()
|
||||
{
|
||||
list<unsigned>::iterator threads = (*activeThreads).begin();
|
||||
std::list<unsigned>::iterator threads = (*activeThreads).begin();
|
||||
panic("Branch Count Fetch policy unimplemented\n");
|
||||
return *threads;
|
||||
}
|
||||
|
|
|
@ -38,8 +38,6 @@
|
|||
#include "cpu/o3/fu_pool.hh"
|
||||
#include "cpu/o3/iew.hh"
|
||||
|
||||
using namespace std;
|
||||
|
||||
template<class Impl>
|
||||
DefaultIEW<Impl>::DefaultIEW(Params *params)
|
||||
: issueToExecQueue(params->backComSize, params->forwardComSize),
|
||||
|
@ -336,7 +334,7 @@ DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
|
|||
|
||||
template<class Impl>
|
||||
void
|
||||
DefaultIEW<Impl>::setActiveThreads(list<unsigned> *at_ptr)
|
||||
DefaultIEW<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
|
||||
{
|
||||
DPRINTF(IEW, "Setting active threads list pointer.\n");
|
||||
activeThreads = at_ptr;
|
||||
|
@ -663,7 +661,7 @@ DefaultIEW<Impl>::skidCount()
|
|||
{
|
||||
int max=0;
|
||||
|
||||
list<unsigned>::iterator threads = (*activeThreads).begin();
|
||||
std::list<unsigned>::iterator threads = (*activeThreads).begin();
|
||||
|
||||
while (threads != (*activeThreads).end()) {
|
||||
unsigned thread_count = skidBuffer[*threads++].size();
|
||||
|
@ -678,7 +676,7 @@ template<class Impl>
|
|||
bool
|
||||
DefaultIEW<Impl>::skidsEmpty()
|
||||
{
|
||||
list<unsigned>::iterator threads = (*activeThreads).begin();
|
||||
std::list<unsigned>::iterator threads = (*activeThreads).begin();
|
||||
|
||||
while (threads != (*activeThreads).end()) {
|
||||
if (!skidBuffer[*threads++].empty())
|
||||
|
@ -694,7 +692,7 @@ DefaultIEW<Impl>::updateStatus()
|
|||
{
|
||||
bool any_unblocking = false;
|
||||
|
||||
list<unsigned>::iterator threads = (*activeThreads).begin();
|
||||
std::list<unsigned>::iterator threads = (*activeThreads).begin();
|
||||
|
||||
threads = (*activeThreads).begin();
|
||||
|
||||
|
@ -1195,13 +1193,13 @@ DefaultIEW<Impl>::printAvailableInsts()
|
|||
{
|
||||
int inst = 0;
|
||||
|
||||
cout << "Available Instructions: ";
|
||||
std::cout << "Available Instructions: ";
|
||||
|
||||
while (fromIssue->insts[inst]) {
|
||||
|
||||
if (inst%3==0) cout << "\n\t";
|
||||
if (inst%3==0) std::cout << "\n\t";
|
||||
|
||||
cout << "PC: " << fromIssue->insts[inst]->readPC()
|
||||
std::cout << "PC: " << fromIssue->insts[inst]->readPC()
|
||||
<< " TN: " << fromIssue->insts[inst]->threadNumber
|
||||
<< " SN: " << fromIssue->insts[inst]->seqNum << " | ";
|
||||
|
||||
|
@ -1209,7 +1207,7 @@ DefaultIEW<Impl>::printAvailableInsts()
|
|||
|
||||
}
|
||||
|
||||
cout << "\n";
|
||||
std::cout << "\n";
|
||||
}
|
||||
|
||||
template <class Impl>
|
||||
|
@ -1219,7 +1217,7 @@ DefaultIEW<Impl>::executeInsts()
|
|||
wbNumInst = 0;
|
||||
wbCycle = 0;
|
||||
|
||||
list<unsigned>::iterator threads = (*activeThreads).begin();
|
||||
std::list<unsigned>::iterator threads = (*activeThreads).begin();
|
||||
|
||||
while (threads != (*activeThreads).end()) {
|
||||
unsigned tid = *threads++;
|
||||
|
@ -1443,7 +1441,7 @@ DefaultIEW<Impl>::tick()
|
|||
// Free function units marked as being freed this cycle.
|
||||
fuPool->processFreeUnits();
|
||||
|
||||
list<unsigned>::iterator threads = (*activeThreads).begin();
|
||||
std::list<unsigned>::iterator threads = (*activeThreads).begin();
|
||||
|
||||
// Check stall and squash signals, dispatch any instructions.
|
||||
while (threads != (*activeThreads).end()) {
|
||||
|
|
|
@ -37,8 +37,6 @@
|
|||
#include "cpu/o3/fu_pool.hh"
|
||||
#include "cpu/o3/inst_queue.hh"
|
||||
|
||||
using namespace std;
|
||||
|
||||
template <class Impl>
|
||||
InstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst,
|
||||
int fu_idx,
|
||||
|
@ -100,7 +98,7 @@ InstructionQueue<Impl>::InstructionQueue(Params *params)
|
|||
|
||||
resetState();
|
||||
|
||||
string policy = params->smtIQPolicy;
|
||||
std::string policy = params->smtIQPolicy;
|
||||
|
||||
//Convert string to lowercase
|
||||
std::transform(policy.begin(), policy.end(), policy.begin(),
|
||||
|
@ -279,7 +277,7 @@ InstructionQueue<Impl>::regStats()
|
|||
;
|
||||
|
||||
for (int i=0; i<Num_OpClasses; ++i) {
|
||||
stringstream subname;
|
||||
std::stringstream subname;
|
||||
subname << opClassStrings[i] << "_delay";
|
||||
issueDelayDist.subname(i, subname.str());
|
||||
}
|
||||
|
@ -359,7 +357,7 @@ InstructionQueue<Impl>::resetState()
|
|||
|
||||
template <class Impl>
|
||||
void
|
||||
InstructionQueue<Impl>::setActiveThreads(list<unsigned> *at_ptr)
|
||||
InstructionQueue<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
|
||||
{
|
||||
DPRINTF(IQ, "Setting active threads list pointer.\n");
|
||||
activeThreads = at_ptr;
|
||||
|
@ -421,8 +419,8 @@ InstructionQueue<Impl>::resetEntries()
|
|||
if (iqPolicy != Dynamic || numThreads > 1) {
|
||||
int active_threads = (*activeThreads).size();
|
||||
|
||||
list<unsigned>::iterator threads = (*activeThreads).begin();
|
||||
list<unsigned>::iterator list_end = (*activeThreads).end();
|
||||
std::list<unsigned>::iterator threads = (*activeThreads).begin();
|
||||
std::list<unsigned>::iterator list_end = (*activeThreads).end();
|
||||
|
||||
while (threads != list_end) {
|
||||
if (iqPolicy == Partitioned) {
|
||||
|
|
|
@ -29,12 +29,11 @@
|
|||
*/
|
||||
|
||||
#include <algorithm>
|
||||
#include <list>
|
||||
#include <string>
|
||||
|
||||
#include "cpu/o3/lsq.hh"
|
||||
|
||||
using namespace std;
|
||||
|
||||
template <class Impl>
|
||||
Tick
|
||||
LSQ<Impl>::DcachePort::recvAtomic(PacketPtr pkt)
|
||||
|
@ -89,7 +88,7 @@ LSQ<Impl>::LSQ(Params *params)
|
|||
//**********************************************/
|
||||
//************ Handle SMT Parameters ***********/
|
||||
//**********************************************/
|
||||
string policy = params->smtLSQPolicy;
|
||||
std::string policy = params->smtLSQPolicy;
|
||||
|
||||
//Convert string to lowercase
|
||||
std::transform(policy.begin(), policy.end(), policy.begin(),
|
||||
|
@ -163,7 +162,7 @@ LSQ<Impl>::regStats()
|
|||
|
||||
template<class Impl>
|
||||
void
|
||||
LSQ<Impl>::setActiveThreads(list<unsigned> *at_ptr)
|
||||
LSQ<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
|
||||
{
|
||||
activeThreads = at_ptr;
|
||||
assert(activeThreads != 0);
|
||||
|
@ -229,8 +228,8 @@ LSQ<Impl>::resetEntries()
|
|||
if (lsqPolicy != Dynamic || numThreads > 1) {
|
||||
int active_threads = (*activeThreads).size();
|
||||
|
||||
list<unsigned>::iterator threads = (*activeThreads).begin();
|
||||
list<unsigned>::iterator list_end = (*activeThreads).end();
|
||||
std::list<unsigned>::iterator threads = (*activeThreads).begin();
|
||||
std::list<unsigned>::iterator list_end = (*activeThreads).end();
|
||||
|
||||
int maxEntries;
|
||||
|
||||
|
@ -268,7 +267,7 @@ template<class Impl>
|
|||
void
|
||||
LSQ<Impl>::tick()
|
||||
{
|
||||
list<unsigned>::iterator active_threads = (*activeThreads).begin();
|
||||
std::list<unsigned>::iterator active_threads = (*activeThreads).begin();
|
||||
|
||||
while (active_threads != (*activeThreads).end()) {
|
||||
unsigned tid = *active_threads++;
|
||||
|
@ -317,7 +316,7 @@ template<class Impl>
|
|||
void
|
||||
LSQ<Impl>::writebackStores()
|
||||
{
|
||||
list<unsigned>::iterator active_threads = (*activeThreads).begin();
|
||||
std::list<unsigned>::iterator active_threads = (*activeThreads).begin();
|
||||
|
||||
while (active_threads != (*activeThreads).end()) {
|
||||
unsigned tid = *active_threads++;
|
||||
|
@ -336,7 +335,7 @@ bool
|
|||
LSQ<Impl>::violation()
|
||||
{
|
||||
/* Answers: Does Anybody Have a Violation?*/
|
||||
list<unsigned>::iterator active_threads = (*activeThreads).begin();
|
||||
std::list<unsigned>::iterator active_threads = (*activeThreads).begin();
|
||||
|
||||
while (active_threads != (*activeThreads).end()) {
|
||||
unsigned tid = *active_threads++;
|
||||
|
@ -353,7 +352,7 @@ LSQ<Impl>::getCount()
|
|||
{
|
||||
unsigned total = 0;
|
||||
|
||||
list<unsigned>::iterator active_threads = (*activeThreads).begin();
|
||||
std::list<unsigned>::iterator active_threads = (*activeThreads).begin();
|
||||
|
||||
while (active_threads != (*activeThreads).end()) {
|
||||
unsigned tid = *active_threads++;
|
||||
|
@ -369,7 +368,7 @@ LSQ<Impl>::numLoads()
|
|||
{
|
||||
unsigned total = 0;
|
||||
|
||||
list<unsigned>::iterator active_threads = (*activeThreads).begin();
|
||||
std::list<unsigned>::iterator active_threads = (*activeThreads).begin();
|
||||
|
||||
while (active_threads != (*activeThreads).end()) {
|
||||
unsigned tid = *active_threads++;
|
||||
|
@ -385,7 +384,7 @@ LSQ<Impl>::numStores()
|
|||
{
|
||||
unsigned total = 0;
|
||||
|
||||
list<unsigned>::iterator active_threads = (*activeThreads).begin();
|
||||
std::list<unsigned>::iterator active_threads = (*activeThreads).begin();
|
||||
|
||||
while (active_threads != (*activeThreads).end()) {
|
||||
unsigned tid = *active_threads++;
|
||||
|
@ -401,7 +400,7 @@ LSQ<Impl>::numLoadsReady()
|
|||
{
|
||||
unsigned total = 0;
|
||||
|
||||
list<unsigned>::iterator active_threads = (*activeThreads).begin();
|
||||
std::list<unsigned>::iterator active_threads = (*activeThreads).begin();
|
||||
|
||||
while (active_threads != (*activeThreads).end()) {
|
||||
unsigned tid = *active_threads++;
|
||||
|
@ -417,7 +416,7 @@ LSQ<Impl>::numFreeEntries()
|
|||
{
|
||||
unsigned total = 0;
|
||||
|
||||
list<unsigned>::iterator active_threads = (*activeThreads).begin();
|
||||
std::list<unsigned>::iterator active_threads = (*activeThreads).begin();
|
||||
|
||||
while (active_threads != (*activeThreads).end()) {
|
||||
unsigned tid = *active_threads++;
|
||||
|
@ -441,7 +440,7 @@ template<class Impl>
|
|||
bool
|
||||
LSQ<Impl>::isFull()
|
||||
{
|
||||
list<unsigned>::iterator active_threads = (*activeThreads).begin();
|
||||
std::list<unsigned>::iterator active_threads = (*activeThreads).begin();
|
||||
|
||||
while (active_threads != (*activeThreads).end()) {
|
||||
unsigned tid = *active_threads++;
|
||||
|
@ -468,7 +467,7 @@ template<class Impl>
|
|||
bool
|
||||
LSQ<Impl>::lqFull()
|
||||
{
|
||||
list<unsigned>::iterator active_threads = (*activeThreads).begin();
|
||||
std::list<unsigned>::iterator active_threads = (*activeThreads).begin();
|
||||
|
||||
while (active_threads != (*activeThreads).end()) {
|
||||
unsigned tid = *active_threads++;
|
||||
|
@ -495,7 +494,7 @@ template<class Impl>
|
|||
bool
|
||||
LSQ<Impl>::sqFull()
|
||||
{
|
||||
list<unsigned>::iterator active_threads = (*activeThreads).begin();
|
||||
std::list<unsigned>::iterator active_threads = (*activeThreads).begin();
|
||||
|
||||
while (active_threads != (*activeThreads).end()) {
|
||||
unsigned tid = *active_threads++;
|
||||
|
@ -522,7 +521,7 @@ template<class Impl>
|
|||
bool
|
||||
LSQ<Impl>::isStalled()
|
||||
{
|
||||
list<unsigned>::iterator active_threads = (*activeThreads).begin();
|
||||
std::list<unsigned>::iterator active_threads = (*activeThreads).begin();
|
||||
|
||||
while (active_threads != (*activeThreads).end()) {
|
||||
unsigned tid = *active_threads++;
|
||||
|
@ -547,7 +546,7 @@ template<class Impl>
|
|||
bool
|
||||
LSQ<Impl>::hasStoresToWB()
|
||||
{
|
||||
list<unsigned>::iterator active_threads = (*activeThreads).begin();
|
||||
std::list<unsigned>::iterator active_threads = (*activeThreads).begin();
|
||||
|
||||
if ((*activeThreads).empty())
|
||||
return false;
|
||||
|
@ -565,7 +564,7 @@ template<class Impl>
|
|||
bool
|
||||
LSQ<Impl>::willWB()
|
||||
{
|
||||
list<unsigned>::iterator active_threads = (*activeThreads).begin();
|
||||
std::list<unsigned>::iterator active_threads = (*activeThreads).begin();
|
||||
|
||||
while (active_threads != (*activeThreads).end()) {
|
||||
unsigned tid = *active_threads++;
|
||||
|
@ -580,7 +579,7 @@ template<class Impl>
|
|||
void
|
||||
LSQ<Impl>::dumpInsts()
|
||||
{
|
||||
list<unsigned>::iterator active_threads = (*activeThreads).begin();
|
||||
std::list<unsigned>::iterator active_threads = (*activeThreads).begin();
|
||||
|
||||
while (active_threads != (*activeThreads).end()) {
|
||||
unsigned tid = *active_threads++;
|
||||
|
|
|
@ -32,10 +32,12 @@
|
|||
#ifndef __CPU_O3_MIPS_CPU_HH__
|
||||
#define __CPU_O3_MIPS_CPU_HH__
|
||||
|
||||
#include "arch/isa_traits.hh"
|
||||
#include "arch/mips/regfile.hh"
|
||||
#include "arch/mips/syscallreturn.hh"
|
||||
#include "cpu/thread_context.hh"
|
||||
#include "cpu/o3/cpu.hh"
|
||||
#include "sim/byteswap.hh"
|
||||
#include "sim/faults.hh"
|
||||
|
||||
class EndQuiesceEvent;
|
||||
namespace Kernel {
|
||||
|
@ -55,14 +57,6 @@ class TranslatingPort;
|
|||
template <class Impl>
|
||||
class MipsO3CPU : public FullO3CPU<Impl>
|
||||
{
|
||||
protected:
|
||||
typedef TheISA::IntReg IntReg;
|
||||
typedef TheISA::FloatReg FloatReg;
|
||||
typedef TheISA::FloatRegBits FloatRegBits;
|
||||
typedef TheISA::MiscReg MiscReg;
|
||||
typedef TheISA::RegFile RegFile;
|
||||
typedef TheISA::MiscRegFile MiscRegFile;
|
||||
|
||||
public:
|
||||
typedef O3ThreadState<Impl> ImplState;
|
||||
typedef O3ThreadState<Impl> Thread;
|
||||
|
@ -93,20 +87,22 @@ class MipsO3CPU : public FullO3CPU<Impl>
|
|||
}
|
||||
|
||||
/** Reads a miscellaneous register. */
|
||||
MiscReg readMiscReg(int misc_reg, unsigned tid);
|
||||
TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid);
|
||||
|
||||
/** Reads a misc. register, including any side effects the read
|
||||
* might have as defined by the architecture.
|
||||
*/
|
||||
MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault, unsigned tid);
|
||||
TheISA::MiscReg readMiscRegWithEffect(int misc_reg,
|
||||
Fault &fault, unsigned tid);
|
||||
|
||||
/** Sets a miscellaneous register. */
|
||||
Fault setMiscReg(int misc_reg, const MiscReg &val, unsigned tid);
|
||||
Fault setMiscReg(int misc_reg, const TheISA::MiscReg &val, unsigned tid);
|
||||
|
||||
/** Sets a misc. register, including any side effects the write
|
||||
* might have as defined by the architecture.
|
||||
*/
|
||||
Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val, unsigned tid);
|
||||
Fault setMiscRegWithEffect(int misc_reg,
|
||||
const TheISA::MiscReg &val, unsigned tid);
|
||||
|
||||
/** Initiates a squash of all in-flight instructions for a given
|
||||
* thread. The source of the squash is an external update of
|
||||
|
@ -122,10 +118,10 @@ class MipsO3CPU : public FullO3CPU<Impl>
|
|||
*/
|
||||
void syscall(int64_t callnum, int tid);
|
||||
/** Gets a syscall argument. */
|
||||
IntReg getSyscallArg(int i, int tid);
|
||||
TheISA::IntReg getSyscallArg(int i, int tid);
|
||||
|
||||
/** Used to shift args for indirect syscall. */
|
||||
void setSyscallArg(int i, IntReg val, int tid);
|
||||
void setSyscallArg(int i, TheISA::IntReg val, int tid);
|
||||
|
||||
/** Sets the return value of a syscall. */
|
||||
void setSyscallReturn(SyscallReturn return_value, int tid);
|
||||
|
|
|
@ -45,8 +45,6 @@
|
|||
#include "cpu/o3/comm.hh"
|
||||
#include "cpu/o3/thread_state.hh"
|
||||
|
||||
using namespace TheISA;
|
||||
|
||||
template <class Impl>
|
||||
MipsO3CPU<Impl>::MipsO3CPU(Params *params)
|
||||
: FullO3CPU<Impl>(params)
|
||||
|
@ -240,12 +238,13 @@ MipsO3CPU<Impl>::setSyscallReturn(SyscallReturn return_value, int tid)
|
|||
// check for error condition.
|
||||
if (return_value.successful()) {
|
||||
// no error
|
||||
this->setArchIntReg(SyscallSuccessReg, 0, tid);
|
||||
this->setArchIntReg(ReturnValueReg, return_value.value(), tid);
|
||||
this->setArchIntReg(TheISA::SyscallSuccessReg, 0, tid);
|
||||
this->setArchIntReg(TheISA::ReturnValueReg, return_value.value(), tid);
|
||||
} else {
|
||||
// got an error, return details
|
||||
this->setArchIntReg(SyscallSuccessReg, (IntReg) -1, tid);
|
||||
this->setArchIntReg(ReturnValueReg, -return_value.value(), tid);
|
||||
this->setArchIntReg(TheISA::SyscallSuccessReg,
|
||||
(TheISA::IntReg) -1, tid);
|
||||
this->setArchIntReg(TheISA::ReturnValueReg, -return_value.value(), tid);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -31,8 +31,7 @@
|
|||
#ifndef __CPU_O3_RAS_HH__
|
||||
#define __CPU_O3_RAS_HH__
|
||||
|
||||
// For Addr type.
|
||||
#include "arch/isa_traits.hh"
|
||||
#include "sim/host.hh"
|
||||
#include <vector>
|
||||
|
||||
/** Return address stack class, implements a simple RAS. */
|
||||
|
|
|
@ -33,11 +33,11 @@
|
|||
#define __CPU_O3_REGFILE_HH__
|
||||
|
||||
#include "arch/isa_traits.hh"
|
||||
#include "arch/faults.hh"
|
||||
#include "arch/types.hh"
|
||||
#include "base/trace.hh"
|
||||
#include "config/full_system.hh"
|
||||
#include "cpu/o3/comm.hh"
|
||||
#include "sim/faults.hh"
|
||||
|
||||
#if FULL_SYSTEM
|
||||
#include "kern/kernel_stats.hh"
|
||||
|
|
|
@ -34,8 +34,6 @@
|
|||
#include "config/full_system.hh"
|
||||
#include "cpu/o3/rename.hh"
|
||||
|
||||
using namespace std;
|
||||
|
||||
template <class Impl>
|
||||
DefaultRename<Impl>::DefaultRename(Params *params)
|
||||
: iewToRenameDelay(params->iewToRenameDelay),
|
||||
|
@ -223,7 +221,7 @@ DefaultRename<Impl>::initStage()
|
|||
|
||||
template<class Impl>
|
||||
void
|
||||
DefaultRename<Impl>::setActiveThreads(list<unsigned> *at_ptr)
|
||||
DefaultRename<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
|
||||
{
|
||||
DPRINTF(Rename, "Setting active threads list pointer.\n");
|
||||
activeThreads = at_ptr;
|
||||
|
@ -272,7 +270,8 @@ DefaultRename<Impl>::switchOut()
|
|||
{
|
||||
// Clear any state, fix up the rename map.
|
||||
for (int i = 0; i < numThreads; i++) {
|
||||
typename list<RenameHistory>::iterator hb_it = historyBuffer[i].begin();
|
||||
typename std::list<RenameHistory>::iterator hb_it =
|
||||
historyBuffer[i].begin();
|
||||
|
||||
while (!historyBuffer[i].empty()) {
|
||||
assert(hb_it != historyBuffer[i].end());
|
||||
|
@ -407,7 +406,7 @@ DefaultRename<Impl>::tick()
|
|||
|
||||
sortInsts();
|
||||
|
||||
list<unsigned>::iterator threads = (*activeThreads).begin();
|
||||
std::list<unsigned>::iterator threads = (*activeThreads).begin();
|
||||
|
||||
// Check stall and squash signals.
|
||||
while (threads != (*activeThreads).end()) {
|
||||
|
@ -759,7 +758,7 @@ template<class Impl>
|
|||
bool
|
||||
DefaultRename<Impl>::skidsEmpty()
|
||||
{
|
||||
list<unsigned>::iterator threads = (*activeThreads).begin();
|
||||
std::list<unsigned>::iterator threads = (*activeThreads).begin();
|
||||
|
||||
while (threads != (*activeThreads).end()) {
|
||||
if (!skidBuffer[*threads++].empty())
|
||||
|
@ -775,7 +774,7 @@ DefaultRename<Impl>::updateStatus()
|
|||
{
|
||||
bool any_unblocking = false;
|
||||
|
||||
list<unsigned>::iterator threads = (*activeThreads).begin();
|
||||
std::list<unsigned>::iterator threads = (*activeThreads).begin();
|
||||
|
||||
threads = (*activeThreads).begin();
|
||||
|
||||
|
@ -865,7 +864,8 @@ template <class Impl>
|
|||
void
|
||||
DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, unsigned tid)
|
||||
{
|
||||
typename list<RenameHistory>::iterator hb_it = historyBuffer[tid].begin();
|
||||
typename std::list<RenameHistory>::iterator hb_it =
|
||||
historyBuffer[tid].begin();
|
||||
|
||||
// After a syscall squashes everything, the history buffer may be empty
|
||||
// but the ROB may still be squashing instructions.
|
||||
|
@ -903,7 +903,8 @@ DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, unsigned tid)
|
|||
"history buffer %u (size=%i), until [sn:%lli].\n",
|
||||
tid, tid, historyBuffer[tid].size(), inst_seq_num);
|
||||
|
||||
typename list<RenameHistory>::iterator hb_it = historyBuffer[tid].end();
|
||||
typename std::list<RenameHistory>::iterator hb_it =
|
||||
historyBuffer[tid].end();
|
||||
|
||||
--hb_it;
|
||||
|
||||
|
@ -1302,7 +1303,7 @@ template <class Impl>
|
|||
void
|
||||
DefaultRename<Impl>::dumpHistory()
|
||||
{
|
||||
typename list<RenameHistory>::iterator buf_it;
|
||||
typename std::list<RenameHistory>::iterator buf_it;
|
||||
|
||||
for (int i = 0; i < numThreads; i++) {
|
||||
|
||||
|
|
|
@ -40,8 +40,7 @@
|
|||
#include <vector>
|
||||
|
||||
#include "cpu/o3/free_list.hh"
|
||||
//For RegIndex
|
||||
#include "arch/isa_traits.hh"
|
||||
#include "arch/types.hh"
|
||||
|
||||
class SimpleRenameMap
|
||||
{
|
||||
|
|
|
@ -32,11 +32,11 @@
|
|||
#include "config/full_system.hh"
|
||||
#include "cpu/o3/rob.hh"
|
||||
|
||||
using namespace std;
|
||||
#include <list>
|
||||
|
||||
template <class Impl>
|
||||
ROB<Impl>::ROB(unsigned _numEntries, unsigned _squashWidth,
|
||||
string _smtROBPolicy, unsigned _smtROBThreshold,
|
||||
std::string _smtROBPolicy, unsigned _smtROBThreshold,
|
||||
unsigned _numThreads)
|
||||
: numEntries(_numEntries),
|
||||
squashWidth(_squashWidth),
|
||||
|
@ -49,7 +49,7 @@ ROB<Impl>::ROB(unsigned _numEntries, unsigned _squashWidth,
|
|||
threadEntries[tid] = 0;
|
||||
}
|
||||
|
||||
string policy = _smtROBPolicy;
|
||||
std::string policy = _smtROBPolicy;
|
||||
|
||||
//Convert string to lowercase
|
||||
std::transform(policy.begin(), policy.end(), policy.begin(),
|
||||
|
@ -118,7 +118,7 @@ ROB<Impl>::setCPU(O3CPU *cpu_ptr)
|
|||
|
||||
template <class Impl>
|
||||
void
|
||||
ROB<Impl>::setActiveThreads(list<unsigned> *at_ptr)
|
||||
ROB<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
|
||||
{
|
||||
DPRINTF(ROB, "Setting active threads list pointer.\n");
|
||||
activeThreads = at_ptr;
|
||||
|
@ -157,8 +157,8 @@ ROB<Impl>::resetEntries()
|
|||
if (robPolicy != Dynamic || numThreads > 1) {
|
||||
int active_threads = (*activeThreads).size();
|
||||
|
||||
list<unsigned>::iterator threads = (*activeThreads).begin();
|
||||
list<unsigned>::iterator list_end = (*activeThreads).end();
|
||||
std::list<unsigned>::iterator threads = (*activeThreads).begin();
|
||||
std::list<unsigned>::iterator list_end = (*activeThreads).end();
|
||||
|
||||
while (threads != list_end) {
|
||||
if (robPolicy == Partitioned) {
|
||||
|
@ -318,7 +318,7 @@ bool
|
|||
ROB<Impl>::canCommit()
|
||||
{
|
||||
//@todo: set ActiveThreads through ROB or CPU
|
||||
list<unsigned>::iterator threads = (*activeThreads).begin();
|
||||
std::list<unsigned>::iterator threads = (*activeThreads).begin();
|
||||
|
||||
while (threads != (*activeThreads).end()) {
|
||||
unsigned tid = *threads++;
|
||||
|
@ -432,7 +432,7 @@ ROB<Impl>::updateHead()
|
|||
bool first_valid = true;
|
||||
|
||||
// @todo: set ActiveThreads through ROB or CPU
|
||||
list<unsigned>::iterator threads = (*activeThreads).begin();
|
||||
std::list<unsigned>::iterator threads = (*activeThreads).begin();
|
||||
|
||||
while (threads != (*activeThreads).end()) {
|
||||
unsigned thread_num = *threads++;
|
||||
|
@ -472,7 +472,7 @@ ROB<Impl>::updateTail()
|
|||
tail = instList[0].end();
|
||||
bool first_valid = true;
|
||||
|
||||
list<unsigned>::iterator threads = (*activeThreads).begin();
|
||||
std::list<unsigned>::iterator threads = (*activeThreads).begin();
|
||||
|
||||
while (threads != (*activeThreads).end()) {
|
||||
unsigned tid = *threads++;
|
||||
|
|
|
@ -35,7 +35,6 @@
|
|||
#include <iostream>
|
||||
#include <utility>
|
||||
#include <vector>
|
||||
#include "arch/isa_traits.hh"
|
||||
#include "base/trace.hh"
|
||||
#include "base/traceflags.hh"
|
||||
#include "cpu/o3/comm.hh"
|
||||
|
|
|
@ -36,8 +36,8 @@
|
|||
#include <utility>
|
||||
#include <vector>
|
||||
|
||||
#include "arch/isa_traits.hh"
|
||||
#include "cpu/inst_seq.hh"
|
||||
#include "sim/host.hh"
|
||||
|
||||
struct ltseqnum {
|
||||
bool operator()(const InstSeqNum &lhs, const InstSeqNum &rhs) const
|
||||
|
|
|
@ -32,8 +32,6 @@
|
|||
#include "cpu/o3/thread_context.hh"
|
||||
#include "cpu/quiesce_event.hh"
|
||||
|
||||
using namespace TheISA;
|
||||
|
||||
#if FULL_SYSTEM
|
||||
template <class Impl>
|
||||
VirtualPort *
|
||||
|
|
|
@ -31,8 +31,6 @@
|
|||
#ifndef __CPU_O3_THREAD_STATE_HH__
|
||||
#define __CPU_O3_THREAD_STATE_HH__
|
||||
|
||||
#include "arch/faults.hh"
|
||||
#include "arch/isa_traits.hh"
|
||||
#include "cpu/thread_context.hh"
|
||||
#include "cpu/thread_state.hh"
|
||||
|
||||
|
|
|
@ -31,9 +31,8 @@
|
|||
#ifndef __CPU_O3_TOURNAMENT_PRED_HH__
|
||||
#define __CPU_O3_TOURNAMENT_PRED_HH__
|
||||
|
||||
// For Addr type.
|
||||
#include "arch/isa_traits.hh"
|
||||
#include "cpu/o3/sat_counter.hh"
|
||||
#include "sim/host.hh"
|
||||
#include <vector>
|
||||
|
||||
/**
|
||||
|
|
|
@ -47,6 +47,7 @@
|
|||
#include "arch/faults.hh"
|
||||
#include "arch/alpha/osfpal.hh"
|
||||
#include "arch/alpha/tlb.hh"
|
||||
#include "arch/alpha/types.hh"
|
||||
#include "arch/vtophys.hh"
|
||||
#include "base/callback.hh"
|
||||
//#include "base/remote_gdb.hh"
|
||||
|
|
|
@ -32,6 +32,7 @@
|
|||
#define __CPU_OZONE_DYN_INST_HH__
|
||||
|
||||
#include "arch/isa_traits.hh"
|
||||
#include "arch/types.hh"
|
||||
#include "config/full_system.hh"
|
||||
#include "cpu/base_dyn_inst.hh"
|
||||
#include "cpu/inst_seq.hh"
|
||||
|
|
|
@ -29,13 +29,10 @@
|
|||
*/
|
||||
|
||||
#include "arch/faults.hh"
|
||||
#include "arch/isa_traits.hh"
|
||||
#include "config/full_system.hh"
|
||||
#include "cpu/ozone/dyn_inst.hh"
|
||||
#include "kern/kernel_stats.hh"
|
||||
|
||||
using namespace TheISA;
|
||||
|
||||
template <class Impl>
|
||||
OzoneDynInst<Impl>::OzoneDynInst(OzoneCPU *cpu)
|
||||
: BaseDynInst<Impl>(0, 0, 0, 0, cpu)
|
||||
|
|
|
@ -35,8 +35,8 @@
|
|||
#include <list>
|
||||
#include <utility>
|
||||
|
||||
#include "arch/isa_traits.hh"
|
||||
#include "cpu/inst_seq.hh"
|
||||
#include "sim/host.hh"
|
||||
|
||||
/**
|
||||
* Simple class to hold onto a list of pairs, each pair having a memory
|
||||
|
|
|
@ -32,6 +32,7 @@
|
|||
|
||||
#include "arch/faults.hh"
|
||||
#include "arch/isa_traits.hh"
|
||||
#include "arch/utility.hh"
|
||||
#include "base/statistics.hh"
|
||||
#include "cpu/thread_context.hh"
|
||||
#include "cpu/exetrace.hh"
|
||||
|
|
|
@ -29,12 +29,10 @@
|
|||
*/
|
||||
|
||||
#include "arch/faults.hh"
|
||||
#include "arch/isa_traits.hh"
|
||||
#include "arch/types.hh"
|
||||
#include "cpu/ozone/inorder_back_end.hh"
|
||||
#include "cpu/ozone/thread_state.hh"
|
||||
|
||||
using namespace TheISA;
|
||||
|
||||
template <class Impl>
|
||||
InorderBackEnd<Impl>::InorderBackEnd(Params *params)
|
||||
: squashPending(false),
|
||||
|
|
|
@ -36,7 +36,7 @@
|
|||
#include <algorithm>
|
||||
|
||||
#include "arch/faults.hh"
|
||||
#include "arch/isa_traits.hh"
|
||||
#include "arch/types.hh"
|
||||
#include "config/full_system.hh"
|
||||
#include "base/hashmap.hh"
|
||||
#include "cpu/inst_seq.hh"
|
||||
|
|
|
@ -28,7 +28,7 @@
|
|||
* Authors: Kevin Lim
|
||||
*/
|
||||
|
||||
#include "arch/isa_traits.hh"
|
||||
#include "arch/faults.hh"
|
||||
#include "base/str.hh"
|
||||
#include "cpu/ozone/lsq_unit.hh"
|
||||
|
||||
|
|
|
@ -37,7 +37,7 @@
|
|||
#include <algorithm>
|
||||
|
||||
#include "arch/faults.hh"
|
||||
#include "arch/isa_traits.hh"
|
||||
#include "arch/types.hh"
|
||||
#include "config/full_system.hh"
|
||||
#include "base/hashmap.hh"
|
||||
#include "cpu/inst_seq.hh"
|
||||
|
|
|
@ -30,7 +30,7 @@
|
|||
|
||||
#include "config/use_checker.hh"
|
||||
|
||||
#include "arch/isa_traits.hh"
|
||||
#include "arch/faults.hh"
|
||||
#include "base/str.hh"
|
||||
#include "cpu/ozone/lw_lsq.hh"
|
||||
#include "cpu/checker/cpu.hh"
|
||||
|
|
|
@ -31,8 +31,8 @@
|
|||
#ifndef __CPU_OZONE_NULL_PREDICTOR_HH__
|
||||
#define __CPU_OZONE_NULL_PREDICTOR_HH__
|
||||
|
||||
#include "arch/isa_traits.hh"
|
||||
#include "cpu/inst_seq.hh"
|
||||
#include "sim/host.hh"
|
||||
|
||||
template <class Impl>
|
||||
class NullPredictor
|
||||
|
|
|
@ -31,7 +31,6 @@
|
|||
#ifndef __CPU_OZONE_OZONE_IMPL_HH__
|
||||
#define __CPU_OZONE_OZONE_IMPL_HH__
|
||||
|
||||
#include "arch/alpha/isa_traits.hh"
|
||||
#include "cpu/o3/bpred_unit.hh"
|
||||
#include "cpu/ozone/front_end.hh"
|
||||
#include "cpu/ozone/inst_queue.hh"
|
||||
|
|
|
@ -31,7 +31,6 @@
|
|||
#ifndef __CPU_OZONE_SIMPLE_IMPL_HH__
|
||||
#define __CPU_OZONE_SIMPLE_IMPL_HH__
|
||||
|
||||
#include "arch/isa_traits.hh"
|
||||
#include "cpu/o3/bpred_unit.hh"
|
||||
#include "cpu/ozone/cpu.hh"
|
||||
#include "cpu/ozone/front_end.hh"
|
||||
|
|
|
@ -32,7 +32,8 @@
|
|||
#define __CPU_OZONE_THREAD_STATE_HH__
|
||||
|
||||
#include "arch/faults.hh"
|
||||
#include "arch/isa_traits.hh"
|
||||
#include "arch/types.hh"
|
||||
#include "arch/regfile.hh"
|
||||
#include "cpu/thread_context.hh"
|
||||
#include "cpu/thread_state.hh"
|
||||
#include "sim/process.hh"
|
||||
|
|
|
@ -35,13 +35,13 @@
|
|||
#include <string>
|
||||
|
||||
#include "arch/isa_traits.hh"
|
||||
#include "arch/faults.hh"
|
||||
#include "base/bitfield.hh"
|
||||
#include "base/hashmap.hh"
|
||||
#include "base/misc.hh"
|
||||
#include "base/refcnt.hh"
|
||||
#include "cpu/op_class.hh"
|
||||
#include "cpu/o3/dyn_inst.hh"
|
||||
#include "sim/faults.hh"
|
||||
#include "sim/host.hh"
|
||||
|
||||
// forward declarations
|
||||
|
|
|
@ -31,7 +31,7 @@
|
|||
#ifndef __CPU_THREAD_STATE_HH__
|
||||
#define __CPU_THREAD_STATE_HH__
|
||||
|
||||
#include "arch/isa_traits.hh"
|
||||
#include "arch/types.hh"
|
||||
#include "cpu/thread_context.hh"
|
||||
|
||||
#if !FULL_SYSTEM
|
||||
|
|
4
src/mem/cache/cache_impl.hh
vendored
4
src/mem/cache/cache_impl.hh
vendored
|
@ -53,8 +53,6 @@
|
|||
|
||||
#include "sim/sim_events.hh" // for SimExitEvent
|
||||
|
||||
using namespace std;
|
||||
|
||||
template<class TagStore, class Buffering, class Coherence>
|
||||
bool
|
||||
Cache<TagStore,Buffering,Coherence>::
|
||||
|
@ -501,7 +499,7 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update)
|
|||
MSHR* mshr = missQueue->findMSHR(blk_addr, pkt->req->getAsid());
|
||||
|
||||
// There can be many matching outstanding writes.
|
||||
vector<MSHR*> writes;
|
||||
std::vector<MSHR*> writes;
|
||||
missQueue->findWrites(blk_addr, pkt->req->getAsid(), writes);
|
||||
|
||||
if (!update) {
|
||||
|
|
2
src/mem/cache/miss/blocking_buffer.cc
vendored
2
src/mem/cache/miss/blocking_buffer.cc
vendored
|
@ -40,8 +40,6 @@
|
|||
#include "sim/eventq.hh" // for Event declaration.
|
||||
#include "mem/request.hh"
|
||||
|
||||
using namespace TheISA;
|
||||
|
||||
/**
|
||||
* @todo Move writebacks into shared BaseBuffer class.
|
||||
*/
|
||||
|
|
|
@ -33,6 +33,7 @@
|
|||
* Describes a tagged prefetcher based on template policies.
|
||||
*/
|
||||
|
||||
#include "arch/isa_traits.hh"
|
||||
#include "mem/cache/prefetch/tagged_prefetcher.hh"
|
||||
|
||||
template <class TagStore, class Buffering>
|
||||
|
|
|
@ -39,7 +39,7 @@
|
|||
#define __MEM_PACKET_HH__
|
||||
|
||||
#include "mem/request.hh"
|
||||
#include "arch/isa_traits.hh"
|
||||
#include "sim/host.hh"
|
||||
#include "sim/root.hh"
|
||||
#include <list>
|
||||
|
||||
|
|
|
@ -38,7 +38,7 @@
|
|||
|
||||
#include <string>
|
||||
|
||||
#include "arch/faults.hh"
|
||||
#include "sim/faults.hh"
|
||||
#include "arch/isa_traits.hh"
|
||||
#include "base/hashmap.hh"
|
||||
#include "base/trace.hh"
|
||||
|
|
|
@ -28,8 +28,6 @@
|
|||
* Authors: Ali Saidi
|
||||
*/
|
||||
|
||||
#include "arch/isa_specific.hh"
|
||||
#include "arch/isa_traits.hh"
|
||||
#include "mem/port.hh"
|
||||
#include "sim/byteswap.hh"
|
||||
|
||||
|
@ -37,7 +35,7 @@ template <typename T>
|
|||
void
|
||||
FunctionalPort::writeHtoG(Addr addr, T d)
|
||||
{
|
||||
d = TheISA::htog(d);
|
||||
d = htog(d);
|
||||
writeBlob(addr, (uint8_t*)&d, sizeof(T));
|
||||
}
|
||||
|
||||
|
@ -48,6 +46,6 @@ FunctionalPort::readGtoH(Addr addr)
|
|||
{
|
||||
T d;
|
||||
readBlob(addr, (uint8_t*)&d, sizeof(T));
|
||||
return TheISA::gtoh(d);
|
||||
return gtoh(d);
|
||||
}
|
||||
|
||||
|
|
|
@ -38,7 +38,7 @@
|
|||
#ifndef __MEM_REQUEST_HH__
|
||||
#define __MEM_REQUEST_HH__
|
||||
|
||||
#include "arch/isa_traits.hh"
|
||||
#include "sim/host.hh"
|
||||
#include "sim/root.hh"
|
||||
|
||||
class Request;
|
||||
|
|
|
@ -30,10 +30,8 @@
|
|||
|
||||
class ThreadContext;
|
||||
|
||||
//We need the "Tick" data type from here
|
||||
//We need the "Tick" and "Addr" data types from here
|
||||
#include "sim/host.hh"
|
||||
//We need the "Addr" data type from here
|
||||
#include "arch/isa_traits.hh"
|
||||
|
||||
namespace AlphaPseudo
|
||||
{
|
||||
|
|
Loading…
Reference in a new issue