sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

ARM: Ignore/warn access to the bpimva registers.

Browse source
This commit is contained in:
Gabe Black 2010-06-02 12:58:09 -05:00
parent 8a7f60194e
commit 741b243260
2 changed files with 6 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
src/arch/arm/isa/formats/misc.isa
View file

@ -119,6 +119,9 @@ def format McrMrc15() {{
case MISCREG_ICIMVAU: case MISCREG_ICIMVAU:
return new WarnUnimplemented( return new WarnUnimplemented(
isRead ? "mrc icimvau" : "mcr icimvau", machInst); isRead ? "mrc icimvau" : "mcr icimvau", machInst);
case MISCREG_BPIMVA:
return new WarnUnimplemented(
isRead ? "mrc bpimva" : "mcr bpimva", machInst);
default: default:
if (isRead) { if (isRead) {
return new Mrc15(machInst, rt, (IntRegIndex)miscReg); return new Mrc15(machInst, rt, (IntRegIndex)miscReg);

6
src/arch/arm/miscregs.hh
View file

@ -97,6 +97,7 @@ namespace ArmISA
MISCREG_ICIALLUIS, MISCREG_ICIALLUIS,
MISCREG_ICIALLU, MISCREG_ICIALLU,
MISCREG_ICIMVAU, MISCREG_ICIMVAU,
MISCREG_BPIMVA,
MISCREG_CP15_UNIMP_START, MISCREG_CP15_UNIMP_START,
MISCREG_CTR = MISCREG_CP15_UNIMP_START, MISCREG_CTR = MISCREG_CP15_UNIMP_START,
MISCREG_TCMTR, MISCREG_TCMTR,
@ -136,7 +137,6 @@ namespace ArmISA
MISCREG_RGNR, MISCREG_RGNR,
MISCREG_BPIALLIS, MISCREG_BPIALLIS,
MISCREG_BPIALL, MISCREG_BPIALL,
MISCREG_BPIMVA,
MISCREG_DCIMVAC, MISCREG_DCIMVAC,
MISCREG_DCISW, MISCREG_DCISW,
MISCREG_MCCSW, MISCREG_MCCSW,
@ -161,7 +161,7 @@ namespace ArmISA
"sctlr", "dccisw", "dccimvac", "dccmvac", "sctlr", "dccisw", "dccimvac", "dccmvac",
"contextidr", "tpidrurw", "tpidruro", "tpidrprw", "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
"cp15isb", "cp15dsb", "cp15dmb", "cpacr", "clidr", "cp15isb", "cp15dsb", "cp15dmb", "cpacr", "clidr",
"icialluis", "iciallu", "icimvau", "icialluis", "iciallu", "icimvau", "bpimva",
"ctr", "tcmtr", "mpuir", "mpidr", "midr", "ctr", "tcmtr", "mpuir", "mpidr", "midr",
"id_pfr0", "id_pfr1", "id_dfr0", "id_afr0", "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
"id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3", "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
@ -170,7 +170,7 @@ namespace ArmISA
"dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar", "dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar",
"drbar", "irbar", "drsr", "irsr", "dracr", "iracr", "drbar", "irbar", "drsr", "irsr", "dracr", "iracr",
"rgnr", "bpiallis", "rgnr", "bpiallis",
"bpiall", "bpimva", "dcimvac", "dcisw", "mccsw", "bpiall", "dcimvac", "dcisw", "mccsw",
"dccmvau", "dccmvau",
"nop", "raz" "nop", "raz"
}; };