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ARM: Do something for ISB, DSB, DMB

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This commit is contained in:
Ali Saidi 2011-02-23 15:10:49 -06:00
parent ae3d456855
commit 7391ea6de6
3 changed files with 13 additions and 10 deletions
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9
src/arch/arm/isa/formats/misc.isa
View file

@ -120,14 +120,11 @@ let {{
return new WarnUnimplemented( return new WarnUnimplemented(
isRead ? "mrc dccmvau" : "mcr dccmvau", machInst); isRead ? "mrc dccmvau" : "mcr dccmvau", machInst);
case MISCREG_CP15ISB: case MISCREG_CP15ISB:
return new WarnUnimplemented( return new Isb(machInst);
isRead ? "mrc cp15isb" : "mcr cp15isb", machInst);
case MISCREG_CP15DSB: case MISCREG_CP15DSB:
return new WarnUnimplemented( return new Dsb(machInst);
isRead ? "mrc cp15dsb" : "mcr cp15dsb", machInst);
case MISCREG_CP15DMB: case MISCREG_CP15DMB:
return new WarnUnimplemented( return new Dmb(machInst);
isRead ? "mrc cp15dmb" : "mcr cp15dmb", machInst);
case MISCREG_ICIALLUIS: case MISCREG_ICIALLUIS:
return new WarnUnimplemented( return new WarnUnimplemented(
isRead ? "mrc icialluis" : "mcr icialluis", machInst); isRead ? "mrc icialluis" : "mcr icialluis", machInst);

11
src/arch/arm/isa/insts/misc.isa
View file

@ -696,19 +696,23 @@ let {{
exec_output += ClrexCompleteAcc.subst(clrexIop) exec_output += ClrexCompleteAcc.subst(clrexIop)
isbCode = ''' isbCode = '''
fault = new FlushPipe;
''' '''
isbIop = InstObjParams("isb", "Isb", "PredOp", isbIop = InstObjParams("isb", "Isb", "PredOp",
{"code": isbCode, {"code": isbCode,
"predicate_test": predicateTest}, ['IsSerializing']) "predicate_test": predicateTest},
['IsSerializeAfter'])
header_output += BasicDeclare.subst(isbIop) header_output += BasicDeclare.subst(isbIop)
decoder_output += BasicConstructor.subst(isbIop) decoder_output += BasicConstructor.subst(isbIop)
exec_output += PredOpExecute.subst(isbIop) exec_output += PredOpExecute.subst(isbIop)
dsbCode = ''' dsbCode = '''
fault = new FlushPipe;
''' '''
dsbIop = InstObjParams("dsb", "Dsb", "PredOp", dsbIop = InstObjParams("dsb", "Dsb", "PredOp",
{"code": dsbCode, {"code": dsbCode,
"predicate_test": predicateTest},['IsMemBarrier']) "predicate_test": predicateTest},
['IsMemBarrier', 'IsSerializeAfter'])
header_output += BasicDeclare.subst(dsbIop) header_output += BasicDeclare.subst(dsbIop)
decoder_output += BasicConstructor.subst(dsbIop) decoder_output += BasicConstructor.subst(dsbIop)
exec_output += PredOpExecute.subst(dsbIop) exec_output += PredOpExecute.subst(dsbIop)
@ -717,7 +721,8 @@ let {{
''' '''
dmbIop = InstObjParams("dmb", "Dmb", "PredOp", dmbIop = InstObjParams("dmb", "Dmb", "PredOp",
{"code": dmbCode, {"code": dmbCode,
"predicate_test": predicateTest},['IsMemBarrier']) "predicate_test": predicateTest},
['IsMemBarrier'])
header_output += BasicDeclare.subst(dmbIop) header_output += BasicDeclare.subst(dmbIop)
decoder_output += BasicConstructor.subst(dmbIop) decoder_output += BasicConstructor.subst(dmbIop)
exec_output += PredOpExecute.subst(dmbIop) exec_output += PredOpExecute.subst(dmbIop)

3
src/cpu/o3/commit_impl.hh
View file

@ -1177,7 +1177,8 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
} }
} }
#endif #endif
DPRINTF(Commit, "Committing instruction with [sn:%lli]\n",
head_inst->seqNum);
if (head_inst->traceData) { if (head_inst->traceData) {
head_inst->traceData->setFetchSeq(head_inst->seqNum); head_inst->traceData->setFetchSeq(head_inst->seqNum);
head_inst->traceData->setCPSeq(thread[tid]->numInst); head_inst->traceData->setCPSeq(thread[tid]->numInst);