ARM: Do something for ISB, DSB, DMB
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parent
ae3d456855
commit
7391ea6de6
3 changed files with 13 additions and 10 deletions
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@ -120,14 +120,11 @@ let {{
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return new WarnUnimplemented(
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return new WarnUnimplemented(
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isRead ? "mrc dccmvau" : "mcr dccmvau", machInst);
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isRead ? "mrc dccmvau" : "mcr dccmvau", machInst);
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case MISCREG_CP15ISB:
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case MISCREG_CP15ISB:
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return new WarnUnimplemented(
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return new Isb(machInst);
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isRead ? "mrc cp15isb" : "mcr cp15isb", machInst);
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case MISCREG_CP15DSB:
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case MISCREG_CP15DSB:
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return new WarnUnimplemented(
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return new Dsb(machInst);
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isRead ? "mrc cp15dsb" : "mcr cp15dsb", machInst);
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case MISCREG_CP15DMB:
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case MISCREG_CP15DMB:
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return new WarnUnimplemented(
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return new Dmb(machInst);
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isRead ? "mrc cp15dmb" : "mcr cp15dmb", machInst);
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case MISCREG_ICIALLUIS:
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case MISCREG_ICIALLUIS:
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return new WarnUnimplemented(
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return new WarnUnimplemented(
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isRead ? "mrc icialluis" : "mcr icialluis", machInst);
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isRead ? "mrc icialluis" : "mcr icialluis", machInst);
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@ -696,19 +696,23 @@ let {{
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exec_output += ClrexCompleteAcc.subst(clrexIop)
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exec_output += ClrexCompleteAcc.subst(clrexIop)
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isbCode = '''
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isbCode = '''
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fault = new FlushPipe;
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'''
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'''
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isbIop = InstObjParams("isb", "Isb", "PredOp",
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isbIop = InstObjParams("isb", "Isb", "PredOp",
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{"code": isbCode,
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{"code": isbCode,
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"predicate_test": predicateTest}, ['IsSerializing'])
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"predicate_test": predicateTest},
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['IsSerializeAfter'])
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header_output += BasicDeclare.subst(isbIop)
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header_output += BasicDeclare.subst(isbIop)
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decoder_output += BasicConstructor.subst(isbIop)
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decoder_output += BasicConstructor.subst(isbIop)
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exec_output += PredOpExecute.subst(isbIop)
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exec_output += PredOpExecute.subst(isbIop)
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dsbCode = '''
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dsbCode = '''
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fault = new FlushPipe;
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'''
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'''
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dsbIop = InstObjParams("dsb", "Dsb", "PredOp",
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dsbIop = InstObjParams("dsb", "Dsb", "PredOp",
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{"code": dsbCode,
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{"code": dsbCode,
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"predicate_test": predicateTest},['IsMemBarrier'])
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"predicate_test": predicateTest},
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['IsMemBarrier', 'IsSerializeAfter'])
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header_output += BasicDeclare.subst(dsbIop)
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header_output += BasicDeclare.subst(dsbIop)
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decoder_output += BasicConstructor.subst(dsbIop)
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decoder_output += BasicConstructor.subst(dsbIop)
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exec_output += PredOpExecute.subst(dsbIop)
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exec_output += PredOpExecute.subst(dsbIop)
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@ -717,7 +721,8 @@ let {{
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'''
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'''
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dmbIop = InstObjParams("dmb", "Dmb", "PredOp",
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dmbIop = InstObjParams("dmb", "Dmb", "PredOp",
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{"code": dmbCode,
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{"code": dmbCode,
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"predicate_test": predicateTest},['IsMemBarrier'])
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"predicate_test": predicateTest},
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['IsMemBarrier'])
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header_output += BasicDeclare.subst(dmbIop)
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header_output += BasicDeclare.subst(dmbIop)
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decoder_output += BasicConstructor.subst(dmbIop)
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decoder_output += BasicConstructor.subst(dmbIop)
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exec_output += PredOpExecute.subst(dmbIop)
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exec_output += PredOpExecute.subst(dmbIop)
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@ -1177,7 +1177,8 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
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}
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}
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}
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}
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#endif
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#endif
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DPRINTF(Commit, "Committing instruction with [sn:%lli]\n",
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head_inst->seqNum);
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if (head_inst->traceData) {
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if (head_inst->traceData) {
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head_inst->traceData->setFetchSeq(head_inst->seqNum);
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head_inst->traceData->setFetchSeq(head_inst->seqNum);
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head_inst->traceData->setCPSeq(thread[tid]->numInst);
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head_inst->traceData->setCPSeq(thread[tid]->numInst);
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