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fix store instructions, pass fast/quick Atomic/TimingSimpleCPU regressions...

Browse source 
src/arch/mips/isa/decoder.isa:
    commment out deret instruction for now...
src/arch/mips/isa/formats/fp.isa:
    edit fp format
src/arch/mips/isa/formats/mem.isa:
    fix for basic store instructions

--HG--
extra : convert_revision : 30cb5a474e78ac9292b6ab37d433db947a177731
This commit is contained in:
Korey Sewell 2007-06-29 15:13:50 -04:00
parent e28cbc98a0
commit 738ecc495b
3 changed files with 12 additions and 19 deletions
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21
src/arch/mips/isa/decoder.isa
View file

@ -27,6 +27,7 @@
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// //
// Authors: Korey Sewell // Authors: Korey Sewell
// Brett Miller
//////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////
// //
@ -557,20 +558,12 @@ decode OPCODE_HI default Unknown::unknown() {
}}); }});
0x1F: deret({{ 0x1F: deret({{
// if(EJTagImplemented()) { //if(Debug_DM == 1){
if(Debug_DM == 1){ //Debug_DM = 1;
Debug_DM = 1; //Debug_IEXI = 0;
Debug_IEXI = 0; //NPC = DEPC;
NPC = DEPC; //}
} panic("deret not implemented");
else
{
// Undefined;
}
//} // EJTag Implemented
//else {
// Reserved Instruction Exception
//}
}}); }});
} }

4
src/arch/mips/isa/formats/fp.isa
View file

@ -150,8 +150,10 @@ output exec {{
//Read FCSR from FloatRegFile //Read FCSR from FloatRegFile
uint32_t fcsr_bits = cpu->tcBase()->readFloatRegBits(FCSR); uint32_t fcsr_bits = cpu->tcBase()->readFloatRegBits(FCSR);
uint32_t new_fcsr = genInvalidVector(fcsr_bits);
//Write FCSR from FloatRegFile //Write FCSR from FloatRegFile
cpu->tcBase()->setFloatRegOperandBits(FCSR, genInvalidVector(fcsr_bits)); cpu->tcBase()->setFloatRegBits(FCSR, new_fcsr);
if (traceData) { traceData->setData(mips_nan); } if (traceData) { traceData->setData(mips_nan); }
return true; return true;

6
src/arch/mips/isa/formats/mem.isa
View file

@ -369,7 +369,6 @@ def template StoreMemAccExecute {{
{ {
Addr EA; Addr EA;
Fault fault = NoFault; Fault fault = NoFault;
uint64_t write_result = 0;
%(fp_enable_check)s; %(fp_enable_check)s;
%(op_decl)s; %(op_decl)s;
@ -383,7 +382,7 @@ def template StoreMemAccExecute {{
if (fault == NoFault) { if (fault == NoFault) {
fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
memAccessFlags, &write_result); memAccessFlags, NULL);
// @NOTE: Need to Call Complete Access to Set Trace Data // @NOTE: Need to Call Complete Access to Set Trace Data
//if (traceData) { traceData->setData(Mem); } //if (traceData) { traceData->setData(Mem); }
} }
@ -434,7 +433,6 @@ def template StoreExecute {{
{ {
Addr EA; Addr EA;
Fault fault = NoFault; Fault fault = NoFault;
uint64_t write_result = 0;
%(fp_enable_check)s; %(fp_enable_check)s;
%(op_decl)s; %(op_decl)s;
@ -447,7 +445,7 @@ def template StoreExecute {{
if (fault == NoFault) { if (fault == NoFault) {
fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
memAccessFlags, &write_result); memAccessFlags, NULL);
if (traceData) { traceData->setData(Mem); } if (traceData) { traceData->setData(Mem); }
} }