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implement the Tcc instruction to call syscall.

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arch/sparc/isa/bitfields.isa:
    the trap field is 7:0
arch/sparc/isa/decoder.isa:
    add code to in the Tcc instruction to call a syscall
arch/sparc/isa_traits.hh:
    We need the syscall num register

--HG--
extra : convert_revision : 0861ec1dd8c7cac57765b22bc408fdffbe63fe2a
This commit is contained in:
Ali Saidi 2006-03-15 18:12:01 -05:00
parent 97e424982a
commit 7359e2df01
3 changed files with 18 additions and 3 deletions
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2
arch/sparc/isa/bitfields.isa
View file

@ -46,5 +46,5 @@ def bitfield SHCNT64 <5:0>;
def bitfield SIMM10 <9:0>;
def bitfield SIMM11 <10:0>;
def bitfield SIMM13 <12:0>;
def bitfield SW_TRAP <6:0>;
def bitfield SW_TRAP <7:0>;
def bitfield X <12>;

18
arch/sparc/isa/decoder.isa
View file

@ -532,12 +532,26 @@ decode OP default Trap::unknown({{IllegalInstruction}}) {
case 1: case 3:
throw illegal_instruction;
case 0:
if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, machInst<25:28>))
#if FULL_SYSTEM
throw trap_instruction;
#else
if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, machInst<25:28>))
// At least glibc only uses trap 0,
// solaris/sunos may use others
assert((I ? Rs1 + Rs2 : Rs1 + SW_TRAP) == 0);
xc->syscall();
#endif
break;
case 2:
if(passesCondition(xc->regs.MiscRegs.ccrFields.xcc, machInst<25:28>))
#if FULL_SYSTEM
throw trap_instruction;
#else
if(passesCondition(xc->regs.MiscRegs.ccrFields.xcc, machInst<25:28>))
// At least glibc only uses trap 0,
// solaris/sunos may use others
assert((I ? Rs1 + Rs2 : Rs1 + SW_TRAP) == 0);
xc->syscall();
#endif
break;
}
}}); //Tcc

1
arch/sparc/isa_traits.hh
View file

@ -106,6 +106,7 @@ namespace SparcISA
const int ArgumentReg3 = 11;
const int ArgumentReg4 = 12;
const int ArgumentReg5 = 13;
const int SyscallNumReg = 1;
// Some OS syscall sue a second register (o1) to return a second value
const int SyscallPseudoReturnReg = ArgumentReg1;