sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

Clean up BAR setting code.

Browse source 
--HG--
extra : convert_revision : 8378be6cd6f55af7a199296cb2ff61ee94849bf7
This commit is contained in:
Steve Reinhardt 2006-08-28 11:17:49 -07:00
parent b77da23e1a
commit 72eb4f5f12
1 changed files with 23 additions and 30 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

47
src/dev/pcidev.cc
View file

@ -252,41 +252,34 @@ PciDev::writeConfig(Packet *pkt)
case PCI0_BASE_ADDR3:
case PCI0_BASE_ADDR4:
case PCI0_BASE_ADDR5:
{
int barnum = BAR_NUMBER(offset);
uint32_t barnum, bar_mask;
Addr base_addr, base_size, space_base;
// convert BAR values to host endianness
uint32_t he_old_bar = letoh(config.baseAddr[barnum]);
uint32_t he_new_bar = letoh(pkt->get<uint32_t>());
barnum = BAR_NUMBER(offset);
if (BAR_IO_SPACE(letoh(config.baseAddr[barnum]))) {
bar_mask = BAR_IO_MASK;
space_base = TSUNAMI_PCI0_IO;
} else {
bar_mask = BAR_MEM_MASK;
space_base = TSUNAMI_PCI0_MEMORY;
}
uint32_t bar_mask =
BAR_IO_SPACE(he_old_bar) ? BAR_IO_MASK : BAR_MEM_MASK;
// Writing 0xffffffff to a BAR tells the card to set the
// value of the bar to size of memory it needs
if (letoh(pkt->get<uint32_t>()) == 0xffffffff) {
// This is I/O Space, bottom two bits are read only
config.baseAddr[barnum] = letoh(
(~(BARSize[barnum] - 1) & ~bar_mask) |
(letoh(config.baseAddr[barnum]) & bar_mask));
// value of the bar to a bitmask indicating the size of
// memory it needs
if (he_new_bar == 0xffffffff) {
he_new_bar = ~(BARSize[barnum] - 1);
} else {
config.baseAddr[barnum] = letoh(
(letoh(pkt->get<uint32_t>()) & ~bar_mask) |
(letoh(config.baseAddr[barnum]) & bar_mask));
if (letoh(config.baseAddr[barnum]) & ~bar_mask) {
base_addr = (letoh(pkt->get<uint32_t>()) & ~bar_mask) + space_base;
base_size = BARSize[barnum];
BARAddrs[barnum] = base_addr;
// does it mean something special to write 0 to a BAR?
he_new_bar &= ~bar_mask;
if (he_new_bar) {
Addr space_base = BAR_IO_SPACE(he_old_bar) ?
TSUNAMI_PCI0_IO : TSUNAMI_PCI0_MEMORY;
BARAddrs[barnum] = he_new_bar + space_base;
pioPort->sendStatusChange(Port::RangeChange);
}
}
config.baseAddr[barnum] = htole((he_new_bar & ~bar_mask) |
(he_old_bar & bar_mask));
}
break;
case PCI0_ROM_BASE_ADDR: