Update configs for cpu_id
tests/configs/o3-timing-mp.py: tests/configs/simple-atomic-mp.py: tests/configs/simple-timing-mp.py: Update config for cpu_id --HG-- extra : convert_revision : 32a1971997920473164ba12f2b121cb640bad7ac
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3 changed files with 5 additions and 5 deletions
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@ -54,7 +54,7 @@ class L2(BaseCache):
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write_buffers = 8
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write_buffers = 8
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nb_cores = 4
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nb_cores = 4
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cpus = [ DetailedO3CPU() for i in xrange(nb_cores) ]
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cpus = [ DetailedO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
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# system simulated
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# system simulated
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system = System(cpu = cpus, physmem = PhysicalMemory(), membus =
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system = System(cpu = cpus, physmem = PhysicalMemory(), membus =
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@ -86,5 +86,5 @@ system.physmem.port = system.membus.port
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root = Root( system = system )
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root = Root( system = system )
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root.system.mem_mode = 'timing'
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root.system.mem_mode = 'timing'
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root.trace.flags="Bus Cache"
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#root.trace.flags="Bus Cache"
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#root.trace.flags = "BusAddrRanges"
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#root.trace.flags = "BusAddrRanges"
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@ -52,10 +52,10 @@ class L2(BaseCache):
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write_buffers = 8
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write_buffers = 8
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nb_cores = 4
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nb_cores = 4
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cpus = [ AtomicSimpleCPU() for i in xrange(nb_cores) ]
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cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
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# system simulated
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# system simulated
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system = System(cpu = cpus, physmem = PhysicalMemory(), membus =
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system = System(cpu = cpus, physmem = PhysicalMemory(range = AddrRange('1024MB')), membus =
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Bus())
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Bus())
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# l2cache & bus
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# l2cache & bus
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@ -52,7 +52,7 @@ class L2(BaseCache):
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write_buffers = 8
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write_buffers = 8
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nb_cores = 4
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nb_cores = 4
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cpus = [ TimingSimpleCPU() for i in xrange(nb_cores) ]
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cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
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# system simulated
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# system simulated
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system = System(cpu = cpus, physmem = PhysicalMemory(), membus =
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system = System(cpu = cpus, physmem = PhysicalMemory(), membus =
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