refactor code for the packet, get rid of packet_impl.hh

and call it packet_access.hh and fix the #includes so
things compile right.

--HG--
extra : convert_revision : d3626c9715b9f7e51bb3ab8d97e971fad4e0b724
This commit is contained in:
Nathan Binkert 2006-10-19 23:38:45 -07:00
parent 5b246a0567
commit 7245d4530d
30 changed files with 174 additions and 57 deletions

View file

@ -73,8 +73,9 @@ output exec {{
#include "config/ss_compatible_fp.hh" #include "config/ss_compatible_fp.hh"
#include "cpu/base.hh" #include "cpu/base.hh"
#include "cpu/exetrace.hh" #include "cpu/exetrace.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/sim_exit.hh" #include "sim/sim_exit.hh"
#include "mem/packet_impl.hh"
using namespace AlphaISA; using namespace AlphaISA;
}}; }};

View file

@ -74,8 +74,9 @@ output exec {{
#endif #endif
#include "cpu/base.hh" #include "cpu/base.hh"
#include "cpu/exetrace.hh" #include "cpu/exetrace.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/sim_exit.hh" #include "sim/sim_exit.hh"
#include "mem/packet_impl.hh"
using namespace MipsISA; using namespace MipsISA;
}}; }};

View file

@ -34,10 +34,8 @@
#include "cpu/base.hh" #include "cpu/base.hh"
#include "cpu/checker/cpu.hh" #include "cpu/checker/cpu.hh"
#include "cpu/simple_thread.hh" #include "cpu/simple_thread.hh"
#include "cpu/thread_context.hh"
#include "cpu/static_inst.hh" #include "cpu/static_inst.hh"
#include "mem/packet_impl.hh" #include "cpu/thread_context.hh"
#include "sim/byteswap.hh"
#if FULL_SYSTEM #if FULL_SYSTEM
#include "arch/vtophys.hh" #include "arch/vtophys.hh"

View file

@ -37,8 +37,6 @@
#include "cpu/simple_thread.hh" #include "cpu/simple_thread.hh"
#include "cpu/thread_context.hh" #include "cpu/thread_context.hh"
#include "cpu/static_inst.hh" #include "cpu/static_inst.hh"
#include "mem/packet_impl.hh"
#include "sim/byteswap.hh"
#include "sim/sim_object.hh" #include "sim/sim_object.hh"
#include "sim/stats.hh" #include "sim/stats.hh"

View file

@ -38,17 +38,17 @@
#include "base/misc.hh" #include "base/misc.hh"
#include "base/statistics.hh" #include "base/statistics.hh"
//#include "cpu/simple_thread.hh"
#include "cpu/memtest/memtest.hh" #include "cpu/memtest/memtest.hh"
//#include "cpu/simple_thread.hh"
//#include "mem/cache/base_cache.hh" //#include "mem/cache/base_cache.hh"
#include "mem/mem_object.hh"
#include "mem/port.hh"
#include "mem/packet.hh"
//#include "mem/physical.hh" //#include "mem/physical.hh"
#include "mem/request.hh"
#include "sim/builder.hh" #include "sim/builder.hh"
#include "sim/sim_events.hh" #include "sim/sim_events.hh"
#include "sim/stats.hh" #include "sim/stats.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
#include "mem/port.hh"
#include "mem/mem_object.hh"
using namespace std; using namespace std;

View file

@ -36,7 +36,7 @@
#include "base/statistics.hh" #include "base/statistics.hh"
#include "base/timebuf.hh" #include "base/timebuf.hh"
#include "cpu/pc_event.hh" #include "cpu/pc_event.hh"
#include "mem/packet_impl.hh" #include "mem/packet.hh"
#include "mem/port.hh" #include "mem/port.hh"
#include "sim/eventq.hh" #include "sim/eventq.hh"

View file

@ -40,7 +40,7 @@
#include "config/full_system.hh" #include "config/full_system.hh"
#include "base/hashmap.hh" #include "base/hashmap.hh"
#include "cpu/inst_seq.hh" #include "cpu/inst_seq.hh"
#include "mem/packet_impl.hh" #include "mem/packet.hh"
#include "mem/port.hh" #include "mem/port.hh"
/** /**

View file

@ -32,7 +32,8 @@
#include "arch/utility.hh" #include "arch/utility.hh"
#include "cpu/exetrace.hh" #include "cpu/exetrace.hh"
#include "cpu/simple/atomic.hh" #include "cpu/simple/atomic.hh"
#include "mem/packet_impl.hh" #include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/builder.hh" #include "sim/builder.hh"
#include "sim/system.hh" #include "sim/system.hh"

View file

@ -47,7 +47,7 @@
#include "cpu/static_inst.hh" #include "cpu/static_inst.hh"
#include "cpu/thread_context.hh" #include "cpu/thread_context.hh"
#include "kern/kernel_stats.hh" #include "kern/kernel_stats.hh"
#include "mem/packet_impl.hh" #include "mem/packet.hh"
#include "sim/builder.hh" #include "sim/builder.hh"
#include "sim/byteswap.hh" #include "sim/byteswap.hh"
#include "sim/debug.hh" #include "sim/debug.hh"

View file

@ -32,7 +32,8 @@
#include "arch/utility.hh" #include "arch/utility.hh"
#include "cpu/exetrace.hh" #include "cpu/exetrace.hh"
#include "cpu/simple/timing.hh" #include "cpu/simple/timing.hh"
#include "mem/packet_impl.hh" #include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/builder.hh" #include "sim/builder.hh"
#include "sim/system.hh" #include "sim/system.hh"

View file

@ -48,6 +48,8 @@
#include "dev/platform.hh" #include "dev/platform.hh"
#include "dev/simconsole.hh" #include "dev/simconsole.hh"
#include "dev/simple_disk.hh" #include "dev/simple_disk.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "mem/physical.hh" #include "mem/physical.hh"
#include "sim/builder.hh" #include "sim/builder.hh"
#include "sim/sim_object.hh" #include "sim/sim_object.hh"

View file

@ -43,6 +43,7 @@
#include "dev/pcireg.h" #include "dev/pcireg.h"
#include "dev/platform.hh" #include "dev/platform.hh"
#include "mem/packet.hh" #include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/builder.hh" #include "sim/builder.hh"
#include "sim/sim_object.hh" #include "sim/sim_object.hh"
#include "sim/byteswap.hh" #include "sim/byteswap.hh"

View file

@ -33,9 +33,9 @@
#define __DEV_IO_DEVICE_HH__ #define __DEV_IO_DEVICE_HH__
#include "mem/mem_object.hh" #include "mem/mem_object.hh"
#include "mem/packet_impl.hh" #include "mem/packet.hh"
#include "sim/sim_object.hh"
#include "mem/tport.hh" #include "mem/tport.hh"
#include "sim/sim_object.hh"
class Event; class Event;
class Platform; class Platform;

View file

@ -40,6 +40,7 @@
#include "base/trace.hh" #include "base/trace.hh"
#include "dev/isa_fake.hh" #include "dev/isa_fake.hh"
#include "mem/packet.hh" #include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/builder.hh" #include "sim/builder.hh"
#include "sim/system.hh" #include "sim/system.hh"

View file

@ -36,9 +36,10 @@
#ifndef __ISA_FAKE_HH__ #ifndef __ISA_FAKE_HH__
#define __ISA_FAKE_HH__ #define __ISA_FAKE_HH__
#include "dev/tsunami.hh"
#include "base/range.hh" #include "base/range.hh"
#include "dev/io_device.hh" #include "dev/io_device.hh"
#include "dev/tsunami.hh"
#include "mem/packet.hh"
/** /**
* IsaFake is a device that returns -1 on all reads and * IsaFake is a device that returns -1 on all reads and

View file

@ -43,6 +43,7 @@
#include "dev/ns_gige.hh" #include "dev/ns_gige.hh"
#include "dev/pciconfigall.hh" #include "dev/pciconfigall.hh"
#include "mem/packet.hh" #include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/builder.hh" #include "sim/builder.hh"
#include "sim/debug.hh" #include "sim/debug.hh"
#include "sim/host.hh" #include "sim/host.hh"

View file

@ -38,6 +38,7 @@
#include "dev/pcireg.h" #include "dev/pcireg.h"
#include "dev/platform.hh" #include "dev/platform.hh"
#include "mem/packet.hh" #include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/builder.hh" #include "sim/builder.hh"
#include "sim/system.hh" #include "sim/system.hh"

View file

@ -47,6 +47,7 @@
#include "dev/pcidev.hh" #include "dev/pcidev.hh"
#include "dev/tsunamireg.h" #include "dev/tsunamireg.h"
#include "mem/packet.hh" #include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/builder.hh" #include "sim/builder.hh"
#include "sim/byteswap.hh" #include "sim/byteswap.hh"
#include "sim/param.hh" #include "sim/param.hh"

View file

@ -40,6 +40,7 @@
#include "dev/io_device.hh" #include "dev/io_device.hh"
#include "dev/pcireg.h" #include "dev/pcireg.h"
#include "dev/platform.hh" #include "dev/platform.hh"
#include "sim/byteswap.hh"
#define BAR_IO_MASK 0x3 #define BAR_IO_MASK 0x3
#define BAR_MEM_MASK 0xF #define BAR_MEM_MASK 0xF

View file

@ -38,6 +38,7 @@
#include "dev/etherlink.hh" #include "dev/etherlink.hh"
#include "dev/sinic.hh" #include "dev/sinic.hh"
#include "mem/packet.hh" #include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/builder.hh" #include "sim/builder.hh"
#include "sim/debug.hh" #include "sim/debug.hh"
#include "sim/eventq.hh" #include "sim/eventq.hh"

View file

@ -39,12 +39,14 @@
#include "arch/alpha/ev5.hh" #include "arch/alpha/ev5.hh"
#include "base/trace.hh" #include "base/trace.hh"
#include "cpu/intr_control.hh"
#include "cpu/thread_context.hh"
#include "dev/tsunami.hh"
#include "dev/tsunami_cchip.hh" #include "dev/tsunami_cchip.hh"
#include "dev/tsunamireg.h" #include "dev/tsunamireg.h"
#include "dev/tsunami.hh" #include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "mem/port.hh" #include "mem/port.hh"
#include "cpu/thread_context.hh"
#include "cpu/intr_control.hh"
#include "sim/builder.hh" #include "sim/builder.hh"
#include "sim/system.hh" #include "sim/system.hh"

View file

@ -47,6 +47,8 @@
#include "dev/tsunami.hh" #include "dev/tsunami.hh"
#include "dev/tsunami_io.hh" #include "dev/tsunami_io.hh"
#include "dev/tsunamireg.h" #include "dev/tsunamireg.h"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "mem/port.hh" #include "mem/port.hh"
#include "sim/builder.hh" #include "sim/builder.hh"
#include "sim/system.hh" #include "sim/system.hh"

View file

@ -42,6 +42,7 @@
#include "dev/tsunamireg.h" #include "dev/tsunamireg.h"
#include "dev/tsunami.hh" #include "dev/tsunami.hh"
#include "mem/packet.hh" #include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/builder.hh" #include "sim/builder.hh"
#include "sim/system.hh" #include "sim/system.hh"

View file

@ -42,6 +42,8 @@
#include "dev/simconsole.hh" #include "dev/simconsole.hh"
#include "dev/uart8250.hh" #include "dev/uart8250.hh"
#include "dev/platform.hh" #include "dev/platform.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/builder.hh" #include "sim/builder.hh"
using namespace std; using namespace std;

View file

@ -33,11 +33,10 @@
* Definition of BaseCache functions. * Definition of BaseCache functions.
*/ */
#include "cpu/base.hh"
#include "cpu/smt.hh"
#include "mem/cache/base_cache.hh" #include "mem/cache/base_cache.hh"
#include "mem/cache/miss/mshr.hh" #include "mem/cache/miss/mshr.hh"
#include "mem/packet_impl.hh"
#include "cpu/smt.hh"
#include "cpu/base.hh"
using namespace std; using namespace std;

View file

@ -36,9 +36,10 @@
*/ */
#include <iostream> #include <iostream>
#include "base/misc.hh" #include "base/misc.hh"
#include "mem/packet.hh"
#include "base/trace.hh" #include "base/trace.hh"
#include "mem/packet.hh"
static const std::string ReadReqString("ReadReq"); static const std::string ReadReqString("ReadReq");
static const std::string WriteReqString("WriteReq"); static const std::string WriteReqString("WriteReq");

View file

@ -38,11 +38,12 @@
#ifndef __MEM_PACKET_HH__ #ifndef __MEM_PACKET_HH__
#define __MEM_PACKET_HH__ #define __MEM_PACKET_HH__
#include <cassert>
#include <list>
#include "mem/request.hh" #include "mem/request.hh"
#include "sim/host.hh" #include "sim/host.hh"
#include "sim/root.hh" #include "sim/root.hh"
#include <list>
#include <cassert>
struct Packet; struct Packet;
typedef Packet* PacketPtr; typedef Packet* PacketPtr;
@ -342,10 +343,12 @@ class Packet
srcValid = false; srcValid = false;
} }
/** Take a request packet and modify it in place to be suitable /**
* for returning as a response to that request. * Take a request packet and modify it in place to be suitable for
* returning as a response to that request.
*/ */
void makeAtomicResponse() { void makeAtomicResponse()
{
assert(needsResponse()); assert(needsResponse());
assert(isRequest()); assert(isRequest());
int icmd = (int)cmd; int icmd = (int)cmd;
@ -358,43 +361,83 @@ class Packet
cmd = (Command)icmd; cmd = (Command)icmd;
} }
/** Take a request packet that has been returned as NACKED and modify it so /**
* that it can be sent out again. Only packets that need a response can be * Take a request packet that has been returned as NACKED and
* NACKED, so verify that that is true. */ * modify it so that it can be sent out again. Only packets that
void reinitNacked() { * need a response can be NACKED, so verify that that is true.
*/
void
reinitNacked()
{
assert(needsResponse() && result == Nacked); assert(needsResponse() && result == Nacked);
dest = Broadcast; dest = Broadcast;
result = Unknown; result = Unknown;
} }
/** Set the data pointer to the following value that should not be freed. */ /**
template <typename T> * Set the data pointer to the following value that should not be
void dataStatic(T *p); * freed.
/** Set the data pointer to a value that should have delete [] called on it.
*/ */
template <typename T> template <typename T>
void dataDynamicArray(T *p); void
dataStatic(T *p)
{
if(dynamicData)
dynamicData = false;
data = (PacketDataPtr)p;
staticData = true;
}
/** set the data pointer to a value that should have delete called on it. */ /**
* Set the data pointer to a value that should have delete []
* called on it.
*/
template <typename T> template <typename T>
void dataDynamic(T *p); void
dataDynamicArray(T *p)
{
assert(!staticData && !dynamicData);
data = (PacketDataPtr)p;
dynamicData = true;
arrayData = true;
}
/**
* set the data pointer to a value that should have delete called
* on it.
*/
template <typename T>
void
dataDynamic(T *p)
{
assert(!staticData && !dynamicData);
data = (PacketDataPtr)p;
dynamicData = true;
arrayData = false;
}
/** get a pointer to the data ptr. */
template <typename T>
T*
getPtr()
{
assert(staticData || dynamicData);
return (T*)data;
}
/** return the value of what is pointed to in the packet. */ /** return the value of what is pointed to in the packet. */
template <typename T> template <typename T>
T get(); T get();
/** get a pointer to the data ptr. */
template <typename T>
T* getPtr();
/** set the value in the data pointer to v. */ /** set the value in the data pointer to v. */
template <typename T> template <typename T>
void set(T v); void set(T v);
/** delete the data pointed to in the data pointer. Ok to call to matter how /**
* data was allocted. */ * delete the data pointed to in the data pointer. Ok to call to
* matter how data was allocted.
*/
void deleteData(); void deleteData();
/** If there isn't data in the packet, allocate some. */ /** If there isn't data in the packet, allocate some. */

62
src/mem/packet_access.hh Normal file
View file

@ -0,0 +1,62 @@
/*
* Copyright (c) 2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Ali Saidi
* Nathan Binkert
*/
#include "arch/isa_traits.hh"
#include "mem/packet.hh"
#include "sim/byteswap.hh"
#ifndef __MEM_PACKET_ACCESS_HH__
#define __MEM_PACKET_ACCESS_HH__
// The memory system needs to have an endianness. This is the easiest
// way to deal with it for now. At some point, we will have to remove
// these functions and make the users do their own byte swapping since
// the memory system does not in fact have an endianness.
/** return the value of what is pointed to in the packet. */
template <typename T>
inline T
Packet::get()
{
assert(staticData || dynamicData);
assert(sizeof(T) <= size);
return TheISA::gtoh(*(T*)data);
}
/** set the value in the data pointer to v. */
template <typename T>
inline void
Packet::set(T v)
{
assert(sizeof(T) <= size);
*(T*)data = TheISA::htog(v);
}
#endif //__MEM_PACKET_ACCESS_HH__

View file

@ -39,21 +39,17 @@
#include <iostream> #include <iostream>
#include <string> #include <string>
#include "arch/isa_traits.hh"
#include "base/misc.hh" #include "base/misc.hh"
#include "config/full_system.hh" #include "config/full_system.hh"
#include "mem/packet_impl.hh"
#include "mem/physical.hh" #include "mem/physical.hh"
#include "sim/host.hh"
#include "sim/builder.hh" #include "sim/builder.hh"
#include "sim/eventq.hh" #include "sim/eventq.hh"
#include "arch/isa_traits.hh" #include "sim/host.hh"
using namespace std; using namespace std;
using namespace TheISA; using namespace TheISA;
PhysicalMemory::PhysicalMemory(Params *p) PhysicalMemory::PhysicalMemory(Params *p)
: MemObject(p->name), pmemAddr(NULL), port(NULL), lat(p->latency), _params(p) : MemObject(p->name), pmemAddr(NULL), port(NULL), lat(p->latency), _params(p)
{ {

View file

@ -35,7 +35,6 @@
#include "base/chunk_generator.hh" #include "base/chunk_generator.hh"
#include "base/trace.hh" #include "base/trace.hh"
#include "mem/packet_impl.hh"
#include "mem/port.hh" #include "mem/port.hh"
void void