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tests: update t1000 & pc-switcheroo-full stats

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committed reference config.json files too
This commit is contained in:
Steve Reinhardt 2014-05-12 17:22:17 -04:00
parent 2136feaa55
commit 72403cb595
10 changed files with 3308 additions and 126 deletions
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38
tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini
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@ -20,13 +20,14 @@ eventq_index=0
init_param=0 init_param=0
intel_mp_pointer=system.intel_mp_pointer intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table intel_mp_table=system.intel_mp_table
kernel=/dist/binaries/x86_64-vmlinux-2.6.22.9 kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
load_addr_mask=18446744073709551615 load_addr_mask=18446744073709551615
load_offset=0
mem_mode=atomic mem_mode=atomic
mem_ranges=0:134217727 mem_ranges=0:134217727
memories=system.physmem memories=system.physmem
num_work_ids=16 num_work_ids=16
readfile=tests/halt.sh readfile=/z/stever/hg/gem5/tests/halt.sh
smbios_table=system.smbios_table smbios_table=system.smbios_table
symbolfile= symbolfile=
work_begin_ckpt_count=0 work_begin_ckpt_count=0
@ -88,6 +89,7 @@ voltage_domain=system.voltage_domain
[system.cpu0] [system.cpu0]
type=AtomicSimpleCPU type=AtomicSimpleCPU
children=apic_clk_domain dcache dtb icache interrupts isa itb tracer children=apic_clk_domain dcache dtb icache interrupts isa itb tracer
branchPred=Null
checker=Null checker=Null
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
cpu_id=0 cpu_id=0
@ -115,6 +117,7 @@ simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts= simpoint_start_insts=
simulate_data_stalls=false simulate_data_stalls=false
simulate_inst_stalls=false simulate_inst_stalls=false
socket_id=0
switched_out=false switched_out=false
system=system system=system
tracer=system.cpu0.tracer tracer=system.cpu0.tracer
@ -252,6 +255,7 @@ eventq_index=0
[system.cpu1] [system.cpu1]
type=TimingSimpleCPU type=TimingSimpleCPU
children=dtb isa itb tracer children=dtb isa itb tracer
branchPred=Null
checker=Null checker=Null
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
cpu_id=0 cpu_id=0
@ -273,6 +277,7 @@ numThreads=1
profile=0 profile=0
progress_interval=0 progress_interval=0
simpoint_start_insts= simpoint_start_insts=
socket_id=0
switched_out=true switched_out=true
system=system system=system
tracer=system.cpu1.tracer tracer=system.cpu1.tracer
@ -390,6 +395,7 @@ smtLSQThreshold=100
smtNumFetchingThreads=1 smtNumFetchingThreads=1
smtROBPolicy=Partitioned smtROBPolicy=Partitioned
smtROBThreshold=100 smtROBThreshold=100
socket_id=0
squashWidth=8 squashWidth=8
store_set_clear_period=250000 store_set_clear_period=250000
switched_out=true switched_out=true
@ -1591,7 +1597,7 @@ table_size=65536
[system.pc.south_bridge.ide.disks0.image.child] [system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage type=RawDiskImage
eventq_index=0 eventq_index=0
image_file=/dist/disks/linux-x86.img image_file=/dist/m5/system/disks/linux-x86.img
read_only=true read_only=true
[system.pc.south_bridge.ide.disks1] [system.pc.south_bridge.ide.disks1]
@ -1614,7 +1620,7 @@ table_size=65536
[system.pc.south_bridge.ide.disks1.image.child] [system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage type=RawDiskImage
eventq_index=0 eventq_index=0
image_file=/dist/disks/linux-bigswap2.img image_file=/dist/m5/system/disks/linux-bigswap2.img
read_only=true read_only=true
[system.pc.south_bridge.int_lines0] [system.pc.south_bridge.int_lines0]
@ -1803,9 +1809,9 @@ system=system
pio=system.iobus.master[9] pio=system.iobus.master[9]
[system.physmem] [system.physmem]
type=SimpleDRAM type=DRAMCtrl
activation_limit=4 activation_limit=4
addr_mapping=RaBaChCo addr_mapping=RoRaBaChCo
banks_per_rank=8 banks_per_rank=8
burst_length=8 burst_length=8
channels=1 channels=1
@ -1816,27 +1822,33 @@ device_rowbuffer_size=1024
devices_per_rank=8 devices_per_rank=8
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false null=false
page_policy=open page_policy=open_adaptive
range=0:134217727 range=0:134217727
ranks_per_channel=2 ranks_per_channel=2
read_buffer_size=32 read_buffer_size=32
static_backend_latency=10000 static_backend_latency=10000
static_frontend_latency=10000 static_frontend_latency=10000
tBURST=5000 tBURST=5000
tCK=1250
tCL=13750 tCL=13750
tRAS=35000 tRAS=35000
tRCD=13750 tRCD=13750
tREFI=7800000 tREFI=7800000
tRFC=300000 tRFC=260000
tRP=13750 tRP=13750
tRRD=6250 tRRD=6000
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500 tWTR=7500
tXAW=40000 tXAW=30000
write_buffer_size=32 write_buffer_size=64
write_high_thresh_perc=70 write_high_thresh_perc=85
write_low_thresh_perc=0 write_low_thresh_perc=50
port=system.membus.master[3] port=system.membus.master[3]
[system.smbios_table] [system.smbios_table]

2374
tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json Normal file
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File diff suppressed because it is too large Load diff

8
tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout
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@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 22 2014 17:10:34 gem5 compiled May 12 2014 12:50:47
gem5 started Jan 22 2014 22:25:31 gem5 started May 12 2014 15:35:34
gem5 executing on u200540-lin gem5 executing on zizzer
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full -re /z/stever/hg/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012

124
tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
View file

@ -4,13 +4,13 @@ sim_seconds 5.133875 # Nu
sim_ticks 5133874673500 # Number of ticks simulated sim_ticks 5133874673500 # Number of ticks simulated
final_tick 5133874673500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 5133874673500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 230895 # Simulator instruction rate (inst/s) host_inst_rate 236000 # Simulator instruction rate (inst/s)
host_op_rate 458967 # Simulator op (including micro ops) rate (op/s) host_op_rate 469116 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 4861072606 # Simulator tick rate (ticks/s) host_tick_rate 4968557721 # Simulator tick rate (ticks/s)
host_mem_usage 966208 # Number of bytes of host memory used host_mem_usage 928744 # Number of bytes of host memory used
host_seconds 1056.12 # Real time elapsed on the host host_seconds 1033.27 # Real time elapsed on the host
sim_insts 243852608 # Number of instructions simulated sim_insts 243852609 # Number of instructions simulated
sim_ops 484724489 # Number of ops (including micro ops) simulated sim_ops 484724493 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::pc.south_bridge.ide 2445440 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 2445440 # Number of bytes read from this memory
@ -309,10 +309,10 @@ system.physmem.readRowHitRate 82.04 # Ro
system.physmem.writeRowHitRate 74.97 # Row buffer hit rate for writes system.physmem.writeRowHitRate 74.97 # Row buffer hit rate for writes
system.physmem.avgGap 30177935.67 # Average gap between requests system.physmem.avgGap 30177935.67 # Average gap between requests
system.physmem.pageHitRate 78.98 # Row buffer hit rate, read and write combined system.physmem.pageHitRate 78.98 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 4939989046000 # Time in different power states system.physmem.memoryStateTime::IDLE 4939989054000 # Time in different power states
system.physmem.memoryStateTime::REF 171431260000 # Time in different power states system.physmem.memoryStateTime::REF 171431260000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 22454250000 # Time in different power states system.physmem.memoryStateTime::ACT 22454242000 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
system.membus.throughput 6437004 # Throughput (bytes/s) system.membus.throughput 6437004 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 422289 # Transaction distribution system.membus.trans_dist::ReadReq 422289 # Transaction distribution
@ -1045,9 +1045,9 @@ system.cpu0.kern.inst.arm 0 # nu
system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu0.icache.tags.replacements 850385 # number of replacements system.cpu0.icache.tags.replacements 850385 # number of replacements
system.cpu0.icache.tags.tagsinuse 510.795763 # Cycle average of tags in use system.cpu0.icache.tags.tagsinuse 510.795763 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 129494150 # Total number of references to valid blocks. system.cpu0.icache.tags.total_refs 129494152 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 850897 # Sample count of references to valid blocks. system.cpu0.icache.tags.sampled_refs 850897 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 152.185458 # Average number of references to valid blocks. system.cpu0.icache.tags.avg_refs 152.185461 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 147465545000 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.warmup_cycle 147465545000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 306.120317 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_blocks::cpu0.inst 306.120317 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 137.033154 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_blocks::cpu1.inst 137.033154 # Average occupied blocks per requestor
@ -1061,20 +1061,20 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::0 101
system.cpu0.icache.tags.age_task_id_blocks_1024::1 183 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 183 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 228 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 228 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 131214877 # Number of tag accesses system.cpu0.icache.tags.tag_accesses 131214879 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 131214877 # Number of data accesses system.cpu0.icache.tags.data_accesses 131214879 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 88330268 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::cpu0.inst 88330268 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 38415628 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::cpu1.inst 38415630 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst 2748254 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::cpu2.inst 2748254 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 129494150 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 129494152 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 88330268 # number of demand (read+write) hits system.cpu0.icache.demand_hits::cpu0.inst 88330268 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 38415628 # number of demand (read+write) hits system.cpu0.icache.demand_hits::cpu1.inst 38415630 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst 2748254 # number of demand (read+write) hits system.cpu0.icache.demand_hits::cpu2.inst 2748254 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 129494150 # number of demand (read+write) hits system.cpu0.icache.demand_hits::total 129494152 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 88330268 # number of overall hits system.cpu0.icache.overall_hits::cpu0.inst 88330268 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 38415628 # number of overall hits system.cpu0.icache.overall_hits::cpu1.inst 38415630 # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst 2748254 # number of overall hits system.cpu0.icache.overall_hits::cpu2.inst 2748254 # number of overall hits
system.cpu0.icache.overall_hits::total 129494150 # number of overall hits system.cpu0.icache.overall_hits::total 129494152 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 347417 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::cpu0.inst 347417 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 153575 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::cpu1.inst 153575 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst 368828 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::cpu2.inst 368828 # number of ReadReq misses
@ -1097,17 +1097,17 @@ system.cpu0.icache.overall_miss_latency::cpu1.inst 2140572500
system.cpu0.icache.overall_miss_latency::cpu2.inst 5126974995 # number of overall miss cycles system.cpu0.icache.overall_miss_latency::cpu2.inst 5126974995 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 7267547495 # number of overall miss cycles system.cpu0.icache.overall_miss_latency::total 7267547495 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 88677685 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::cpu0.inst 88677685 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 38569203 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::cpu1.inst 38569205 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst 3117082 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::cpu2.inst 3117082 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 130363970 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 130363972 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 88677685 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::cpu0.inst 88677685 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 38569203 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::cpu1.inst 38569205 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst 3117082 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::cpu2.inst 3117082 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 130363970 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::total 130363972 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 88677685 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::cpu0.inst 88677685 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 38569203 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::cpu1.inst 38569205 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst 3117082 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::cpu2.inst 3117082 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 130363970 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 130363972 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003918 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003918 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.003982 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.003982 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.118325 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.118325 # miss rate for ReadReq accesses
@ -1182,9 +1182,9 @@ system.cpu0.icache.overall_avg_mshr_miss_latency::total 12079.025728
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements 1632172 # number of replacements system.cpu0.dcache.tags.replacements 1632172 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.999414 # Cycle average of tags in use system.cpu0.dcache.tags.tagsinuse 511.999414 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 19616448 # Total number of references to valid blocks. system.cpu0.dcache.tags.total_refs 19616450 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 1632684 # Sample count of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 1632684 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 12.014847 # Average number of references to valid blocks. system.cpu0.dcache.tags.avg_refs 12.014848 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 243.807235 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_blocks::cpu0.data 243.807235 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 263.156885 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_blocks::cpu1.data 263.156885 # Average occupied blocks per requestor
@ -1198,24 +1198,24 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 184
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 88185531 # Number of tag accesses system.cpu0.dcache.tags.tag_accesses 88185539 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 88185531 # Number of data accesses system.cpu0.dcache.tags.data_accesses 88185539 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 5216887 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu0.data 5216887 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 2373281 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu1.data 2373282 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data 3941483 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu2.data 3941483 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 11531651 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 11531652 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 3654093 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 3654093 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 1632237 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::cpu1.data 1632238 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data 2796808 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::cpu2.data 2796808 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 8083138 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::total 8083139 # number of WriteReq hits
system.cpu0.dcache.demand_hits::cpu0.data 8870980 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::cpu0.data 8870980 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 4005518 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::cpu1.data 4005520 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data 6738291 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::cpu2.data 6738291 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 19614789 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::total 19614791 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 8870980 # number of overall hits system.cpu0.dcache.overall_hits::cpu0.data 8870980 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 4005518 # number of overall hits system.cpu0.dcache.overall_hits::cpu1.data 4005520 # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data 6738291 # number of overall hits system.cpu0.dcache.overall_hits::cpu2.data 6738291 # number of overall hits
system.cpu0.dcache.overall_hits::total 19614789 # number of overall hits system.cpu0.dcache.overall_hits::total 19614791 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 535895 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::cpu0.data 535895 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 223619 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::cpu1.data 223619 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data 948939 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::cpu2.data 948939 # number of ReadReq misses
@ -1245,21 +1245,21 @@ system.cpu0.dcache.overall_miss_latency::cpu1.data 5349158328
system.cpu0.dcache.overall_miss_latency::cpu2.data 18666142786 # number of overall miss cycles system.cpu0.dcache.overall_miss_latency::cpu2.data 18666142786 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 24015301114 # number of overall miss cycles system.cpu0.dcache.overall_miss_latency::total 24015301114 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 5752782 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::cpu0.data 5752782 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 2596900 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::cpu1.data 2596901 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data 4890422 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::cpu2.data 4890422 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 13240104 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 13240105 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 3798594 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 3798594 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 1694395 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu1.data 1694396 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data 2905116 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu2.data 2905116 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 8398105 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 8398106 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 9551376 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::cpu0.data 9551376 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 4291295 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::cpu1.data 4291297 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data 7795538 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::cpu2.data 7795538 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 21638209 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::total 21638211 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 9551376 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::cpu0.data 9551376 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 4291295 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::cpu1.data 4291297 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data 7795538 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::cpu2.data 7795538 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 21638209 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 21638211 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.093154 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.093154 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.086110 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.086110 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.194040 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.194040 # miss rate for ReadReq accesses
@ -1376,30 +1376,30 @@ system.cpu0.dcache.no_allocate_misses 0 # Nu
system.cpu1.numCycles 2606021866 # number of cpu cycles simulated system.cpu1.numCycles 2606021866 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 34914128 # Number of instructions committed system.cpu1.committedInsts 34914129 # Number of instructions committed
system.cpu1.committedOps 67869824 # Number of ops (including micro ops) committed system.cpu1.committedOps 67869828 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 62995293 # Number of integer alu accesses system.cpu1.num_int_alu_accesses 62995297 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu1.num_func_calls 438942 # number of times a function call or return occured system.cpu1.num_func_calls 438942 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 6428622 # number of instructions that are conditional controls system.cpu1.num_conditional_control_insts 6428622 # number of instructions that are conditional controls
system.cpu1.num_int_insts 62995293 # number of integer instructions system.cpu1.num_int_insts 62995297 # number of integer instructions
system.cpu1.num_fp_insts 0 # number of float instructions system.cpu1.num_fp_insts 0 # number of float instructions
system.cpu1.num_int_register_reads 116271698 # number of times the integer registers were read system.cpu1.num_int_register_reads 116271710 # number of times the integer registers were read
system.cpu1.num_int_register_writes 54373004 # number of times the integer registers were written system.cpu1.num_int_register_writes 54373007 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu1.num_cc_register_reads 35773637 # number of times the CC registers were read system.cpu1.num_cc_register_reads 35773638 # number of times the CC registers were read
system.cpu1.num_cc_register_writes 26686134 # number of times the CC registers were written system.cpu1.num_cc_register_writes 26686136 # number of times the CC registers were written
system.cpu1.num_mem_refs 4480510 # number of memory refs system.cpu1.num_mem_refs 4480512 # number of memory refs
system.cpu1.num_load_insts 2784988 # Number of load instructions system.cpu1.num_load_insts 2784989 # Number of load instructions
system.cpu1.num_store_insts 1695522 # Number of store instructions system.cpu1.num_store_insts 1695523 # Number of store instructions
system.cpu1.num_idle_cycles 2483027078.364504 # Number of idle cycles system.cpu1.num_idle_cycles 2483027076.334052 # Number of idle cycles
system.cpu1.num_busy_cycles 122994787.635496 # Number of busy cycles system.cpu1.num_busy_cycles 122994789.665948 # Number of busy cycles
system.cpu1.not_idle_fraction 0.047196 # Percentage of non-idle cycles system.cpu1.not_idle_fraction 0.047196 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.952804 # Percentage of idle cycles system.cpu1.idle_fraction 0.952804 # Percentage of idle cycles
system.cpu1.Branches 7029914 # Number of branches fetched system.cpu1.Branches 7029914 # Number of branches fetched
system.cpu1.op_class::No_OpClass 31008 0.05% 0.05% # Class of executed instruction system.cpu1.op_class::No_OpClass 31008 0.05% 0.05% # Class of executed instruction
system.cpu1.op_class::IntAlu 63308001 93.28% 93.32% # Class of executed instruction system.cpu1.op_class::IntAlu 63308003 93.28% 93.32% # Class of executed instruction
system.cpu1.op_class::IntMult 28040 0.04% 93.37% # Class of executed instruction system.cpu1.op_class::IntMult 28040 0.04% 93.37% # Class of executed instruction
system.cpu1.op_class::IntDiv 22580 0.03% 93.40% # Class of executed instruction system.cpu1.op_class::IntDiv 22580 0.03% 93.40% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 93.40% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 93.40% # Class of executed instruction
@ -1428,11 +1428,11 @@ system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.40% # Cl
system.cpu1.op_class::SimdFloatMult 0 0.00% 93.40% # Class of executed instruction system.cpu1.op_class::SimdFloatMult 0 0.00% 93.40% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.40% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.40% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.40% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.40% # Class of executed instruction
system.cpu1.op_class::MemRead 2784988 4.10% 97.50% # Class of executed instruction system.cpu1.op_class::MemRead 2784989 4.10% 97.50% # Class of executed instruction
system.cpu1.op_class::MemWrite 1695522 2.50% 100.00% # Class of executed instruction system.cpu1.op_class::MemWrite 1695523 2.50% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::total 67870139 # Class of executed instruction system.cpu1.op_class::total 67870143 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu2.branchPred.lookups 28758894 # Number of BP lookups system.cpu2.branchPred.lookups 28758894 # Number of BP lookups

2
tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal
View file

@ -44,7 +44,7 @@ ACPI: Core revision 20070126
ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126] ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
ACPI: Unable to load the System Description Tables ACPI: Unable to load the System Description Tables
Using local APIC timer interrupts. Using local APIC timer interrupts.
result 7812463 result 7812444
Detected 7.812 MHz APIC timer. Detected 7.812 MHz APIC timer.
NET: Registered protocol family 16 NET: Registered protocol family 16
PCI: Using configuration type 1 PCI: Using configuration type 1

52
tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
View file

@ -1,7 +1,9 @@
[root] [root]
type=Root type=Root
children=system children=system
eventq_index=0
full_system=true full_system=true
sim_quantum=0
time_sync_enable=false time_sync_enable=false
time_sync_period=200000000 time_sync_period=200000000
time_sync_spin_threshold=200000 time_sync_spin_threshold=200000
@ -12,6 +14,7 @@ children=bridge clk_domain cpu cpu_clk_domain disk0 hypervisor_desc intrctrl iob
boot_osflags=a boot_osflags=a
cache_line_size=64 cache_line_size=64
clk_domain=system.clk_domain clk_domain=system.clk_domain
eventq_index=0
hypervisor_addr=1099243257856 hypervisor_addr=1099243257856
hypervisor_bin=/dist/m5/system/binaries/q_new.bin hypervisor_bin=/dist/m5/system/binaries/q_new.bin
hypervisor_desc=system.hypervisor_desc hypervisor_desc=system.hypervisor_desc
@ -20,9 +23,10 @@ hypervisor_desc_bin=/dist/m5/system/binaries/1up-hv.bin
init_param=0 init_param=0
kernel= kernel=
load_addr_mask=1099511627775 load_addr_mask=1099511627775
load_offset=0
mem_mode=atomic mem_mode=atomic
mem_ranges=1048576:68157439 2147483648:2415919103 mem_ranges=1048576:68157439 2147483648:2415919103
memories=system.rom system.physmem1 system.hypervisor_desc system.physmem0 system.nvram system.partition_desc memories=system.nvram system.rom system.hypervisor_desc system.physmem0 system.physmem1 system.partition_desc
num_work_ids=16 num_work_ids=16
nvram=system.nvram nvram=system.nvram
nvram_addr=133429198848 nvram_addr=133429198848
@ -32,7 +36,7 @@ openboot_bin=/dist/m5/system/binaries/openboot_new.bin
partition_desc=system.partition_desc partition_desc=system.partition_desc
partition_desc_addr=133445976064 partition_desc_addr=133445976064
partition_desc_bin=/dist/m5/system/binaries/1up-md.bin partition_desc_bin=/dist/m5/system/binaries/1up-md.bin
readfile=tests/halt.sh readfile=/z/stever/hg/gem5/tests/halt.sh
reset_addr=1099243192320 reset_addr=1099243192320
reset_bin=/dist/m5/system/binaries/reset_new.bin reset_bin=/dist/m5/system/binaries/reset_new.bin
rom=system.rom rom=system.rom
@ -50,6 +54,7 @@ system_port=system.membus.slave[0]
type=Bridge type=Bridge
clk_domain=system.clk_domain clk_domain=system.clk_domain
delay=100 delay=100
eventq_index=0
ranges=133412421632:133412421639 134217728000:554050781183 644245094400:652835028991 725849473024:1095485095935 1099255955456:1099255955463 ranges=133412421632:133412421639 134217728000:554050781183 644245094400:652835028991 725849473024:1095485095935 1099255955456:1099255955463
req_size=16 req_size=16
resp_size=16 resp_size=16
@ -59,11 +64,13 @@ slave=system.membus.master[2]
[system.clk_domain] [system.clk_domain]
type=SrcClockDomain type=SrcClockDomain
clock=2 clock=2
eventq_index=0
voltage_domain=system.voltage_domain voltage_domain=system.voltage_domain
[system.cpu] [system.cpu]
type=AtomicSimpleCPU type=AtomicSimpleCPU
children=dtb interrupts isa itb tracer children=dtb interrupts isa itb tracer
branchPred=Null
checker=Null checker=Null
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
cpu_id=0 cpu_id=0
@ -71,6 +78,7 @@ do_checkpoint_insts=true
do_quiesce=true do_quiesce=true
do_statistics_insts=true do_statistics_insts=true
dtb=system.cpu.dtb dtb=system.cpu.dtb
eventq_index=0
fastmem=false fastmem=false
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
@ -90,6 +98,7 @@ simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts= simpoint_start_insts=
simulate_data_stalls=false simulate_data_stalls=false
simulate_inst_stalls=false simulate_inst_stalls=false
socket_id=0
switched_out=false switched_out=false
system=system system=system
tracer=system.cpu.tracer tracer=system.cpu.tracer
@ -100,30 +109,37 @@ icache_port=system.membus.slave[1]
[system.cpu.dtb] [system.cpu.dtb]
type=SparcTLB type=SparcTLB
eventq_index=0
size=64 size=64
[system.cpu.interrupts] [system.cpu.interrupts]
type=SparcInterrupts type=SparcInterrupts
eventq_index=0
[system.cpu.isa] [system.cpu.isa]
type=SparcISA type=SparcISA
eventq_index=0
[system.cpu.itb] [system.cpu.itb]
type=SparcTLB type=SparcTLB
eventq_index=0
size=64 size=64
[system.cpu.tracer] [system.cpu.tracer]
type=ExeTracer type=ExeTracer
eventq_index=0
[system.cpu_clk_domain] [system.cpu_clk_domain]
type=SrcClockDomain type=SrcClockDomain
clock=2 clock=2
eventq_index=0
voltage_domain=system.voltage_domain voltage_domain=system.voltage_domain
[system.disk0] [system.disk0]
type=MmDisk type=MmDisk
children=image children=image
clk_domain=system.clk_domain clk_domain=system.clk_domain
eventq_index=0
image=system.disk0.image image=system.disk0.image
pio_addr=134217728000 pio_addr=134217728000
pio_latency=200 pio_latency=200
@ -134,12 +150,14 @@ pio=system.iobus.master[14]
type=CowDiskImage type=CowDiskImage
children=child children=child
child=system.disk0.image.child child=system.disk0.image.child
eventq_index=0
image_file= image_file=
read_only=false read_only=false
table_size=65536 table_size=65536
[system.disk0.image.child] [system.disk0.image.child]
type=RawDiskImage type=RawDiskImage
eventq_index=0
image_file=/dist/m5/system/disks/disk.s10hw2 image_file=/dist/m5/system/disks/disk.s10hw2
read_only=true read_only=true
@ -148,6 +166,7 @@ type=SimpleMemory
bandwidth=0.000000 bandwidth=0.000000
clk_domain=system.clk_domain clk_domain=system.clk_domain
conf_table_reported=true conf_table_reported=true
eventq_index=0
in_addr_map=true in_addr_map=true
latency=60 latency=60
latency_var=0 latency_var=0
@ -157,11 +176,13 @@ port=system.membus.master[5]
[system.intrctrl] [system.intrctrl]
type=IntrControl type=IntrControl
eventq_index=0
sys=system sys=system
[system.iobus] [system.iobus]
type=NoncoherentBus type=NoncoherentBus
clk_domain=system.clk_domain clk_domain=system.clk_domain
eventq_index=0
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=8 width=8
@ -172,6 +193,7 @@ slave=system.bridge.master
type=CoherentBus type=CoherentBus
children=badaddr_responder children=badaddr_responder
clk_domain=system.clk_domain clk_domain=system.clk_domain
eventq_index=0
header_cycles=1 header_cycles=1
system=system system=system
use_default_range=false use_default_range=false
@ -183,6 +205,7 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.membus.badaddr_responder] [system.membus.badaddr_responder]
type=IsaFake type=IsaFake
clk_domain=system.clk_domain clk_domain=system.clk_domain
eventq_index=0
fake_mem=false fake_mem=false
pio_addr=0 pio_addr=0
pio_latency=200 pio_latency=200
@ -202,6 +225,7 @@ type=SimpleMemory
bandwidth=0.000000 bandwidth=0.000000
clk_domain=system.clk_domain clk_domain=system.clk_domain
conf_table_reported=true conf_table_reported=true
eventq_index=0
in_addr_map=true in_addr_map=true
latency=60 latency=60
latency_var=0 latency_var=0
@ -214,6 +238,7 @@ type=SimpleMemory
bandwidth=0.000000 bandwidth=0.000000
clk_domain=system.clk_domain clk_domain=system.clk_domain
conf_table_reported=true conf_table_reported=true
eventq_index=0
in_addr_map=true in_addr_map=true
latency=60 latency=60
latency_var=0 latency_var=0
@ -226,6 +251,7 @@ type=SimpleMemory
bandwidth=0.000000 bandwidth=0.000000
clk_domain=system.clk_domain clk_domain=system.clk_domain
conf_table_reported=true conf_table_reported=true
eventq_index=0
in_addr_map=true in_addr_map=true
latency=60 latency=60
latency_var=0 latency_var=0
@ -238,6 +264,7 @@ type=SimpleMemory
bandwidth=0.000000 bandwidth=0.000000
clk_domain=system.clk_domain clk_domain=system.clk_domain
conf_table_reported=true conf_table_reported=true
eventq_index=0
in_addr_map=true in_addr_map=true
latency=60 latency=60
latency_var=0 latency_var=0
@ -250,6 +277,7 @@ type=SimpleMemory
bandwidth=0.000000 bandwidth=0.000000
clk_domain=system.clk_domain clk_domain=system.clk_domain
conf_table_reported=true conf_table_reported=true
eventq_index=0
in_addr_map=true in_addr_map=true
latency=60 latency=60
latency_var=0 latency_var=0
@ -260,12 +288,14 @@ port=system.membus.master[3]
[system.t1000] [system.t1000]
type=T1000 type=T1000
children=fake_clk fake_jbi fake_l2_1 fake_l2_2 fake_l2_3 fake_l2_4 fake_l2esr_1 fake_l2esr_2 fake_l2esr_3 fake_l2esr_4 fake_membnks fake_ssi hterm htod hvuart iob pterm puart0 children=fake_clk fake_jbi fake_l2_1 fake_l2_2 fake_l2_3 fake_l2_4 fake_l2esr_1 fake_l2esr_2 fake_l2esr_3 fake_l2esr_4 fake_membnks fake_ssi hterm htod hvuart iob pterm puart0
eventq_index=0
intrctrl=system.intrctrl intrctrl=system.intrctrl
system=system system=system
[system.t1000.fake_clk] [system.t1000.fake_clk]
type=IsaFake type=IsaFake
clk_domain=system.clk_domain clk_domain=system.clk_domain
eventq_index=0
fake_mem=false fake_mem=false
pio_addr=644245094400 pio_addr=644245094400
pio_latency=200 pio_latency=200
@ -283,6 +313,7 @@ pio=system.iobus.master[0]
[system.t1000.fake_jbi] [system.t1000.fake_jbi]
type=IsaFake type=IsaFake
clk_domain=system.clk_domain clk_domain=system.clk_domain
eventq_index=0
fake_mem=false fake_mem=false
pio_addr=549755813888 pio_addr=549755813888
pio_latency=200 pio_latency=200
@ -300,6 +331,7 @@ pio=system.iobus.master[11]
[system.t1000.fake_l2_1] [system.t1000.fake_l2_1]
type=IsaFake type=IsaFake
clk_domain=system.clk_domain clk_domain=system.clk_domain
eventq_index=0
fake_mem=false fake_mem=false
pio_addr=725849473024 pio_addr=725849473024
pio_latency=200 pio_latency=200
@ -317,6 +349,7 @@ pio=system.iobus.master[2]
[system.t1000.fake_l2_2] [system.t1000.fake_l2_2]
type=IsaFake type=IsaFake
clk_domain=system.clk_domain clk_domain=system.clk_domain
eventq_index=0
fake_mem=false fake_mem=false
pio_addr=725849473088 pio_addr=725849473088
pio_latency=200 pio_latency=200
@ -334,6 +367,7 @@ pio=system.iobus.master[3]
[system.t1000.fake_l2_3] [system.t1000.fake_l2_3]
type=IsaFake type=IsaFake
clk_domain=system.clk_domain clk_domain=system.clk_domain
eventq_index=0
fake_mem=false fake_mem=false
pio_addr=725849473152 pio_addr=725849473152
pio_latency=200 pio_latency=200
@ -351,6 +385,7 @@ pio=system.iobus.master[4]
[system.t1000.fake_l2_4] [system.t1000.fake_l2_4]
type=IsaFake type=IsaFake
clk_domain=system.clk_domain clk_domain=system.clk_domain
eventq_index=0
fake_mem=false fake_mem=false
pio_addr=725849473216 pio_addr=725849473216
pio_latency=200 pio_latency=200
@ -368,6 +403,7 @@ pio=system.iobus.master[5]
[system.t1000.fake_l2esr_1] [system.t1000.fake_l2esr_1]
type=IsaFake type=IsaFake
clk_domain=system.clk_domain clk_domain=system.clk_domain
eventq_index=0
fake_mem=false fake_mem=false
pio_addr=734439407616 pio_addr=734439407616
pio_latency=200 pio_latency=200
@ -385,6 +421,7 @@ pio=system.iobus.master[6]
[system.t1000.fake_l2esr_2] [system.t1000.fake_l2esr_2]
type=IsaFake type=IsaFake
clk_domain=system.clk_domain clk_domain=system.clk_domain
eventq_index=0
fake_mem=false fake_mem=false
pio_addr=734439407680 pio_addr=734439407680
pio_latency=200 pio_latency=200
@ -402,6 +439,7 @@ pio=system.iobus.master[7]
[system.t1000.fake_l2esr_3] [system.t1000.fake_l2esr_3]
type=IsaFake type=IsaFake
clk_domain=system.clk_domain clk_domain=system.clk_domain
eventq_index=0
fake_mem=false fake_mem=false
pio_addr=734439407744 pio_addr=734439407744
pio_latency=200 pio_latency=200
@ -419,6 +457,7 @@ pio=system.iobus.master[8]
[system.t1000.fake_l2esr_4] [system.t1000.fake_l2esr_4]
type=IsaFake type=IsaFake
clk_domain=system.clk_domain clk_domain=system.clk_domain
eventq_index=0
fake_mem=false fake_mem=false
pio_addr=734439407808 pio_addr=734439407808
pio_latency=200 pio_latency=200
@ -436,6 +475,7 @@ pio=system.iobus.master[9]
[system.t1000.fake_membnks] [system.t1000.fake_membnks]
type=IsaFake type=IsaFake
clk_domain=system.clk_domain clk_domain=system.clk_domain
eventq_index=0
fake_mem=false fake_mem=false
pio_addr=648540061696 pio_addr=648540061696
pio_latency=200 pio_latency=200
@ -453,6 +493,7 @@ pio=system.iobus.master[1]
[system.t1000.fake_ssi] [system.t1000.fake_ssi]
type=IsaFake type=IsaFake
clk_domain=system.clk_domain clk_domain=system.clk_domain
eventq_index=0
fake_mem=false fake_mem=false
pio_addr=1095216660480 pio_addr=1095216660480
pio_latency=200 pio_latency=200
@ -469,6 +510,7 @@ pio=system.iobus.master[10]
[system.t1000.hterm] [system.t1000.hterm]
type=Terminal type=Terminal
eventq_index=0
intr_control=system.intrctrl intr_control=system.intrctrl
number=0 number=0
output=true output=true
@ -477,6 +519,7 @@ port=3456
[system.t1000.htod] [system.t1000.htod]
type=DumbTOD type=DumbTOD
clk_domain=system.clk_domain clk_domain=system.clk_domain
eventq_index=0
pio_addr=1099255906296 pio_addr=1099255906296
pio_latency=200 pio_latency=200
system=system system=system
@ -486,6 +529,7 @@ pio=system.membus.master[1]
[system.t1000.hvuart] [system.t1000.hvuart]
type=Uart8250 type=Uart8250
clk_domain=system.clk_domain clk_domain=system.clk_domain
eventq_index=0
pio_addr=1099255955456 pio_addr=1099255955456
pio_latency=200 pio_latency=200
platform=system.t1000 platform=system.t1000
@ -496,6 +540,7 @@ pio=system.iobus.master[13]
[system.t1000.iob] [system.t1000.iob]
type=Iob type=Iob
clk_domain=system.clk_domain clk_domain=system.clk_domain
eventq_index=0
pio_latency=2 pio_latency=2
platform=system.t1000 platform=system.t1000
system=system system=system
@ -503,6 +548,7 @@ pio=system.membus.master[0]
[system.t1000.pterm] [system.t1000.pterm]
type=Terminal type=Terminal
eventq_index=0
intr_control=system.intrctrl intr_control=system.intrctrl
number=0 number=0
output=true output=true
@ -511,6 +557,7 @@ port=3456
[system.t1000.puart0] [system.t1000.puart0]
type=Uart8250 type=Uart8250
clk_domain=system.clk_domain clk_domain=system.clk_domain
eventq_index=0
pio_addr=133412421632 pio_addr=133412421632
pio_latency=200 pio_latency=200
platform=system.t1000 platform=system.t1000
@ -520,5 +567,6 @@ pio=system.iobus.master[12]
[system.voltage_domain] [system.voltage_domain]
type=VoltageDomain type=VoltageDomain
eventq_index=0
voltage=1.000000 voltage=1.000000

717
tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json Normal file
View file

@ -0,0 +1,717 @@
{
"name": null,
"sim_quantum": 0,
"system": {
"bridge": {
"slave": {
"peer": "system.membus.master[2]",
"role": "SLAVE"
},
"name": "bridge",
"req_size": 16,
"delay": 5.0000000000000004e-08,
"eventq_index": 0,
"master": {
"peer": "system.iobus.slave[0]",
"role": "MASTER"
},
"cxx_class": "Bridge",
"path": "system.bridge",
"resp_size": 16,
"type": "Bridge"
},
"iobus": {
"slave": {
"peer": [
"system.bridge.master"
],
"role": "SLAVE"
},
"name": "iobus",
"header_cycles": 1,
"width": 8,
"eventq_index": 0,
"master": {
"peer": [
"system.t1000.fake_clk.pio",
"system.t1000.fake_membnks.pio",
"system.t1000.fake_l2_1.pio",
"system.t1000.fake_l2_2.pio",
"system.t1000.fake_l2_3.pio",
"system.t1000.fake_l2_4.pio",
"system.t1000.fake_l2esr_1.pio",
"system.t1000.fake_l2esr_2.pio",
"system.t1000.fake_l2esr_3.pio",
"system.t1000.fake_l2esr_4.pio",
"system.t1000.fake_ssi.pio",
"system.t1000.fake_jbi.pio",
"system.t1000.puart0.pio",
"system.t1000.hvuart.pio",
"system.disk0.pio"
],
"role": "MASTER"
},
"cxx_class": "NoncoherentBus",
"path": "system.iobus",
"type": "NoncoherentBus",
"use_default_range": false
},
"rom": {
"latency": 3.0000000000000004e-08,
"name": "rom",
"eventq_index": 0,
"latency_var": 0.0,
"conf_table_reported": true,
"cxx_class": "SimpleMemory",
"path": "system.rom",
"null": false,
"type": "SimpleMemory",
"port": {
"peer": "system.membus.master[3]",
"role": "SLAVE"
},
"in_addr_map": true
},
"membus": {
"slave": {
"peer": [
"system.system_port",
"system.cpu.icache_port",
"system.cpu.dcache_port"
],
"role": "SLAVE"
},
"name": "membus",
"badaddr_responder": {
"ret_data8": 255,
"name": "badaddr_responder",
"pio": {
"peer": "system.membus.default",
"role": "SLAVE"
},
"ret_bad_addr": true,
"pio_latency": 1.0000000000000001e-07,
"fake_mem": false,
"pio_size": 8,
"ret_data32": 4294967295,
"eventq_index": 0,
"update_data": false,
"ret_data64": 18446744073709551615,
"cxx_class": "IsaFake",
"path": "system.membus.badaddr_responder",
"pio_addr": 0,
"type": "IsaFake",
"ret_data16": 65535
},
"default": {
"peer": "system.membus.badaddr_responder.pio",
"role": "MASTER"
},
"header_cycles": 1,
"width": 8,
"eventq_index": 0,
"master": {
"peer": [
"system.t1000.iob.pio",
"system.t1000.htod.pio",
"system.bridge.slave",
"system.rom.port",
"system.nvram.port",
"system.hypervisor_desc.port",
"system.partition_desc.port",
"system.physmem0.port",
"system.physmem1.port"
],
"role": "MASTER"
},
"cxx_class": "CoherentBus",
"path": "system.membus",
"type": "CoherentBus",
"use_default_range": false
},
"t1000": {
"htod": {
"name": "htod",
"pio": {
"peer": "system.membus.master[1]",
"role": "SLAVE"
},
"time": "Thu Jan 1 00:00:00 2009",
"pio_latency": 1.0000000000000001e-07,
"eventq_index": 0,
"cxx_class": "DumbTOD",
"path": "system.t1000.htod",
"pio_addr": 1099255906296,
"type": "DumbTOD"
},
"puart0": {
"name": "puart0",
"pio": {
"peer": "system.iobus.master[12]",
"role": "SLAVE"
},
"pio_latency": 1.0000000000000001e-07,
"eventq_index": 0,
"cxx_class": "Uart8250",
"path": "system.t1000.puart0",
"pio_addr": 133412421632,
"type": "Uart8250"
},
"fake_membnks": {
"ret_data8": 255,
"name": "fake_membnks",
"pio": {
"peer": "system.iobus.master[1]",
"role": "SLAVE"
},
"ret_bad_addr": false,
"pio_latency": 1.0000000000000001e-07,
"fake_mem": false,
"pio_size": 16384,
"ret_data32": 4294967295,
"eventq_index": 0,
"update_data": false,
"ret_data64": 0,
"cxx_class": "IsaFake",
"path": "system.t1000.fake_membnks",
"pio_addr": 648540061696,
"type": "IsaFake",
"ret_data16": 65535
},
"cxx_class": "T1000",
"fake_jbi": {
"ret_data8": 255,
"name": "fake_jbi",
"pio": {
"peer": "system.iobus.master[11]",
"role": "SLAVE"
},
"ret_bad_addr": false,
"pio_latency": 1.0000000000000001e-07,
"fake_mem": false,
"pio_size": 4294967296,
"ret_data32": 4294967295,
"eventq_index": 0,
"update_data": false,
"ret_data64": 18446744073709551615,
"cxx_class": "IsaFake",
"path": "system.t1000.fake_jbi",
"pio_addr": 549755813888,
"type": "IsaFake",
"ret_data16": 65535
},
"fake_l2esr_2": {
"ret_data8": 255,
"name": "fake_l2esr_2",
"pio": {
"peer": "system.iobus.master[7]",
"role": "SLAVE"
},
"ret_bad_addr": false,
"pio_latency": 1.0000000000000001e-07,
"fake_mem": false,
"pio_size": 8,
"ret_data32": 4294967295,
"eventq_index": 0,
"update_data": true,
"ret_data64": 0,
"cxx_class": "IsaFake",
"path": "system.t1000.fake_l2esr_2",
"pio_addr": 734439407680,
"type": "IsaFake",
"ret_data16": 65535
},
"eventq_index": 0,
"hterm": {
"name": "hterm",
"output": true,
"number": 0,
"eventq_index": 0,
"cxx_class": "Terminal",
"path": "system.t1000.hterm",
"type": "Terminal",
"port": 3456
},
"type": "T1000",
"fake_l2_4": {
"ret_data8": 255,
"name": "fake_l2_4",
"pio": {
"peer": "system.iobus.master[5]",
"role": "SLAVE"
},
"ret_bad_addr": false,
"pio_latency": 1.0000000000000001e-07,
"fake_mem": false,
"pio_size": 8,
"ret_data32": 4294967295,
"eventq_index": 0,
"update_data": true,
"ret_data64": 1,
"cxx_class": "IsaFake",
"path": "system.t1000.fake_l2_4",
"pio_addr": 725849473216,
"type": "IsaFake",
"ret_data16": 65535
},
"fake_l2_1": {
"ret_data8": 255,
"name": "fake_l2_1",
"pio": {
"peer": "system.iobus.master[2]",
"role": "SLAVE"
},
"ret_bad_addr": false,
"pio_latency": 1.0000000000000001e-07,
"fake_mem": false,
"pio_size": 8,
"ret_data32": 4294967295,
"eventq_index": 0,
"update_data": true,
"ret_data64": 1,
"cxx_class": "IsaFake",
"path": "system.t1000.fake_l2_1",
"pio_addr": 725849473024,
"type": "IsaFake",
"ret_data16": 65535
},
"fake_l2_2": {
"ret_data8": 255,
"name": "fake_l2_2",
"pio": {
"peer": "system.iobus.master[3]",
"role": "SLAVE"
},
"ret_bad_addr": false,
"pio_latency": 1.0000000000000001e-07,
"fake_mem": false,
"pio_size": 8,
"ret_data32": 4294967295,
"eventq_index": 0,
"update_data": true,
"ret_data64": 1,
"cxx_class": "IsaFake",
"path": "system.t1000.fake_l2_2",
"pio_addr": 725849473088,
"type": "IsaFake",
"ret_data16": 65535
},
"fake_l2_3": {
"ret_data8": 255,
"name": "fake_l2_3",
"pio": {
"peer": "system.iobus.master[4]",
"role": "SLAVE"
},
"ret_bad_addr": false,
"pio_latency": 1.0000000000000001e-07,
"fake_mem": false,
"pio_size": 8,
"ret_data32": 4294967295,
"eventq_index": 0,
"update_data": true,
"ret_data64": 1,
"cxx_class": "IsaFake",
"path": "system.t1000.fake_l2_3",
"pio_addr": 725849473152,
"type": "IsaFake",
"ret_data16": 65535
},
"pterm": {
"name": "pterm",
"output": true,
"number": 0,
"eventq_index": 0,
"cxx_class": "Terminal",
"path": "system.t1000.pterm",
"type": "Terminal",
"port": 3456
},
"path": "system.t1000",
"iob": {
"name": "iob",
"pio": {
"peer": "system.membus.master[0]",
"role": "SLAVE"
},
"pio_latency": 1e-09,
"eventq_index": 0,
"cxx_class": "Iob",
"path": "system.t1000.iob",
"type": "Iob"
},
"hvuart": {
"name": "hvuart",
"pio": {
"peer": "system.iobus.master[13]",
"role": "SLAVE"
},
"pio_latency": 1.0000000000000001e-07,
"eventq_index": 0,
"cxx_class": "Uart8250",
"path": "system.t1000.hvuart",
"pio_addr": 1099255955456,
"type": "Uart8250"
},
"name": "t1000",
"fake_l2esr_3": {
"ret_data8": 255,
"name": "fake_l2esr_3",
"pio": {
"peer": "system.iobus.master[8]",
"role": "SLAVE"
},
"ret_bad_addr": false,
"pio_latency": 1.0000000000000001e-07,
"fake_mem": false,
"pio_size": 8,
"ret_data32": 4294967295,
"eventq_index": 0,
"update_data": true,
"ret_data64": 0,
"cxx_class": "IsaFake",
"path": "system.t1000.fake_l2esr_3",
"pio_addr": 734439407744,
"type": "IsaFake",
"ret_data16": 65535
},
"fake_ssi": {
"ret_data8": 255,
"name": "fake_ssi",
"pio": {
"peer": "system.iobus.master[10]",
"role": "SLAVE"
},
"ret_bad_addr": false,
"pio_latency": 1.0000000000000001e-07,
"fake_mem": false,
"pio_size": 268435456,
"ret_data32": 4294967295,
"eventq_index": 0,
"update_data": false,
"ret_data64": 18446744073709551615,
"cxx_class": "IsaFake",
"path": "system.t1000.fake_ssi",
"pio_addr": 1095216660480,
"type": "IsaFake",
"ret_data16": 65535
},
"fake_l2esr_1": {
"ret_data8": 255,
"name": "fake_l2esr_1",
"pio": {
"peer": "system.iobus.master[6]",
"role": "SLAVE"
},
"ret_bad_addr": false,
"pio_latency": 1.0000000000000001e-07,
"fake_mem": false,
"pio_size": 8,
"ret_data32": 4294967295,
"eventq_index": 0,
"update_data": true,
"ret_data64": 0,
"cxx_class": "IsaFake",
"path": "system.t1000.fake_l2esr_1",
"pio_addr": 734439407616,
"type": "IsaFake",
"ret_data16": 65535
},
"fake_l2esr_4": {
"ret_data8": 255,
"name": "fake_l2esr_4",
"pio": {
"peer": "system.iobus.master[9]",
"role": "SLAVE"
},
"ret_bad_addr": false,
"pio_latency": 1.0000000000000001e-07,
"fake_mem": false,
"pio_size": 8,
"ret_data32": 4294967295,
"eventq_index": 0,
"update_data": true,
"ret_data64": 0,
"cxx_class": "IsaFake",
"path": "system.t1000.fake_l2esr_4",
"pio_addr": 734439407808,
"type": "IsaFake",
"ret_data16": 65535
},
"fake_clk": {
"ret_data8": 255,
"name": "fake_clk",
"pio": {
"peer": "system.iobus.master[0]",
"role": "SLAVE"
},
"ret_bad_addr": false,
"pio_latency": 1.0000000000000001e-07,
"fake_mem": false,
"pio_size": 4294967296,
"ret_data32": 4294967295,
"eventq_index": 0,
"update_data": false,
"ret_data64": 18446744073709551615,
"cxx_class": "IsaFake",
"path": "system.t1000.fake_clk",
"pio_addr": 644245094400,
"type": "IsaFake",
"ret_data16": 65535
}
},
"partition_desc_addr": 133445976064,
"physmem": [
{
"latency": 3.0000000000000004e-08,
"name": "physmem0",
"eventq_index": 0,
"latency_var": 0.0,
"conf_table_reported": true,
"cxx_class": "SimpleMemory",
"path": "system.physmem0",
"null": false,
"type": "SimpleMemory",
"port": {
"peer": "system.membus.master[7]",
"role": "SLAVE"
},
"in_addr_map": true
},
{
"latency": 3.0000000000000004e-08,
"name": "physmem1",
"eventq_index": 0,
"latency_var": 0.0,
"conf_table_reported": true,
"cxx_class": "SimpleMemory",
"path": "system.physmem1",
"null": false,
"type": "SimpleMemory",
"port": {
"peer": "system.membus.master[8]",
"role": "SLAVE"
},
"in_addr_map": true
}
],
"hypervisor_addr": 1099243257856,
"cxx_class": "SparcSystem",
"load_offset": 0,
"openboot_addr": 1099243716608,
"work_end_ckpt_count": 0,
"nvram_addr": 133429198848,
"work_begin_ckpt_count": 0,
"partition_desc": {
"latency": 3.0000000000000004e-08,
"name": "partition_desc",
"eventq_index": 0,
"latency_var": 0.0,
"conf_table_reported": true,
"cxx_class": "SimpleMemory",
"path": "system.partition_desc",
"null": false,
"type": "SimpleMemory",
"port": {
"peer": "system.membus.master[6]",
"role": "SLAVE"
},
"in_addr_map": true
},
"clk_domain": {
"name": "clk_domain",
"clock": 1e-09,
"eventq_index": 0,
"cxx_class": "SrcClockDomain",
"path": "system.clk_domain",
"type": "SrcClockDomain"
},
"hypervisor_desc": {
"latency": 3.0000000000000004e-08,
"name": "hypervisor_desc",
"eventq_index": 0,
"latency_var": 0.0,
"conf_table_reported": true,
"cxx_class": "SimpleMemory",
"path": "system.hypervisor_desc",
"null": false,
"type": "SimpleMemory",
"port": {
"peer": "system.membus.master[5]",
"role": "SLAVE"
},
"in_addr_map": true
},
"nvram": {
"latency": 3.0000000000000004e-08,
"name": "nvram",
"eventq_index": 0,
"latency_var": 0.0,
"conf_table_reported": true,
"cxx_class": "SimpleMemory",
"path": "system.nvram",
"null": false,
"type": "SimpleMemory",
"port": {
"peer": "system.membus.master[4]",
"role": "SLAVE"
},
"in_addr_map": true
},
"eventq_index": 0,
"work_end_exit_count": 0,
"type": "SparcSystem",
"voltage_domain": {
"eventq_index": 0,
"path": "system.voltage_domain",
"type": "VoltageDomain",
"name": "voltage_domain",
"cxx_class": "VoltageDomain"
},
"cache_line_size": 64,
"work_cpus_ckpt_count": 0,
"work_begin_exit_count": 0,
"num_work_ids": 16,
"path": "system",
"cpu_clk_domain": {
"name": "cpu_clk_domain",
"clock": 1e-09,
"eventq_index": 0,
"cxx_class": "SrcClockDomain",
"path": "system.cpu_clk_domain",
"type": "SrcClockDomain"
},
"mem_mode": "atomic",
"name": "system",
"init_param": 0,
"system_port": {
"peer": "system.membus.slave[0]",
"role": "MASTER"
},
"load_addr_mask": 1099511627775,
"cpu": {
"simpoint_interval": 100000000,
"do_statistics_insts": true,
"numThreads": 1,
"itb": {
"name": "itb",
"eventq_index": 0,
"cxx_class": "SparcISA::TLB",
"path": "system.cpu.itb",
"type": "SparcTLB",
"size": 64
},
"function_trace": false,
"do_checkpoint_insts": true,
"cxx_class": "AtomicSimpleCPU",
"max_loads_all_threads": 0,
"simpoint_profile": false,
"simulate_data_stalls": false,
"function_trace_start": 0,
"cpu_id": 0,
"width": 1,
"eventq_index": 0,
"do_quiesce": true,
"type": "AtomicSimpleCPU",
"fastmem": false,
"profile": 0.0,
"icache_port": {
"peer": "system.membus.slave[1]",
"role": "MASTER"
},
"interrupts": {
"eventq_index": 0,
"path": "system.cpu.interrupts",
"type": "SparcInterrupts",
"name": "interrupts",
"cxx_class": "SparcISA::Interrupts"
},
"socket_id": 0,
"max_insts_all_threads": 0,
"path": "system.cpu",
"isa": [
{
"eventq_index": 0,
"path": "system.cpu.isa",
"type": "SparcISA",
"name": "isa",
"cxx_class": "SparcISA::ISA"
}
],
"switched_out": false,
"name": "cpu",
"dtb": {
"name": "dtb",
"eventq_index": 0,
"cxx_class": "SparcISA::TLB",
"path": "system.cpu.dtb",
"type": "SparcTLB",
"size": 64
},
"max_insts_any_thread": 0,
"simulate_inst_stalls": false,
"progress_interval": 0.0,
"dcache_port": {
"peer": "system.membus.slave[2]",
"role": "MASTER"
},
"max_loads_any_thread": 0,
"tracer": {
"eventq_index": 0,
"path": "system.cpu.tracer",
"type": "ExeTracer",
"name": "tracer",
"cxx_class": "Trace::ExeTracer"
}
},
"intrctrl": {
"eventq_index": 0,
"path": "system.intrctrl",
"type": "IntrControl",
"name": "intrctrl",
"cxx_class": "IntrControl"
},
"disk0": {
"name": "disk0",
"pio": {
"peer": "system.iobus.master[14]",
"role": "SLAVE"
},
"image": {
"read_only": false,
"name": "image",
"child": {
"read_only": true,
"name": "child",
"eventq_index": 0,
"cxx_class": "RawDiskImage",
"path": "system.disk0.image.child",
"type": "RawDiskImage"
},
"eventq_index": 0,
"cxx_class": "CowDiskImage",
"path": "system.disk0.image",
"table_size": 65536,
"type": "CowDiskImage"
},
"pio_latency": 1.0000000000000001e-07,
"eventq_index": 0,
"cxx_class": "MmDisk",
"path": "system.disk0",
"pio_addr": 134217728000,
"type": "MmDisk"
},
"hypervisor_desc_addr": 133446500352,
"reset_addr": 1099243192320,
"work_item_id": -1,
"work_begin_cpu_id_exit": -1
},
"time_sync_period": 0.1,
"eventq_index": 0,
"time_sync_spin_threshold": 9.999999999999999e-05,
"cxx_class": "Root",
"path": "root",
"time_sync_enable": false,
"type": "Root",
"full_system": true
}

2
tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr
View file

@ -23,7 +23,5 @@ warn: rounding error > tolerance
warn: rounding error > tolerance warn: rounding error > tolerance
0.145519 rounded to 0 0.145519 rounded to 0
warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting terminal connections
warn: CoherentBus system.membus has no snooping ports attached!
warn: Sockets disabled, not accepting gdb connections warn: Sockets disabled, not accepting gdb connections
warn: Don't know what interrupt to clear for console. warn: Don't know what interrupt to clear for console.
hack: be nice to actually delete the event here

8
tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
View file

@ -1,12 +1,10 @@
Redirecting stdout to build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic/simout
Redirecting stderr to build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic/simerr
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 22 2013 06:07:13 gem5 compiled May 12 2014 11:27:38
gem5 started Sep 22 2013 06:07:33 gem5 started May 12 2014 11:28:05
gem5 executing on zizzer gem5 executing on zizzer
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re tests/run.py build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re /z/stever/hg/gem5/tests/run.py build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic
Global frequency set at 2000000000 ticks per second Global frequency set at 2000000000 ticks per second
info: No kernel set for full system simulation. Assuming you know what you're doing info: No kernel set for full system simulation. Assuming you know what you're doing
0: system.t1000.htod: Real-time clock set to Thu Jan 1 00:00:00 2009 0: system.t1000.htod: Real-time clock set to Thu Jan 1 00:00:00 2009

109
tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 2.233778 # Nu
sim_ticks 4467555024 # Number of ticks simulated sim_ticks 4467555024 # Number of ticks simulated
final_tick 4467555024 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 4467555024 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 2000000000 # Frequency of simulated ticks sim_freq 2000000000 # Frequency of simulated ticks
host_inst_rate 1895600 # Simulator instruction rate (inst/s) host_inst_rate 2578014 # Simulator instruction rate (inst/s)
host_op_rate 1896345 # Simulator op (including micro ops) rate (op/s) host_op_rate 2579027 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 3800545 # Simulator tick rate (ticks/s) host_tick_rate 5168737 # Simulator tick rate (ticks/s)
host_mem_usage 576292 # Number of bytes of host memory used host_mem_usage 527944 # Number of bytes of host memory used
host_seconds 1175.50 # Real time elapsed on the host host_seconds 864.34 # Real time elapsed on the host
sim_insts 2228284650 # Number of instructions simulated sim_insts 2228284650 # Number of instructions simulated
sim_ops 2229160714 # Number of ops (including micro ops) simulated sim_ops 2229160714 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts system.voltage_domain.voltage 1 # Voltage in Volts
@ -35,38 +35,6 @@ system.nvram.bw_write::cpu.data 41 # Wr
system.nvram.bw_write::total 41 # Write bandwidth from this memory (bytes/s) system.nvram.bw_write::total 41 # Write bandwidth from this memory (bytes/s)
system.nvram.bw_total::cpu.data 168 # Total bandwidth to/from this memory (bytes/s) system.nvram.bw_total::cpu.data 168 # Total bandwidth to/from this memory (bytes/s)
system.nvram.bw_total::total 168 # Total bandwidth to/from this memory (bytes/s) system.nvram.bw_total::total 168 # Total bandwidth to/from this memory (bytes/s)
system.physmem1.bytes_read::cpu.inst 8318106840 # Number of bytes read from this memory
system.physmem1.bytes_read::cpu.data 1495885127 # Number of bytes read from this memory
system.physmem1.bytes_read::total 9813991967 # Number of bytes read from this memory
system.physmem1.bytes_inst_read::cpu.inst 8318106840 # Number of instructions bytes read from this memory
system.physmem1.bytes_inst_read::total 8318106840 # Number of instructions bytes read from this memory
system.physmem1.bytes_written::cpu.data 897268422 # Number of bytes written to this memory
system.physmem1.bytes_written::total 897268422 # Number of bytes written to this memory
system.physmem1.num_reads::cpu.inst 2079526710 # Number of read requests responded to by this memory
system.physmem1.num_reads::cpu.data 323962420 # Number of read requests responded to by this memory
system.physmem1.num_reads::total 2403489130 # Number of read requests responded to by this memory
system.physmem1.num_writes::cpu.data 187387796 # Number of write requests responded to by this memory
system.physmem1.num_writes::total 187387796 # Number of write requests responded to by this memory
system.physmem1.num_other::cpu.data 5403067 # Number of other requests responded to by this memory
system.physmem1.num_other::total 5403067 # Number of other requests responded to by this memory
system.physmem1.bw_read::cpu.inst 3723784842 # Total read bandwidth from this memory (bytes/s)
system.physmem1.bw_read::cpu.data 669666123 # Total read bandwidth from this memory (bytes/s)
system.physmem1.bw_read::total 4393450966 # Total read bandwidth from this memory (bytes/s)
system.physmem1.bw_inst_read::cpu.inst 3723784842 # Instruction read bandwidth from this memory (bytes/s)
system.physmem1.bw_inst_read::total 3723784842 # Instruction read bandwidth from this memory (bytes/s)
system.physmem1.bw_write::cpu.data 401682091 # Write bandwidth from this memory (bytes/s)
system.physmem1.bw_write::total 401682091 # Write bandwidth from this memory (bytes/s)
system.physmem1.bw_total::cpu.inst 3723784842 # Total bandwidth to/from this memory (bytes/s)
system.physmem1.bw_total::cpu.data 1071348214 # Total bandwidth to/from this memory (bytes/s)
system.physmem1.bw_total::total 4795133057 # Total bandwidth to/from this memory (bytes/s)
system.partition_desc.bytes_read::cpu.data 4846 # Number of bytes read from this memory
system.partition_desc.bytes_read::total 4846 # Number of bytes read from this memory
system.partition_desc.num_reads::cpu.data 608 # Number of read requests responded to by this memory
system.partition_desc.num_reads::total 608 # Number of read requests responded to by this memory
system.partition_desc.bw_read::cpu.data 2169 # Total read bandwidth from this memory (bytes/s)
system.partition_desc.bw_read::total 2169 # Total read bandwidth from this memory (bytes/s)
system.partition_desc.bw_total::cpu.data 2169 # Total bandwidth to/from this memory (bytes/s)
system.partition_desc.bw_total::total 2169 # Total bandwidth to/from this memory (bytes/s)
system.rom.bytes_read::cpu.inst 432296 # Number of bytes read from this memory system.rom.bytes_read::cpu.inst 432296 # Number of bytes read from this memory
system.rom.bytes_read::cpu.data 696392 # Number of bytes read from this memory system.rom.bytes_read::cpu.data 696392 # Number of bytes read from this memory
system.rom.bytes_read::total 1128688 # Number of bytes read from this memory system.rom.bytes_read::total 1128688 # Number of bytes read from this memory
@ -107,6 +75,38 @@ system.physmem0.bw_write::total 6894251 # Wr
system.physmem0.bw_total::cpu.inst 274105779 # Total bandwidth to/from this memory (bytes/s) system.physmem0.bw_total::cpu.inst 274105779 # Total bandwidth to/from this memory (bytes/s)
system.physmem0.bw_total::cpu.data 50557518 # Total bandwidth to/from this memory (bytes/s) system.physmem0.bw_total::cpu.data 50557518 # Total bandwidth to/from this memory (bytes/s)
system.physmem0.bw_total::total 324663297 # Total bandwidth to/from this memory (bytes/s) system.physmem0.bw_total::total 324663297 # Total bandwidth to/from this memory (bytes/s)
system.physmem1.bytes_read::cpu.inst 8318106840 # Number of bytes read from this memory
system.physmem1.bytes_read::cpu.data 1495885127 # Number of bytes read from this memory
system.physmem1.bytes_read::total 9813991967 # Number of bytes read from this memory
system.physmem1.bytes_inst_read::cpu.inst 8318106840 # Number of instructions bytes read from this memory
system.physmem1.bytes_inst_read::total 8318106840 # Number of instructions bytes read from this memory
system.physmem1.bytes_written::cpu.data 897268422 # Number of bytes written to this memory
system.physmem1.bytes_written::total 897268422 # Number of bytes written to this memory
system.physmem1.num_reads::cpu.inst 2079526710 # Number of read requests responded to by this memory
system.physmem1.num_reads::cpu.data 323962420 # Number of read requests responded to by this memory
system.physmem1.num_reads::total 2403489130 # Number of read requests responded to by this memory
system.physmem1.num_writes::cpu.data 187387796 # Number of write requests responded to by this memory
system.physmem1.num_writes::total 187387796 # Number of write requests responded to by this memory
system.physmem1.num_other::cpu.data 5403067 # Number of other requests responded to by this memory
system.physmem1.num_other::total 5403067 # Number of other requests responded to by this memory
system.physmem1.bw_read::cpu.inst 3723784842 # Total read bandwidth from this memory (bytes/s)
system.physmem1.bw_read::cpu.data 669666123 # Total read bandwidth from this memory (bytes/s)
system.physmem1.bw_read::total 4393450966 # Total read bandwidth from this memory (bytes/s)
system.physmem1.bw_inst_read::cpu.inst 3723784842 # Instruction read bandwidth from this memory (bytes/s)
system.physmem1.bw_inst_read::total 3723784842 # Instruction read bandwidth from this memory (bytes/s)
system.physmem1.bw_write::cpu.data 401682091 # Write bandwidth from this memory (bytes/s)
system.physmem1.bw_write::total 401682091 # Write bandwidth from this memory (bytes/s)
system.physmem1.bw_total::cpu.inst 3723784842 # Total bandwidth to/from this memory (bytes/s)
system.physmem1.bw_total::cpu.data 1071348214 # Total bandwidth to/from this memory (bytes/s)
system.physmem1.bw_total::total 4795133057 # Total bandwidth to/from this memory (bytes/s)
system.partition_desc.bytes_read::cpu.data 4846 # Number of bytes read from this memory
system.partition_desc.bytes_read::total 4846 # Number of bytes read from this memory
system.partition_desc.num_reads::cpu.data 608 # Number of read requests responded to by this memory
system.partition_desc.num_reads::total 608 # Number of read requests responded to by this memory
system.partition_desc.bw_read::cpu.data 2169 # Total read bandwidth from this memory (bytes/s)
system.partition_desc.bw_read::total 2169 # Total read bandwidth from this memory (bytes/s)
system.partition_desc.bw_total::cpu.data 2169 # Total bandwidth to/from this memory (bytes/s)
system.partition_desc.bw_total::total 2169 # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput 5163367605 # Throughput (bytes/s) system.membus.throughput 5163367605 # Throughput (bytes/s)
system.membus.data_through_bus 11533814443 # Total data (bytes) system.membus.data_through_bus 11533814443 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
@ -136,6 +136,41 @@ system.cpu.num_busy_cycles 2233777513 # Nu
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 441057355 # Number of branches fetched system.cpu.Branches 441057355 # Number of branches fetched
system.cpu.op_class::No_OpClass 49673656 2.22% 2.22% # Class of executed instruction
system.cpu.op_class::IntAlu 1619015933 72.49% 74.71% # Class of executed instruction
system.cpu.op_class::IntMult 0 0.00% 74.71% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 74.71% # Class of executed instruction
system.cpu.op_class::FloatAdd 8419779 0.38% 75.09% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 75.09% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 75.09% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 75.09% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 75.09% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 75.09% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 75.09% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 75.09% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 75.09% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 75.09% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 75.09% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 75.09% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 75.09% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 75.09% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 75.09% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 75.09% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 75.09% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 75.09% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 75.09% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 75.09% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 75.09% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 75.09% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 75.09% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 75.09% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 75.09% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 75.09% # Class of executed instruction
system.cpu.op_class::MemRead 356274529 15.95% 91.04% # Class of executed instruction
system.cpu.op_class::MemWrite 200199782 8.96% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 2233583679 # Class of executed instruction
system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed