Merge with head
--HG-- extra : convert_revision : cc73b9aaf73e9dacf52f3350fa591e67ca4ccee6
This commit is contained in:
parent
8d1c7a83d7
commit
7227ab5f22
15 changed files with 212 additions and 104 deletions
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@ -364,6 +364,8 @@ DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
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DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid);
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assert(!pkt->wasNacked());
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// Only change the status if it's still waiting on the icache access
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// to return.
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if (fetchStatus[tid] != IcacheWaitResponse ||
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@ -80,6 +80,8 @@ template <class Impl>
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bool
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LSQ<Impl>::DcachePort::recvTiming(PacketPtr pkt)
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{
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if (pkt->isError())
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DPRINTF(LSQ, "Got error packet back for address: %#X\n", pkt->getAddr());
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if (pkt->isResponse()) {
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lsq->thread[pkt->req->getThreadNum()].completeDataAccess(pkt);
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}
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@ -83,6 +83,8 @@ LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
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//iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);
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assert(!pkt->wasNacked());
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if (isSwitchedOut() || inst->isSquashed()) {
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iewStage->decrWb(inst->seqNum);
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} else {
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@ -328,6 +328,7 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
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dcache_latency += dcachePort.sendAtomic(&pkt);
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}
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dcache_access = true;
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assert(!pkt.isError());
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if (req->isLocked()) {
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@ -611,6 +612,7 @@ AtomicSimpleCPU::tick()
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else
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icache_latency = icachePort.sendAtomic(&ifetch_pkt);
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assert(!ifetch_pkt.isError());
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// ifetch_req is initialized to read the instruction directly
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// into the CPU object's inst field.
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@ -583,7 +583,7 @@ TimingSimpleCPU::IcachePort::ITickEvent::process()
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bool
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TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
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{
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if (pkt->isResponse()) {
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if (pkt->isResponse() && !pkt->wasNacked()) {
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// delay processing of returned data until next CPU clock edge
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Tick next_tick = cpu->nextCycle(curTick);
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@ -686,7 +686,7 @@ TimingSimpleCPU::DcachePort::setPeer(Port *port)
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bool
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TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
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{
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if (pkt->isResponse()) {
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if (pkt->isResponse() && !pkt->wasNacked()) {
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// delay processing of returned data until next CPU clock edge
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Tick next_tick = cpu->nextCycle(curTick);
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@ -107,6 +107,7 @@ AlphaConsole::read(PacketPtr pkt)
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Addr daddr = pkt->getAddr() - pioAddr;
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pkt->allocate();
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pkt->makeAtomicResponse();
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switch (pkt->getSize())
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{
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@ -188,7 +189,6 @@ AlphaConsole::read(PacketPtr pkt)
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default:
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pkt->setBadAddress();
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}
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pkt->makeAtomicResponse();
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return pioDelay;
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}
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@ -57,7 +57,7 @@ using namespace Net;
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IGbE::IGbE(const Params *p)
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: EtherDevice(p), etherInt(NULL), drainEvent(NULL), useFlowControl(p->use_flow_control),
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rxFifo(p->rx_fifo_size), txFifo(p->tx_fifo_size), rxTick(false),
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txTick(false), txFifoTick(false), rdtrEvent(this), radvEvent(this),
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txTick(false), txFifoTick(false), rxDmaPacket(false), rdtrEvent(this), radvEvent(this),
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tadvEvent(this), tidvEvent(this), tickEvent(this), interEvent(this),
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rxDescCache(this, name()+".RxDesc", p->rx_desc_cache_size),
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txDescCache(this, name()+".TxDesc", p->tx_desc_cache_size), clock(p->clock)
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@ -113,7 +113,7 @@ EtherInt*
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IGbE::getEthPort(const std::string &if_name, int idx)
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{
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if (if_name == "interface" && !etherInt) {
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if (if_name == "interface") {
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if (etherInt->getPeer())
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panic("Port already connected to\n");
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return etherInt;
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@ -504,8 +504,13 @@ IGbE::write(PacketPtr pkt)
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break;
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case REG_RDT:
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regs.rdt = val;
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rxTick = true;
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restartClock();
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DPRINTF(EthernetSM, "RXS: RDT Updated.\n");
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if (getState() == SimObject::Running) {
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DPRINTF(EthernetSM, "RXS: RDT Fetching Descriptors!\n");
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rxDescCache.fetchDescriptors();
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} else {
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DPRINTF(EthernetSM, "RXS: RDT NOT Fetching Desc b/c draining!\n");
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}
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break;
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case REG_RDTR:
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regs.rdtr = val;
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@ -531,8 +536,13 @@ IGbE::write(PacketPtr pkt)
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break;
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case REG_TDT:
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regs.tdt = val;
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txTick = true;
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restartClock();
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DPRINTF(EthernetSM, "TXS: TX Tail pointer updated\n");
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if (getState() == SimObject::Running) {
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DPRINTF(EthernetSM, "TXS: TDT Fetching Descriptors!\n");
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txDescCache.fetchDescriptors();
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} else {
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DPRINTF(EthernetSM, "TXS: TDT NOT Fetching Desc b/c draining!\n");
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}
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break;
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case REG_TIDV:
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regs.tidv = val;
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@ -566,33 +576,47 @@ IGbE::postInterrupt(IntTypes t, bool now)
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assert(t);
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// Interrupt is already pending
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if (t & regs.icr())
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if (t & regs.icr() && !now)
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return;
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if (regs.icr() & regs.imr)
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{
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regs.icr = regs.icr() | t;
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if (!interEvent.scheduled())
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interEvent.schedule(curTick + Clock::Int::ns * 256 *
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regs.itr.interval());
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} else {
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regs.icr = regs.icr() | t;
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if (regs.itr.interval() == 0 || now) {
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if (interEvent.scheduled())
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if (interEvent.scheduled()) {
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interEvent.deschedule();
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}
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cpuPostInt();
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} else {
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DPRINTF(EthernetIntr, "EINT: Scheduling timer interrupt for %d ticks\n",
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Clock::Int::ns * 256 * regs.itr.interval());
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if (!interEvent.scheduled())
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if (!interEvent.scheduled()) {
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interEvent.schedule(curTick + Clock::Int::ns * 256 * regs.itr.interval());
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}
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}
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}
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void
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IGbE::delayIntEvent()
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{
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cpuPostInt();
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}
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void
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IGbE::cpuPostInt()
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{
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if (!(regs.icr() & regs.imr)) {
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DPRINTF(Ethernet, "Interrupt Masked. Not Posting\n");
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return;
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}
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DPRINTF(Ethernet, "Posting Interrupt\n");
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if (interEvent.scheduled()) {
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interEvent.deschedule();
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}
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if (rdtrEvent.scheduled()) {
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regs.icr.rxt0(1);
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rdtrEvent.deschedule();
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@ -613,7 +637,9 @@ IGbE::cpuPostInt()
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regs.icr.int_assert(1);
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DPRINTF(EthernetIntr, "EINT: Posting interrupt to CPU now. Vector %#x\n",
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regs.icr());
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intrPost();
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}
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void
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@ -630,22 +656,30 @@ IGbE::cpuClearInt()
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void
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IGbE::chkInterrupt()
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{
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DPRINTF(Ethernet, "Checking interrupts icr: %#x imr: %#x\n", regs.icr(),
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regs.imr);
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// Check if we need to clear the cpu interrupt
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if (!(regs.icr() & regs.imr)) {
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DPRINTF(Ethernet, "Mask cleaned all interrupts\n");
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if (interEvent.scheduled())
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interEvent.deschedule();
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if (regs.icr.int_assert())
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cpuClearInt();
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}
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DPRINTF(Ethernet, "ITR = %#X itr.interval = %#X\n", regs.itr(), regs.itr.interval());
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if (regs.icr() & regs.imr) {
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if (regs.itr.interval() == 0) {
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cpuPostInt();
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} else {
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if (!interEvent.scheduled())
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DPRINTF(Ethernet, "Possibly scheduling interrupt because of imr write\n");
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if (!interEvent.scheduled()) {
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DPRINTF(Ethernet, "Scheduling for %d\n", curTick + Clock::Int::ns
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* 256 * regs.itr.interval());
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interEvent.schedule(curTick + Clock::Int::ns * 256 * regs.itr.interval());
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}
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}
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}
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}
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@ -682,6 +716,7 @@ IGbE::RxDescCache::pktComplete()
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RxDesc *desc;
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desc = unusedCache.front();
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uint16_t crcfixup = igbe->regs.rctl.secrc() ? 0 : 4 ;
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desc->len = htole((uint16_t)(pktPtr->length + crcfixup));
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DPRINTF(EthernetDesc, "pktPtr->length: %d stripcrc offset: %d value written: %d %d\n",
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@ -754,10 +789,11 @@ IGbE::RxDescCache::pktComplete()
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if (igbe->regs.radv.idv() && igbe->regs.rdtr.delay()) {
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DPRINTF(EthernetSM, "RXS: Scheduling ADV for %d\n",
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igbe->regs.radv.idv() * igbe->intClock());
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if (!igbe->radvEvent.scheduled())
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if (!igbe->radvEvent.scheduled()) {
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igbe->radvEvent.schedule(curTick + igbe->regs.radv.idv() *
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igbe->intClock());
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}
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}
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// if neither radv or rdtr, maybe itr is set...
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if (!igbe->regs.rdtr.delay()) {
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@ -775,10 +811,13 @@ IGbE::RxDescCache::pktComplete()
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DPRINTF(EthernetDesc, "Processing of this descriptor complete\n");
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unusedCache.pop_front();
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usedCache.push_back(desc);
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pktPtr = NULL;
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enableSm();
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pktDone = true;
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igbe->checkDrain();
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}
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void
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@ -843,11 +882,13 @@ IGbE::TxDescCache::getPacketSize()
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// I think we can just ignore these for now?
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desc = unusedCache.front();
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DPRINTF(EthernetDesc, "Descriptor upper: %#x lower: %#X\n", desc->d1,
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desc->d2);
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// is this going to be a tcp or udp packet?
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isTcp = TxdOp::tcp(desc) ? true : false;
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// make sure it's ipv4
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assert(TxdOp::ip(desc));
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//assert(TxdOp::ip(desc));
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TxdOp::setDd(desc);
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unusedCache.pop_front();
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@ -894,7 +935,6 @@ IGbE::TxDescCache::pktComplete()
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DPRINTF(EthernetDesc, "DMA of packet complete\n");
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desc = unusedCache.front();
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assert((TxdOp::isLegacy(desc) || TxdOp::isData(desc)) && TxdOp::getLen(desc));
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@ -952,18 +992,19 @@ IGbE::TxDescCache::pktComplete()
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DPRINTF(EthernetDesc, "Calculated IP checksum\n");
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}
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if (TxdOp::txsm(desc)) {
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if (isTcp) {
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TcpPtr tcp(ip);
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assert(tcp);
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UdpPtr udp(ip);
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if (tcp) {
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tcp->sum(0);
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tcp->sum(cksum(tcp));
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DPRINTF(EthernetDesc, "Calculated TCP checksum\n");
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} else {
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UdpPtr udp(ip);
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} else if (udp) {
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assert(udp);
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udp->sum(0);
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udp->sum(cksum(udp));
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DPRINTF(EthernetDesc, "Calculated UDP checksum\n");
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} else {
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panic("Told to checksum, but don't know how\n");
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}
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}
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}
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@ -979,11 +1020,12 @@ IGbE::TxDescCache::pktComplete()
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if (igbe->regs.tadv.idv() && igbe->regs.tidv.idv()) {
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DPRINTF(EthernetDesc, "setting tadv\n");
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if (!igbe->tadvEvent.scheduled())
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if (!igbe->tadvEvent.scheduled()) {
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igbe->tadvEvent.schedule(curTick + igbe->regs.tadv.idv() *
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igbe->intClock());
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}
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}
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}
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@ -1103,8 +1145,11 @@ IGbE::checkDrain()
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if (!drainEvent)
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return;
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if (rxDescCache.hasOutstandingEvents() ||
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txDescCache.hasOutstandingEvents()) {
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txFifoTick = false;
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txTick = false;
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rxTick = false;
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if (!rxDescCache.hasOutstandingEvents() &&
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!txDescCache.hasOutstandingEvents()) {
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drainEvent->process();
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drainEvent = NULL;
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}
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@ -1124,6 +1169,7 @@ IGbE::txStateMachine()
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// iteration we'll get the rest of the data
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if (txPacket && txDescCache.packetAvailable() && txPacket->length) {
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bool success;
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DPRINTF(EthernetSM, "TXS: packet placed in TX FIFO\n");
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success = txFifo.push(txPacket);
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txFifoTick = true;
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@ -1146,11 +1192,12 @@ IGbE::txStateMachine()
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if (!txDescCache.packetWaiting()) {
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if (txDescCache.descLeft() == 0) {
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postInterrupt(IT_TXQE);
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txDescCache.writeback(0);
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DPRINTF(EthernetSM, "TXS: No descriptors left in ring, forcing "
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"writeback stopping ticking and posting TXQE\n");
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txDescCache.writeback(0);
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txDescCache.fetchDescriptors();
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txTick = false;
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postInterrupt(IT_TXQE, true);
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return;
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}
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@ -1170,12 +1217,13 @@ IGbE::txStateMachine()
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txFifo.reserve(size);
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txDescCache.getPacketData(txPacket);
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} else if (size <= 0) {
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DPRINTF(EthernetSM, "TXS: getPacketSize returned: %d\n", size);
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DPRINTF(EthernetSM, "TXS: No packets to get, writing back used descriptors\n");
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txDescCache.writeback(0);
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} else {
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txDescCache.writeback((cacheBlockSize()-1)>>4);
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DPRINTF(EthernetSM, "TXS: FIFO full, stopping ticking until space "
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"available in FIFO\n");
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txDescCache.writeback((cacheBlockSize()-1)>>4);
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txTick = false;
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}
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@ -1190,6 +1238,7 @@ bool
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IGbE::ethRxPkt(EthPacketPtr pkt)
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{
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DPRINTF(Ethernet, "RxFIFO: Receiving pcakte from wire\n");
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if (!regs.rctl.en()) {
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DPRINTF(Ethernet, "RxFIFO: RX not enabled, dropping\n");
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return true;
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@ -1235,8 +1284,6 @@ IGbE::rxStateMachine()
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}
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if (descLeft == 0) {
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DPRINTF(EthernetSM, "RXS: No descriptors left in ring, forcing"
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" writeback and stopping ticking\n");
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rxDescCache.writeback(0);
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rxTick = false;
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}
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@ -1310,16 +1357,26 @@ IGbE::txWire()
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return;
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}
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if (etherInt->askBusy()) {
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// We'll get woken up when the packet ethTxDone() gets called
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txFifoTick = false;
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} else {
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if (DTRACE(EthernetSM)) {
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IpPtr ip(txFifo.front());
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if (ip)
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DPRINTF(EthernetSM, "Transmitting Ip packet with Id=%d\n",
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ip->id());
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else
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DPRINTF(EthernetSM, "Transmitting Non-Ip packet\n");
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}
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if (etherInt->sendPacket(txFifo.front())) {
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bool r = etherInt->sendPacket(txFifo.front());
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assert(r);
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r += 1;
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DPRINTF(EthernetSM, "TxFIFO: Successful transmit, bytes available in fifo: %d\n",
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txFifo.avail());
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txFifo.pop();
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} else {
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// We'll get woken up when the packet ethTxDone() gets called
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txFifoTick = false;
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}
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}
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void
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@ -1348,6 +1405,7 @@ IGbE::ethTxDone()
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// fifo to send another packet
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// tx sm to put more data into the fifo
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txFifoTick = true;
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if (txDescCache.descLeft() != 0)
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txTick = true;
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restartClock();
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@ -1387,15 +1445,15 @@ IGbE::serialize(std::ostream &os)
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SERIALIZE_SCALAR(radv_time);
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if (tidvEvent.scheduled())
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rdtr_time = tidvEvent.when();
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tidv_time = tidvEvent.when();
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SERIALIZE_SCALAR(tidv_time);
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if (tadvEvent.scheduled())
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rdtr_time = tadvEvent.when();
|
||||
tadv_time = tadvEvent.when();
|
||||
SERIALIZE_SCALAR(tadv_time);
|
||||
|
||||
if (interEvent.scheduled())
|
||||
rdtr_time = interEvent.when();
|
||||
inter_time = interEvent.when();
|
||||
SERIALIZE_SCALAR(inter_time);
|
||||
|
||||
nameOut(os, csprintf("%s.TxDescCache", name()));
|
||||
|
|
|
@ -147,9 +147,10 @@ class IGbE : public EtherDevice
|
|||
|
||||
/** Send an interrupt to the cpu
|
||||
*/
|
||||
void delayIntEvent();
|
||||
void cpuPostInt();
|
||||
// Event to moderate interrupts
|
||||
EventWrapper<IGbE, &IGbE::cpuPostInt> interEvent;
|
||||
EventWrapper<IGbE, &IGbE::delayIntEvent> interEvent;
|
||||
|
||||
/** Clear the interupt line to the cpu
|
||||
*/
|
||||
|
@ -177,6 +178,7 @@ class IGbE : public EtherDevice
|
|||
virtual void updateHead(long h) = 0;
|
||||
virtual void enableSm() = 0;
|
||||
virtual void intAfterWb() const {}
|
||||
virtual void fetchAfterWb() = 0;
|
||||
|
||||
std::deque<T*> usedCache;
|
||||
std::deque<T*> unusedCache;
|
||||
|
@ -283,12 +285,6 @@ class IGbE : public EtherDevice
|
|||
for (int x = 0; x < wbOut; x++)
|
||||
memcpy(&wbBuf[x], usedCache[x], sizeof(T));
|
||||
|
||||
for (int x = 0; x < wbOut; x++) {
|
||||
assert(usedCache.size());
|
||||
delete usedCache[0];
|
||||
usedCache.pop_front();
|
||||
};
|
||||
|
||||
|
||||
assert(wbOut);
|
||||
igbe->dmaWrite(igbe->platform->pciToDma(descBase() + curHead * sizeof(T)),
|
||||
|
@ -307,7 +303,6 @@ class IGbE : public EtherDevice
|
|||
else
|
||||
max_to_fetch = descLen() - cachePnt;
|
||||
|
||||
|
||||
max_to_fetch = std::min(max_to_fetch, (size - usedCache.size() -
|
||||
unusedCache.size()));
|
||||
|
||||
|
@ -369,10 +364,16 @@ class IGbE : public EtherDevice
|
|||
*/
|
||||
void wbComplete()
|
||||
{
|
||||
|
||||
long curHead = descHead();
|
||||
#ifndef NDEBUG
|
||||
long oldHead = curHead;
|
||||
#endif
|
||||
for (int x = 0; x < wbOut; x++) {
|
||||
assert(usedCache.size());
|
||||
delete usedCache[0];
|
||||
usedCache.pop_front();
|
||||
};
|
||||
|
||||
curHead += wbOut;
|
||||
wbOut = 0;
|
||||
|
@ -387,13 +388,18 @@ class IGbE : public EtherDevice
|
|||
oldHead, curHead);
|
||||
|
||||
// If we still have more to wb, call wb now
|
||||
bool oldMoreToWb = moreToWb;
|
||||
if (moreToWb) {
|
||||
DPRINTF(EthernetDesc, "Writeback has more todo\n");
|
||||
writeback(wbAlignment);
|
||||
}
|
||||
|
||||
intAfterWb();
|
||||
if (!oldMoreToWb) {
|
||||
igbe->checkDrain();
|
||||
}
|
||||
fetchAfterWb();
|
||||
}
|
||||
|
||||
|
||||
EventWrapper<DescCache, &DescCache::wbComplete> wbEvent;
|
||||
|
@ -502,6 +508,10 @@ class IGbE : public EtherDevice
|
|||
virtual long descTail() const { return igbe->regs.rdt(); }
|
||||
virtual void updateHead(long h) { igbe->regs.rdh(h); }
|
||||
virtual void enableSm();
|
||||
virtual void fetchAfterWb() {
|
||||
if (!igbe->rxTick && igbe->getState() == SimObject::Running)
|
||||
fetchDescriptors();
|
||||
}
|
||||
|
||||
bool pktDone;
|
||||
|
||||
|
@ -544,7 +554,13 @@ class IGbE : public EtherDevice
|
|||
virtual long descLen() const { return igbe->regs.tdlen() >> 4; }
|
||||
virtual void updateHead(long h) { igbe->regs.tdh(h); }
|
||||
virtual void enableSm();
|
||||
virtual void intAfterWb() const { igbe->postInterrupt(iGbReg::IT_TXDW);}
|
||||
virtual void intAfterWb() const {
|
||||
igbe->postInterrupt(iGbReg::IT_TXDW);
|
||||
}
|
||||
virtual void fetchAfterWb() {
|
||||
if (!igbe->txTick && igbe->getState() == SimObject::Running)
|
||||
fetchDescriptors();
|
||||
}
|
||||
|
||||
bool pktDone;
|
||||
bool isTcp;
|
||||
|
|
|
@ -56,6 +56,7 @@ Tick
|
|||
IsaFake::read(PacketPtr pkt)
|
||||
{
|
||||
|
||||
pkt->makeAtomicResponse();
|
||||
if (params()->warn_access != "")
|
||||
warn("Device %s accessed by read to address %#x size=%d\n",
|
||||
name(), pkt->getAddr(), pkt->getSize());
|
||||
|
@ -83,7 +84,6 @@ IsaFake::read(PacketPtr pkt)
|
|||
default:
|
||||
panic("invalid access size!\n");
|
||||
}
|
||||
pkt->makeAtomicResponse();
|
||||
}
|
||||
return pioDelay;
|
||||
}
|
||||
|
@ -91,6 +91,7 @@ IsaFake::read(PacketPtr pkt)
|
|||
Tick
|
||||
IsaFake::write(PacketPtr pkt)
|
||||
{
|
||||
pkt->makeAtomicResponse();
|
||||
if (params()->warn_access != "") {
|
||||
uint64_t data;
|
||||
switch (pkt->getSize()) {
|
||||
|
@ -138,7 +139,6 @@ IsaFake::write(PacketPtr pkt)
|
|||
panic("invalid access size!\n");
|
||||
}
|
||||
}
|
||||
pkt->makeAtomicResponse();
|
||||
}
|
||||
return pioDelay;
|
||||
}
|
||||
|
|
|
@ -119,17 +119,17 @@ Bridge::BridgePort::recvTiming(PacketPtr pkt)
|
|||
|
||||
DPRINTF(BusBridge, "Local queue size: %d outreq: %d outresp: %d\n",
|
||||
sendQueue.size(), queuedRequests, outstandingResponses);
|
||||
DPRINTF(BusBridge, "Remove queue size: %d outreq: %d outresp: %d\n",
|
||||
DPRINTF(BusBridge, "Remote queue size: %d outreq: %d outresp: %d\n",
|
||||
otherPort->sendQueue.size(), otherPort->queuedRequests,
|
||||
otherPort->outstandingResponses);
|
||||
|
||||
if (pkt->isRequest() && otherPort->reqQueueFull() && !pkt->wasNacked()) {
|
||||
if (pkt->isRequest() && otherPort->reqQueueFull()) {
|
||||
DPRINTF(BusBridge, "Remote queue full, nacking\n");
|
||||
nackRequest(pkt);
|
||||
return true;
|
||||
}
|
||||
|
||||
if (pkt->needsResponse() && !pkt->wasNacked())
|
||||
if (pkt->needsResponse())
|
||||
if (respQueueFull()) {
|
||||
DPRINTF(BusBridge, "Local queue full, no space for response, nacking\n");
|
||||
DPRINTF(BusBridge, "queue size: %d outreq: %d outstanding resp: %d\n",
|
||||
|
@ -150,8 +150,8 @@ void
|
|||
Bridge::BridgePort::nackRequest(PacketPtr pkt)
|
||||
{
|
||||
// Nack the packet
|
||||
pkt->makeTimingResponse();
|
||||
pkt->setNacked();
|
||||
pkt->setDest(pkt->getSrc());
|
||||
|
||||
//put it on the list to send
|
||||
Tick readyTime = curTick + nackDelay;
|
||||
|
@ -195,27 +195,23 @@ Bridge::BridgePort::nackRequest(PacketPtr pkt)
|
|||
void
|
||||
Bridge::BridgePort::queueForSendTiming(PacketPtr pkt)
|
||||
{
|
||||
if (pkt->isResponse() || pkt->wasNacked()) {
|
||||
if (pkt->isResponse()) {
|
||||
// This is a response for a request we forwarded earlier. The
|
||||
// corresponding PacketBuffer should be stored in the packet's
|
||||
// senderState field.
|
||||
|
||||
PacketBuffer *buf = dynamic_cast<PacketBuffer*>(pkt->senderState);
|
||||
assert(buf != NULL);
|
||||
// set up new packet dest & senderState based on values saved
|
||||
// from original request
|
||||
buf->fixResponse(pkt);
|
||||
|
||||
// Check if this packet was expecting a response and it's a nacked
|
||||
// packet, in which case we will never being seeing it
|
||||
if (buf->expectResponse && pkt->wasNacked())
|
||||
--outstandingResponses;
|
||||
|
||||
DPRINTF(BusBridge, "response, new dest %d\n", pkt->getDest());
|
||||
delete buf;
|
||||
}
|
||||
|
||||
|
||||
if (pkt->isRequest() && !pkt->wasNacked()) {
|
||||
if (pkt->isRequest()) {
|
||||
++queuedRequests;
|
||||
}
|
||||
|
||||
|
@ -249,7 +245,15 @@ Bridge::BridgePort::trySend()
|
|||
buf->origSrc, pkt->getDest(), pkt->getAddr());
|
||||
|
||||
bool wasReq = pkt->isRequest();
|
||||
bool wasNacked = pkt->wasNacked();
|
||||
bool was_nacked_here = buf->nackedHere;
|
||||
|
||||
// If the send was successful, make sure sender state was set to NULL
|
||||
// otherwise we could get a NACK back of a packet that didn't expect a
|
||||
// response and we would try to use freed memory.
|
||||
|
||||
Packet::SenderState *old_sender_state = pkt->senderState;
|
||||
if (pkt->isRequest() && !buf->expectResponse)
|
||||
pkt->senderState = NULL;
|
||||
|
||||
if (sendTiming(pkt)) {
|
||||
// send successful
|
||||
|
@ -266,12 +270,10 @@ Bridge::BridgePort::trySend()
|
|||
delete buf;
|
||||
}
|
||||
|
||||
if (!wasNacked) {
|
||||
if (wasReq)
|
||||
--queuedRequests;
|
||||
else
|
||||
else if (!was_nacked_here)
|
||||
--outstandingResponses;
|
||||
}
|
||||
|
||||
// If there are more packets to send, schedule event to try again.
|
||||
if (!sendQueue.empty()) {
|
||||
|
@ -281,8 +283,10 @@ Bridge::BridgePort::trySend()
|
|||
}
|
||||
} else {
|
||||
DPRINTF(BusBridge, " unsuccessful\n");
|
||||
pkt->senderState = old_sender_state;
|
||||
inRetry = true;
|
||||
}
|
||||
|
||||
DPRINTF(BusBridge, "trySend: queue size: %d outreq: %d outstanding resp: %d\n",
|
||||
sendQueue.size(), queuedRequests, outstandingResponses);
|
||||
}
|
||||
|
|
|
@ -78,17 +78,19 @@ class Bridge : public MemObject
|
|||
public:
|
||||
Tick ready;
|
||||
PacketPtr pkt;
|
||||
bool nackedHere;
|
||||
Packet::SenderState *origSenderState;
|
||||
short origSrc;
|
||||
bool expectResponse;
|
||||
|
||||
PacketBuffer(PacketPtr _pkt, Tick t, bool nack = false)
|
||||
: ready(t), pkt(_pkt),
|
||||
origSenderState(_pkt->senderState), origSrc(_pkt->getSrc()),
|
||||
: ready(t), pkt(_pkt), nackedHere(nack),
|
||||
origSenderState(_pkt->senderState),
|
||||
origSrc(nack ? _pkt->getDest() : _pkt->getSrc() ),
|
||||
expectResponse(_pkt->needsResponse() && !nack)
|
||||
|
||||
{
|
||||
if (!pkt->isResponse() && !nack && !pkt->wasNacked())
|
||||
if (!pkt->isResponse() && !nack)
|
||||
pkt->senderState = this;
|
||||
}
|
||||
|
||||
|
|
|
@ -237,6 +237,7 @@ Bus::recvTiming(PacketPtr pkt)
|
|||
if (dest_port_id == src) {
|
||||
// Must be forwarded snoop up from below...
|
||||
assert(dest == Packet::Broadcast);
|
||||
assert(src != defaultId); // catch infinite loops
|
||||
} else {
|
||||
// send to actual target
|
||||
if (!dest_port->sendTiming(pkt)) {
|
||||
|
|
25
src/mem/cache/cache_impl.hh
vendored
25
src/mem/cache/cache_impl.hh
vendored
|
@ -606,7 +606,13 @@ Cache<TagStore>::atomicAccess(PacketPtr pkt)
|
|||
DPRINTF(Cache, "Receive response: %s for addr %x in state %i\n",
|
||||
busPkt->cmdString(), busPkt->getAddr(), old_state);
|
||||
|
||||
if (isCacheFill) {
|
||||
bool is_error = busPkt->isError();
|
||||
assert(!busPkt->wasNacked());
|
||||
|
||||
if (is_error && pkt->needsResponse()) {
|
||||
pkt->makeAtomicResponse();
|
||||
pkt->copyError(busPkt);
|
||||
} else if (isCacheFill && !is_error) {
|
||||
PacketList writebacks;
|
||||
blk = handleFill(busPkt, blk, writebacks);
|
||||
satisfyCpuSideRequest(pkt, blk);
|
||||
|
@ -667,6 +673,8 @@ Cache<TagStore>::handleResponse(PacketPtr pkt)
|
|||
{
|
||||
Tick time = curTick + hitLatency;
|
||||
MSHR *mshr = dynamic_cast<MSHR*>(pkt->senderState);
|
||||
bool is_error = pkt->isError();
|
||||
|
||||
assert(mshr);
|
||||
|
||||
if (pkt->wasNacked()) {
|
||||
|
@ -675,7 +683,11 @@ Cache<TagStore>::handleResponse(PacketPtr pkt)
|
|||
"not implemented\n");
|
||||
return;
|
||||
}
|
||||
assert(!pkt->isError());
|
||||
if (is_error) {
|
||||
DPRINTF(Cache, "Cache received packet with error for address %x, "
|
||||
"cmd: %s\n", pkt->getAddr(), pkt->cmdString());
|
||||
}
|
||||
|
||||
DPRINTF(Cache, "Handling response to %x\n", pkt->getAddr());
|
||||
|
||||
MSHRQueue *mq = mshr->queue;
|
||||
|
@ -702,7 +714,7 @@ Cache<TagStore>::handleResponse(PacketPtr pkt)
|
|||
miss_latency;
|
||||
}
|
||||
|
||||
if (mshr->isCacheFill) {
|
||||
if (mshr->isCacheFill && !is_error) {
|
||||
DPRINTF(Cache, "Block for addr %x being updated in Cache\n",
|
||||
pkt->getAddr());
|
||||
|
||||
|
@ -744,13 +756,18 @@ Cache<TagStore>::handleResponse(PacketPtr pkt)
|
|||
} else {
|
||||
// not a cache fill, just forwarding response
|
||||
completion_time = tags->getHitLatency() + pkt->finishTime;
|
||||
if (pkt->isRead()) {
|
||||
if (pkt->isRead() && !is_error) {
|
||||
target->pkt->setData(pkt->getPtr<uint8_t>());
|
||||
}
|
||||
}
|
||||
target->pkt->makeTimingResponse();
|
||||
// if this packet is an error copy that to the new packet
|
||||
if (is_error)
|
||||
target->pkt->copyError(pkt);
|
||||
cpuSidePort->respond(target->pkt, completion_time);
|
||||
} else {
|
||||
// I don't believe that a snoop can be in an error state
|
||||
assert(!is_error);
|
||||
// response to snoop request
|
||||
DPRINTF(Cache, "processing deferred snoop...\n");
|
||||
handleSnoop(target->pkt, blk, true, true);
|
||||
|
|
|
@ -117,11 +117,11 @@ MemCmd::commandInfo[] =
|
|||
{ SET5(IsRead, IsWrite, NeedsExclusive, IsResponse, HasData),
|
||||
InvalidCmd, "SwapResp" },
|
||||
/* NetworkNackError -- nacked at network layer (not by protocol) */
|
||||
{ SET2(IsRequest, IsError), InvalidCmd, "NetworkNackError" },
|
||||
{ SET2(IsResponse, IsError), InvalidCmd, "NetworkNackError" },
|
||||
/* InvalidDestError -- packet dest field invalid */
|
||||
{ SET2(IsRequest, IsError), InvalidCmd, "InvalidDestError" },
|
||||
{ SET2(IsResponse, IsError), InvalidCmd, "InvalidDestError" },
|
||||
/* BadAddressError -- memory address invalid */
|
||||
{ SET2(IsRequest, IsError), InvalidCmd, "BadAddressError" }
|
||||
{ SET2(IsResponse, IsError), InvalidCmd, "BadAddressError" }
|
||||
};
|
||||
|
||||
|
||||
|
|
|
@ -332,10 +332,11 @@ class Packet : public FastAlloc
|
|||
// Network error conditions... encapsulate them as methods since
|
||||
// their encoding keeps changing (from result field to command
|
||||
// field, etc.)
|
||||
void setNacked() { origCmd = cmd; cmd = MemCmd::NetworkNackError; }
|
||||
void setBadAddress() { origCmd = cmd; cmd = MemCmd::BadAddressError; }
|
||||
void setNacked() { assert(isResponse()); cmd = MemCmd::NetworkNackError; }
|
||||
void setBadAddress() { assert(isResponse()); cmd = MemCmd::BadAddressError; }
|
||||
bool wasNacked() { return cmd == MemCmd::NetworkNackError; }
|
||||
bool hadBadAddress() { return cmd == MemCmd::BadAddressError; }
|
||||
void copyError(Packet *pkt) { assert(pkt->isError()); cmd = pkt->cmd; }
|
||||
|
||||
bool nic_pkt() { panic("Unimplemented"); M5_DUMMY_RETURN }
|
||||
|
||||
|
@ -431,6 +432,7 @@ class Packet : public FastAlloc
|
|||
{
|
||||
assert(needsResponse());
|
||||
assert(isRequest());
|
||||
origCmd = cmd;
|
||||
cmd = cmd.responseCommand();
|
||||
dest = src;
|
||||
destValid = srcValid;
|
||||
|
|
Loading…
Reference in a new issue