From 71b67d408bb595471a57dbe8e40cf5ac82c5d3b7 Mon Sep 17 00:00:00 2001 From: Korey Sewell Date: Thu, 24 Jun 2010 15:34:19 -0400 Subject: [PATCH] inorder: cleanup virtual functions remove the annotation 'virtual' from function declaration that isnt being derived from --- src/cpu/inorder/cpu.hh | 6 +- src/cpu/inorder/pipeline_stage.hh | 34 +++-- src/cpu/inorder/pipeline_traits.hh | 2 - src/cpu/inorder/resource.hh | 4 +- src/cpu/inorder/resource_pool.hh | 2 +- src/cpu/inorder/resources/agen_unit.hh | 1 - src/cpu/inorder/resources/branch_predictor.hh | 8 +- src/cpu/inorder/resources/cache_unit.hh | 16 +-- src/cpu/inorder/resources/decode_unit.hh | 3 +- src/cpu/inorder/resources/execution_unit.hh | 4 +- src/cpu/inorder/resources/fetch_seq_unit.hh | 18 +-- src/cpu/inorder/resources/graduation_unit.hh | 3 +- src/cpu/inorder/resources/inst_buffer.hh | 15 +- src/cpu/inorder/resources/mult_div_unit.hh | 16 +-- src/cpu/inorder/resources/use_def.hh | 9 +- src/cpu/inorder/thread_context.hh | 130 +++++++++--------- 16 files changed, 131 insertions(+), 140 deletions(-) diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh index 9be3c756e..4e7e64a40 100644 --- a/src/cpu/inorder/cpu.hh +++ b/src/cpu/inorder/cpu.hh @@ -222,10 +222,10 @@ class InOrderCPU : public BaseCPU vpe = 0; } - /** Processes a resource event. */ - virtual void process(); + /** Processes a CPU event. */ + void process(); - /** Returns the description of the resource event. */ + /** Returns the description of the CPU event. */ const char *description(); /** Schedule Event */ diff --git a/src/cpu/inorder/pipeline_stage.hh b/src/cpu/inorder/pipeline_stage.hh index 6c9cf0d99..c971e400e 100644 --- a/src/cpu/inorder/pipeline_stage.hh +++ b/src/cpu/inorder/pipeline_stage.hh @@ -106,9 +106,7 @@ class PipelineStage void regStats(); /** Sets CPU pointer. */ - virtual void setCPU(InOrderCPU *cpu_ptr); - - virtual void scheduleStageStart(int delay, ThreadID tid) { } + void setCPU(InOrderCPU *cpu_ptr); /** Sets the main backwards communication time buffer pointer. */ void setTimeBuffer(TimeBuffer *tb_ptr); @@ -145,7 +143,7 @@ class PipelineStage /** Ticks stage, processing all input signals and executing as many * instructions as possible. */ - virtual void tick(); + void tick(); /** Set a resource stall in the pipeline-stage */ void setResStall(ResReqPtr res_req, ThreadID tid); @@ -154,7 +152,7 @@ class PipelineStage void unsetResStall(ResReqPtr res_req, ThreadID tid); /** Remove all stall signals for a particular thread; */ - virtual void removeStalls(ThreadID tid); + void removeStalls(ThreadID tid); /** Is there room in the stage buffer? */ int stageBufferAvail(); @@ -168,7 +166,7 @@ class PipelineStage * change (ie switching from from blocking to unblocking). * @param tid Thread id to stage instructions from. */ - virtual void processThread(bool &status_change, ThreadID tid); + void processThread(bool &status_change, ThreadID tid); /** Processes instructions from fetch and passes them on to rename. * Decoding of instructions actually happens when they are created in @@ -178,13 +176,13 @@ class PipelineStage virtual void processInsts(ThreadID tid); /** Process all resources on an instruction's resource schedule */ - virtual bool processInstSchedule(DynInstPtr inst, int &reqs_processed); + bool processInstSchedule(DynInstPtr inst, int &reqs_processed); /** Is there room in the next stage buffer for this instruction? */ - virtual bool canSendInstToStage(unsigned stage_num); + bool canSendInstToStage(unsigned stage_num); /** Send an instruction to the next stage buffer */ - virtual bool sendInstToNextStage(DynInstPtr inst); + bool sendInstToNextStage(DynInstPtr inst); /** Inserts a thread's instructions into the skid buffer, to be staged * once stage unblocks. @@ -198,7 +196,7 @@ class PipelineStage bool skidsEmpty(); /** Updates overall stage status based on all of the threads' statuses. */ - virtual void updateStatus(); + void updateStatus(); /** Separates instructions from fetch into individual lists of instructions * sorted by thread. @@ -206,13 +204,13 @@ class PipelineStage void sortInsts(); /** Reads all stall signals from the backwards communication timebuffer. */ - virtual void readStallSignals(ThreadID tid); + void readStallSignals(ThreadID tid); /** Checks all input signals and updates stage's status appropriately. */ - virtual bool checkSignalsAndUpdate(ThreadID tid); + bool checkSignalsAndUpdate(ThreadID tid); /** Checks all stall signals, and returns if any are true. */ - virtual bool checkStall(ThreadID tid) const; + bool checkStall(ThreadID tid) const; /** Returns if there any instructions from the previous stage * on this cycle. @@ -223,7 +221,7 @@ class PipelineStage * become blocked. * @return Returns true if there is a status change. */ - virtual bool block(ThreadID tid); + bool block(ThreadID tid); void blockDueToBuffer(ThreadID tid); @@ -231,21 +229,21 @@ class PipelineStage * signals back that stage has unblocked. * @return Returns true if there is a status change. */ - virtual bool unblock(ThreadID tid); + bool unblock(ThreadID tid); public: - virtual void activateThread(ThreadID tid); + void activateThread(ThreadID tid); /** Squashes if there is a PC-relative branch that was predicted * incorrectly. Sends squash information back to fetch. */ - virtual void squashDueToBranch(DynInstPtr &inst, ThreadID tid); + void squashDueToBranch(DynInstPtr &inst, ThreadID tid); virtual void squashDueToMemStall(InstSeqNum seq_num, ThreadID tid); /** Squash instructions from stage buffer */ - virtual void squashPrevStageInsts(InstSeqNum squash_seq_num, ThreadID tid); + void squashPrevStageInsts(InstSeqNum squash_seq_num, ThreadID tid); /** Squashes due to commit signalling a squash. Changes status to * squashing and clears block/unblock signals as needed. diff --git a/src/cpu/inorder/pipeline_traits.hh b/src/cpu/inorder/pipeline_traits.hh index f039b9e5d..0f996023b 100644 --- a/src/cpu/inorder/pipeline_traits.hh +++ b/src/cpu/inorder/pipeline_traits.hh @@ -95,8 +95,6 @@ namespace ThePipeline { idx(_idx), priority(_priority) { } - virtual ~ScheduleEntry(){} - // Stage number to perform this service. int stageNum; diff --git a/src/cpu/inorder/resource.hh b/src/cpu/inorder/resource.hh index b423b1625..3e42593c2 100644 --- a/src/cpu/inorder/resource.hh +++ b/src/cpu/inorder/resource.hh @@ -132,7 +132,7 @@ class Resource { unsigned cmd); /** Schedule Execution of This Resource For A Given Slot*/ - virtual void scheduleExecution(int slot_idx); + void scheduleExecution(int slot_idx); /** Execute the function of this resource. The Default is action * is to do nothing. More specific models will derive from this @@ -195,7 +195,7 @@ class Resource { virtual ResReqPtr findRequest(DynInstPtr inst); /** */ - virtual void rejectRequest(DynInstPtr inst); + void rejectRequest(DynInstPtr inst); /** Request a Resource again. Some resources have to special process this * in subsequent accesses. diff --git a/src/cpu/inorder/resource_pool.hh b/src/cpu/inorder/resource_pool.hh index 60d35ab61..e8061d3ff 100644 --- a/src/cpu/inorder/resource_pool.hh +++ b/src/cpu/inorder/resource_pool.hh @@ -108,7 +108,7 @@ class ResourcePool { } /** Processes a resource event. */ - virtual void process(); + void process(); /** Returns the description of the resource event. */ const char *description(); diff --git a/src/cpu/inorder/resources/agen_unit.hh b/src/cpu/inorder/resources/agen_unit.hh index fbfd2f446..7c9c5fd89 100644 --- a/src/cpu/inorder/resources/agen_unit.hh +++ b/src/cpu/inorder/resources/agen_unit.hh @@ -49,7 +49,6 @@ class AGENUnit : public Resource { public: AGENUnit(std::string res_name, int res_id, int res_width, int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params); - virtual ~AGENUnit() {} enum Command { GenerateAddr diff --git a/src/cpu/inorder/resources/branch_predictor.hh b/src/cpu/inorder/resources/branch_predictor.hh index 7d0b3348a..00915fd0d 100644 --- a/src/cpu/inorder/resources/branch_predictor.hh +++ b/src/cpu/inorder/resources/branch_predictor.hh @@ -56,14 +56,14 @@ class BranchPredictor : public Resource { BranchPredictor(std::string res_name, int res_id, int res_width, int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params); - virtual void regStats(); + void regStats(); - virtual void execute(int slot_num); + void execute(int slot_num); - virtual void squash(DynInstPtr inst, int stage_num, + void squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num, ThreadID tid); - virtual void instGraduated(InstSeqNum seq_num, ThreadID tid); + void instGraduated(InstSeqNum seq_num, ThreadID tid); protected: /** List of instructions this resource is currently diff --git a/src/cpu/inorder/resources/cache_unit.hh b/src/cpu/inorder/resources/cache_unit.hh index 7e3052bd7..177f81559 100644 --- a/src/cpu/inorder/resources/cache_unit.hh +++ b/src/cpu/inorder/resources/cache_unit.hh @@ -101,30 +101,30 @@ class CacheUnit : public Resource protected: /** Atomic version of receive. Panics. */ - virtual Tick recvAtomic(PacketPtr pkt); + Tick recvAtomic(PacketPtr pkt); /** Functional version of receive. Panics. */ - virtual void recvFunctional(PacketPtr pkt); + void recvFunctional(PacketPtr pkt); /** Receives status change. Other than range changing, panics. */ - virtual void recvStatusChange(Status status); + void recvStatusChange(Status status); /** Returns the address ranges of this device. */ - virtual void getDeviceAddressRanges(AddrRangeList &resp, + void getDeviceAddressRanges(AddrRangeList &resp, AddrRangeList &snoop) { resp.clear(); snoop.clear(); } /** Timing version of receive. Handles setting fetch to the * proper status to start fetching. */ - virtual bool recvTiming(PacketPtr pkt); + bool recvTiming(PacketPtr pkt); /** Handles doing a retry of a failed fetch. */ - virtual void recvRetry(); + void recvRetry(); }; void init(); - virtual ResourceRequest* getRequest(DynInstPtr _inst, int stage_num, + ResourceRequest* getRequest(DynInstPtr _inst, int stage_num, int res_idx, int slot_num, unsigned cmd); @@ -238,7 +238,7 @@ class CacheUnitEvent : public ResourceEvent { virtual ~CacheUnitEvent() {} /** Processes a resource event. */ - virtual void process(); + void process(); }; class CacheRequest : public ResourceRequest diff --git a/src/cpu/inorder/resources/decode_unit.hh b/src/cpu/inorder/resources/decode_unit.hh index 1a700c211..1c4dc0523 100644 --- a/src/cpu/inorder/resources/decode_unit.hh +++ b/src/cpu/inorder/resources/decode_unit.hh @@ -49,13 +49,12 @@ class DecodeUnit : public Resource { public: DecodeUnit(std::string res_name, int res_id, int res_width, int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params); - virtual ~DecodeUnit() {} enum Command { DecodeInst }; - virtual void execute(int slot_num); + void execute(int slot_num); void squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num, ThreadID tid); diff --git a/src/cpu/inorder/resources/execution_unit.hh b/src/cpu/inorder/resources/execution_unit.hh index e852e3ed0..8be339f4a 100644 --- a/src/cpu/inorder/resources/execution_unit.hh +++ b/src/cpu/inorder/resources/execution_unit.hh @@ -54,13 +54,13 @@ class ExecutionUnit : public Resource { int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params); public: - virtual void regStats(); + void regStats(); /** Execute the function of this resource. The Default is action * is to do nothing. More specific models will derive from this * class and define their own execute function. */ - virtual void execute(int slot_num); + void execute(int slot_num); protected: ///////////////////////////////////////////////////////////////// diff --git a/src/cpu/inorder/resources/fetch_seq_unit.hh b/src/cpu/inorder/resources/fetch_seq_unit.hh index 289e150aa..aab462224 100644 --- a/src/cpu/inorder/resources/fetch_seq_unit.hh +++ b/src/cpu/inorder/resources/fetch_seq_unit.hh @@ -54,13 +54,13 @@ class FetchSeqUnit : public Resource { public: FetchSeqUnit(std::string res_name, int res_id, int res_width, int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params); - virtual ~FetchSeqUnit(); + ~FetchSeqUnit(); - virtual void init(); - virtual void activateThread(ThreadID tid); - virtual void deactivateThread(ThreadID tid); - virtual void suspendThread(ThreadID tid); - virtual void execute(int slot_num); + void init(); + void activateThread(ThreadID tid); + void deactivateThread(ThreadID tid); + void suspendThread(ThreadID tid); + void execute(int slot_num); void updateAfterContextSwitch(DynInstPtr inst, ThreadID tid); @@ -68,7 +68,7 @@ class FetchSeqUnit : public Resource { * looks in the global communication buffer to get squash * info */ - virtual void squash(DynInstPtr inst, int squash_stage, + void squash(DynInstPtr inst, int squash_stage, InstSeqNum squash_seq_num, ThreadID tid); @@ -110,10 +110,10 @@ class FetchSeqUnit : public Resource { public: /** Constructs a resource event. */ FetchSeqEvent(); - virtual ~FetchSeqEvent() {} + ~FetchSeqEvent() {} /** Processes a resource event. */ - virtual void process(); + void process(); }; }; diff --git a/src/cpu/inorder/resources/graduation_unit.hh b/src/cpu/inorder/resources/graduation_unit.hh index f53b6797f..aae41993f 100644 --- a/src/cpu/inorder/resources/graduation_unit.hh +++ b/src/cpu/inorder/resources/graduation_unit.hh @@ -53,9 +53,8 @@ class GraduationUnit : public Resource { GraduationUnit(std::string res_name, int res_id, int res_width, int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params); - virtual ~GraduationUnit() {} - virtual void execute(int slot_num); + void execute(int slot_num); protected: Tick lastCycleGrad; diff --git a/src/cpu/inorder/resources/inst_buffer.hh b/src/cpu/inorder/resources/inst_buffer.hh index b655e132f..fcbdc20df 100644 --- a/src/cpu/inorder/resources/inst_buffer.hh +++ b/src/cpu/inorder/resources/inst_buffer.hh @@ -57,21 +57,20 @@ class InstBuffer : public Resource { public: InstBuffer(std::string res_name, int res_id, int res_width, int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params); - virtual ~InstBuffer() {} - virtual void regStats(); + void regStats(); - virtual void execute(int slot_num); + void execute(int slot_num); - virtual void insert(DynInstPtr inst); + void insert(DynInstPtr inst); - virtual void remove(DynInstPtr inst); + void remove(DynInstPtr inst); - virtual void pop(ThreadID tid); + void pop(ThreadID tid); - virtual DynInstPtr top(ThreadID tid); + DynInstPtr top(ThreadID tid); - virtual void squash(DynInstPtr inst, int stage_num, + void squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num, ThreadID tid); protected: /** List of instructions this resource is currently diff --git a/src/cpu/inorder/resources/mult_div_unit.hh b/src/cpu/inorder/resources/mult_div_unit.hh index 555367504..d243eebea 100644 --- a/src/cpu/inorder/resources/mult_div_unit.hh +++ b/src/cpu/inorder/resources/mult_div_unit.hh @@ -63,24 +63,24 @@ class MultDivUnit : public Resource { /** Override default Resource getSlot(). Will only getSlot if * valid mult/div sequence is being maintained */ - virtual int getSlot(DynInstPtr inst); + int getSlot(DynInstPtr inst); - virtual int findSlot(DynInstPtr inst); + int findSlot(DynInstPtr inst); - virtual void freeSlot(int slot_idx); + void freeSlot(int slot_idx); - virtual void init(); + void init(); /** Get Operand Size For A Division Operation */ int getDivOpSize(DynInstPtr inst); /** Override default Resource execute */ - virtual void execute(int slot_num); + void execute(int slot_num); void exeMulDiv(int slot_num); /** Register extra resource stats */ - virtual void regStats(); + void regStats(); void requestAgain(DynInstPtr inst, bool &try_request); @@ -130,10 +130,10 @@ class MDUEvent : public ResourceEvent { public: MDUEvent(); - virtual ~MDUEvent() { } + ~MDUEvent() { } - virtual void process(); + void process(); }; diff --git a/src/cpu/inorder/resources/use_def.hh b/src/cpu/inorder/resources/use_def.hh index adfdd6ed3..d2cc55315 100644 --- a/src/cpu/inorder/resources/use_def.hh +++ b/src/cpu/inorder/resources/use_def.hh @@ -55,17 +55,16 @@ class UseDefUnit : public Resource { public: UseDefUnit(std::string res_name, int res_id, int res_width, int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params); - virtual ~UseDefUnit() {} - virtual ResourceRequest* getRequest(DynInstPtr _inst, int stage_num, + ResourceRequest* getRequest(DynInstPtr _inst, int stage_num, int res_idx, int slot_num, unsigned cmd); - virtual ResReqPtr findRequest(DynInstPtr inst); + ResReqPtr findRequest(DynInstPtr inst); - virtual void execute(int slot_num); + void execute(int slot_num); - virtual void squash(DynInstPtr inst, int stage_num, + void squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num, ThreadID tid); void updateAfterContextSwitch(DynInstPtr inst, ThreadID tid); diff --git a/src/cpu/inorder/thread_context.hh b/src/cpu/inorder/thread_context.hh index 99d9f5598..3ed2e7f50 100644 --- a/src/cpu/inorder/thread_context.hh +++ b/src/cpu/inorder/thread_context.hh @@ -75,193 +75,193 @@ class InOrderThreadContext : public ThreadContext System *getSystemPtr() { return cpu->system; } /** Returns a pointer to this CPU. */ - virtual BaseCPU *getCpuPtr() { return cpu; } + BaseCPU *getCpuPtr() { return cpu; } /** Returns a pointer to this CPU. */ - virtual std::string getCpuName() { return cpu->name(); } + std::string getCpuName() { return cpu->name(); } /** Reads this CPU's ID. */ - virtual int cpuId() { return cpu->cpuId(); } + int cpuId() { return cpu->cpuId(); } - virtual int contextId() { return thread->contextId(); } + int contextId() { return thread->contextId(); } - virtual void setContextId(int id) { thread->setContextId(id); } + void setContextId(int id) { thread->setContextId(id); } /** Returns this thread's ID number. */ - virtual int threadId() { return thread->threadId(); } - virtual void setThreadId(int id) { return thread->setThreadId(id); } + int threadId() { return thread->threadId(); } + void setThreadId(int id) { return thread->setThreadId(id); } - virtual uint64_t readMicroPC() + uint64_t readMicroPC() { return 0; } - virtual void setMicroPC(uint64_t val) { }; + void setMicroPC(uint64_t val) { }; - virtual uint64_t readNextMicroPC() + uint64_t readNextMicroPC() { return 0; } - virtual void setNextMicroPC(uint64_t val) { }; + void setNextMicroPC(uint64_t val) { }; #if FULL_SYSTEM /** Returns a pointer to physical memory. */ - virtual PhysicalMemory *getPhysMemPtr() + PhysicalMemory *getPhysMemPtr() { assert(0); return 0; /*return cpu->physmem;*/ } /** Returns a pointer to this thread's kernel statistics. */ - virtual TheISA::Kernel::Statistics *getKernelStats() + TheISA::Kernel::Statistics *getKernelStats() { return thread->kernelStats; } - virtual FunctionalPort *getPhysPort() { return thread->getPhysPort(); } + FunctionalPort *getPhysPort() { return thread->getPhysPort(); } - virtual VirtualPort *getVirtPort(); + VirtualPort *getVirtPort(); - virtual void connectMemPorts(ThreadContext *tc) + void connectMemPorts(ThreadContext *tc) { thread->connectMemPorts(tc); } /** Dumps the function profiling information. * @todo: Implement. */ - virtual void dumpFuncProfile(); + void dumpFuncProfile(); /** Reads the last tick that this thread was activated on. */ - virtual Tick readLastActivate(); + Tick readLastActivate(); /** Reads the last tick that this thread was suspended on. */ - virtual Tick readLastSuspend(); + Tick readLastSuspend(); /** Clears the function profiling information. */ - virtual void profileClear(); + void profileClear(); /** Samples the function profiling information. */ - virtual void profileSample(); + void profileSample(); /** Returns pointer to the quiesce event. */ - virtual EndQuiesceEvent *getQuiesceEvent() + EndQuiesceEvent *getQuiesceEvent() { return this->thread->quiesceEvent; } #else - virtual TranslatingPort *getMemPort() { return thread->getMemPort(); } + TranslatingPort *getMemPort() { return thread->getMemPort(); } /** Returns a pointer to this thread's process. */ - virtual Process *getProcessPtr() { return thread->getProcessPtr(); } + Process *getProcessPtr() { return thread->getProcessPtr(); } #endif /** Returns this thread's status. */ - virtual Status status() const { return thread->status(); } + Status status() const { return thread->status(); } /** Sets this thread's status. */ - virtual void setStatus(Status new_status) + void setStatus(Status new_status) { thread->setStatus(new_status); } /** Set the status to Active. Optional delay indicates number of * cycles to wait before beginning execution. */ - virtual void activate(int delay = 1); + void activate(int delay = 1); /** Set the status to Suspended. */ - virtual void suspend(int delay = 0); + void suspend(int delay = 0); /** Set the status to Halted. */ - virtual void halt(int delay = 0); + void halt(int delay = 0); /** Takes over execution of a thread from another CPU. */ - virtual void takeOverFrom(ThreadContext *old_context); + void takeOverFrom(ThreadContext *old_context); /** Registers statistics associated with this TC. */ - virtual void regStats(const std::string &name); + void regStats(const std::string &name); /** Serializes state. */ - virtual void serialize(std::ostream &os); + void serialize(std::ostream &os); /** Unserializes state. */ - virtual void unserialize(Checkpoint *cp, const std::string §ion); + void unserialize(Checkpoint *cp, const std::string §ion); /** Returns this thread's ID number. */ - virtual int getThreadNum() { return thread->readTid(); } + int getThreadNum() { return thread->readTid(); } /** Returns the instruction this thread is currently committing. * Only used when an instruction faults. */ - virtual TheISA::MachInst getInst(); + TheISA::MachInst getInst(); /** Copies the architectural registers from another TC into this TC. */ - virtual void copyArchRegs(ThreadContext *src_tc); + void copyArchRegs(ThreadContext *src_tc); /** Resets all architectural registers to 0. */ - virtual void clearArchRegs(); + void clearArchRegs(); /** Reads an integer register. */ - virtual uint64_t readIntReg(int reg_idx); + uint64_t readIntReg(int reg_idx); - virtual FloatReg readFloatReg(int reg_idx); + FloatReg readFloatReg(int reg_idx); - virtual FloatRegBits readFloatRegBits(int reg_idx); + FloatRegBits readFloatRegBits(int reg_idx); - virtual uint64_t readRegOtherThread(int misc_reg, ThreadID tid); + uint64_t readRegOtherThread(int misc_reg, ThreadID tid); /** Sets an integer register to a value. */ - virtual void setIntReg(int reg_idx, uint64_t val); + void setIntReg(int reg_idx, uint64_t val); - virtual void setFloatReg(int reg_idx, FloatReg val); + void setFloatReg(int reg_idx, FloatReg val); - virtual void setFloatRegBits(int reg_idx, FloatRegBits val); + void setFloatRegBits(int reg_idx, FloatRegBits val); - virtual void setRegOtherThread(int misc_reg, + void setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid); /** Reads this thread's PC. */ - virtual uint64_t readPC() + uint64_t readPC() { return cpu->readPC(thread->readTid()); } /** Sets this thread's PC. */ - virtual void setPC(uint64_t val); + void setPC(uint64_t val); /** Reads this thread's next PC. */ - virtual uint64_t readNextPC() + uint64_t readNextPC() { return cpu->readNextPC(thread->readTid()); } /** Sets this thread's next PC. */ - virtual void setNextPC(uint64_t val); + void setNextPC(uint64_t val); - virtual uint64_t readNextNPC() + uint64_t readNextNPC() { return cpu->readNextNPC(thread->readTid()); } - virtual void setNextNPC(uint64_t val); + void setNextNPC(uint64_t val); /** Reads a miscellaneous register. */ - virtual MiscReg readMiscRegNoEffect(int misc_reg) + MiscReg readMiscRegNoEffect(int misc_reg) { return cpu->readMiscRegNoEffect(misc_reg, thread->readTid()); } /** Reads a misc. register, including any side-effects the * read might have as defined by the architecture. */ - virtual MiscReg readMiscReg(int misc_reg) + MiscReg readMiscReg(int misc_reg) { return cpu->readMiscReg(misc_reg, thread->readTid()); } /** Sets a misc. register. */ - virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val); + void setMiscRegNoEffect(int misc_reg, const MiscReg &val); /** Sets a misc. register, including any side-effects the * write might have as defined by the architecture. */ - virtual void setMiscReg(int misc_reg, const MiscReg &val); + void setMiscReg(int misc_reg, const MiscReg &val); - virtual int flattenIntIndex(int reg) + int flattenIntIndex(int reg) { return cpu->isa[thread->readTid()].flattenIntIndex(reg); } - virtual int flattenFloatIndex(int reg) + int flattenFloatIndex(int reg) { return cpu->isa[thread->readTid()].flattenFloatIndex(reg); } - virtual void activateContext(int delay) + void activateContext(int delay) { cpu->activateContext(thread->readTid(), delay); } - virtual void deallocateContext() + void deallocateContext() { cpu->deallocateContext(thread->readTid()); } /** Returns the number of consecutive store conditional failures. */ // @todo: Figure out where these store cond failures should go. - virtual unsigned readStCondFailures() + unsigned readStCondFailures() { return thread->storeCondFailures; } /** Sets the number of consecutive store conditional failures. */ - virtual void setStCondFailures(unsigned sc_failures) + void setStCondFailures(unsigned sc_failures) { thread->storeCondFailures = sc_failures; } // Only really makes sense for old CPU model. Lots of code @@ -270,18 +270,18 @@ class InOrderThreadContext : public ThreadContext /** Checks if the thread is misspeculating. Because it is * very difficult to determine if the thread is * misspeculating, this is set as false. */ - virtual bool misspeculating() { return false; } + bool misspeculating() { return false; } #if !FULL_SYSTEM /** Executes a syscall in SE mode. */ - virtual void syscall(int64_t callnum) + void syscall(int64_t callnum) { return cpu->syscall(callnum, thread->readTid()); } #endif /** Reads the funcExeInst counter. */ - virtual Counter readFuncExeInst() { return thread->funcExeInst; } + Counter readFuncExeInst() { return thread->funcExeInst; } - virtual void changeRegFileContext(unsigned param, + void changeRegFileContext(unsigned param, unsigned val) { panic("Not supported!"); } };