CPU: Update where the simple cpus read their cpu id from the thread context to init() to make sure they read the right value. This fixes a bug with multi-processor full-system configurations.
--HG-- extra : convert_revision : 4f2801967a271b43817d88e147c2f80c4480b2c3
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3 changed files with 10 additions and 6 deletions
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@ -79,12 +79,13 @@ void
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AtomicSimpleCPU::init()
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AtomicSimpleCPU::init()
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{
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{
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BaseCPU::init();
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BaseCPU::init();
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cpuId = tc->readCpuId();
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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for (int i = 0; i < threadContexts.size(); ++i) {
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for (int i = 0; i < threadContexts.size(); ++i) {
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ThreadContext *tc = threadContexts[i];
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ThreadContext *tc = threadContexts[i];
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// initialize CPU, including PC
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// initialize CPU, including PC
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TheISA::initCPU(tc, tc->readCpuId());
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TheISA::initCPU(tc, cpuId);
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}
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}
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#endif
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#endif
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if (hasPhysMemPort) {
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if (hasPhysMemPort) {
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@ -93,6 +94,9 @@ AtomicSimpleCPU::init()
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physmemPort.getPeerAddressRanges(pmAddrList, snoop);
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physmemPort.getPeerAddressRanges(pmAddrList, snoop);
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physMemAddr = *pmAddrList.begin();
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physMemAddr = *pmAddrList.begin();
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}
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}
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ifetch_req.setThreadContext(cpuId, 0); // Add thread ID if we add MT
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data_read_req.setThreadContext(cpuId, 0); // Add thread ID here too
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data_write_req.setThreadContext(cpuId, 0); // Add thread ID here too
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}
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}
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bool
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bool
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@ -159,9 +163,6 @@ AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
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icachePort.snoopRangeSent = false;
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icachePort.snoopRangeSent = false;
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dcachePort.snoopRangeSent = false;
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dcachePort.snoopRangeSent = false;
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ifetch_req.setThreadContext(cpuId, 0); // Add thread ID if we add MT
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data_read_req.setThreadContext(cpuId, 0); // Add thread ID here too
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data_write_req.setThreadContext(cpuId, 0); // Add thread ID here too
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}
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}
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@ -240,6 +241,9 @@ AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
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}
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}
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assert(threadContexts.size() == 1);
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assert(threadContexts.size() == 1);
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cpuId = tc->readCpuId();
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cpuId = tc->readCpuId();
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ifetch_req.setThreadContext(cpuId, 0); // Add thread ID if we add MT
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data_read_req.setThreadContext(cpuId, 0); // Add thread ID here too
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data_write_req.setThreadContext(cpuId, 0); // Add thread ID here too
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}
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}
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@ -91,7 +91,6 @@ BaseSimpleCPU::BaseSimpleCPU(Params *p)
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threadContexts.push_back(tc);
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threadContexts.push_back(tc);
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cpuId = tc->readCpuId();
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fetchOffset = 0;
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fetchOffset = 0;
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stayAtPC = false;
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stayAtPC = false;
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@ -57,12 +57,13 @@ void
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TimingSimpleCPU::init()
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TimingSimpleCPU::init()
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{
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{
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BaseCPU::init();
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BaseCPU::init();
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cpuId = tc->readCpuId();
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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for (int i = 0; i < threadContexts.size(); ++i) {
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for (int i = 0; i < threadContexts.size(); ++i) {
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ThreadContext *tc = threadContexts[i];
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ThreadContext *tc = threadContexts[i];
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// initialize CPU, including PC
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// initialize CPU, including PC
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TheISA::initCPU(tc, tc->readCpuId());
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TheISA::initCPU(tc, cpuId);
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}
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}
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#endif
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#endif
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}
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}
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