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X86: Configure the first PCI interrupt.

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This commit is contained in:
Gabe Black 2009-02-01 00:26:10 -08:00
parent f1b43b39a7
commit 70cd5bfce5
3 changed files with 39 additions and 1 deletions
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31
configs/common/FSConfig.py
View file

@ -212,6 +212,19 @@ def makeX86System(mem_mode, mdesc = None, self = None):
self.intel_mp_table.add_entry(io_apic) self.intel_mp_table.add_entry(io_apic)
isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA') isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA')
self.intel_mp_table.add_entry(isa_bus) self.intel_mp_table.add_entry(isa_bus)
pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI')
self.intel_mp_table.add_entry(pci_bus)
connect_busses = X86IntelMPBusHierarchy(bus_id=0,
subtractive_decode=True, parent_bus=1)
self.intel_mp_table.add_entry(connect_busses)
pci_dev4_inta = X86IntelMPIOIntAssignment(
interrupt_type = 'INT',
polarity = 'ConformPolarity',
trigger = 'ConformTrigger',
source_bus_id = 1,
source_bus_irq = 0 + (4 << 2),
dest_io_apic_id = 1,
dest_io_apic_intin = 16)
assign_8259_0_to_apic = X86IntelMPIOIntAssignment( assign_8259_0_to_apic = X86IntelMPIOIntAssignment(
interrupt_type = 'ExtInt', interrupt_type = 'ExtInt',
polarity = 'ConformPolarity', polarity = 'ConformPolarity',
@ -266,6 +279,24 @@ def makeX86System(mem_mode, mdesc = None, self = None):
dest_io_apic_id = 1, dest_io_apic_id = 1,
dest_io_apic_intin = 12) dest_io_apic_intin = 12)
self.intel_mp_table.add_entry(assign_12_to_apic) self.intel_mp_table.add_entry(assign_12_to_apic)
assign_8259_14_to_apic = X86IntelMPIOIntAssignment(
interrupt_type = 'ExtInt',
polarity = 'ConformPolarity',
trigger = 'ConformTrigger',
source_bus_id = 0,
source_bus_irq = 14,
dest_io_apic_id = 1,
dest_io_apic_intin = 0)
self.intel_mp_table.add_entry(assign_8259_14_to_apic)
assign_14_to_apic = X86IntelMPIOIntAssignment(
interrupt_type = 'INT',
polarity = 'ConformPolarity',
trigger = 'ConformTrigger',
source_bus_id = 0,
source_bus_irq = 14,
dest_io_apic_id = 1,
dest_io_apic_intin = 14)
self.intel_mp_table.add_entry(assign_14_to_apic)
def makeLinuxX86System(mem_mode, mdesc = None): def makeLinuxX86System(mem_mode, mdesc = None):

3
src/dev/x86/SouthBridge.py
View file

@ -87,7 +87,8 @@ class SouthBridge(SimObject):
ide.BAR3LegacyIO = True ide.BAR3LegacyIO = True
ide.BAR4 = 1 ide.BAR4 = 1
ide.Command = 1 ide.Command = 1
ide.InterruptLine = 20 ide.InterruptLine = 14
ide.InterruptPin = 1
def attachIO(self, bus): def attachIO(self, bus):
# Route interupt signals # Route interupt signals

6
src/dev/x86/pc.cc
View file

@ -101,6 +101,12 @@ Pc::init()
entry.vector = 0x2C; entry.vector = 0x2C;
ioApic.writeReg(0x28, entry.bottomDW); ioApic.writeReg(0x28, entry.bottomDW);
ioApic.writeReg(0x29, entry.topDW); ioApic.writeReg(0x29, entry.topDW);
entry.vector = 0x2E;
ioApic.writeReg(0x2C, entry.bottomDW);
ioApic.writeReg(0x2D, entry.topDW);
entry.vector = 0x30;
ioApic.writeReg(0x30, entry.bottomDW);
ioApic.writeReg(0x31, entry.topDW);
} }
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