From 6fa713a66c380f38297e2306ec3d67e5fbb6f6c2 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 2 Jun 2010 12:58:11 -0500
Subject: [PATCH] ARM: Decode the setend instruction.

---
 src/arch/arm/isa/formats/data.isa   | 2 +-
 src/arch/arm/isa/formats/uncond.isa | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/arch/arm/isa/formats/data.isa b/src/arch/arm/isa/formats/data.isa
index 6fb698e75..19a9ee9fe 100644
--- a/src/arch/arm/isa/formats/data.isa
+++ b/src/arch/arm/isa/formats/data.isa
@@ -1024,7 +1024,7 @@ def format Thumb16Misc() {{
             {
                 const uint32_t opBits = bits(machInst, 7, 5);
                 if (opBits == 2) {
-                    return new WarnUnimplemented("setend", machInst);
+                    return new Setend(machInst, bits(machInst, 3));
                 } else if (opBits == 3) {
                     return new WarnUnimplemented("cps", machInst);
                 }
diff --git a/src/arch/arm/isa/formats/uncond.isa b/src/arch/arm/isa/formats/uncond.isa
index d305ee996..fd2f66e75 100644
--- a/src/arch/arm/isa/formats/uncond.isa
+++ b/src/arch/arm/isa/formats/uncond.isa
@@ -44,7 +44,7 @@ def format ArmUnconditional() {{
             const uint32_t op2 = bits(machInst, 7, 4);
             if (op1 == 0x10) {
                 if (bits((uint32_t)rn, 0) == 1 && op2 == 0) {
-                    return new WarnUnimplemented("setend", machInst);
+                    return new Setend(machInst, bits(machInst, 9));
                 } else if (bits((uint32_t)rn, 0) == 0 && bits(op2, 1) == 0) {
                     return new WarnUnimplemented("cps", machInst);
                 }