Merge zizzer.eecs.umich.edu:/bk/newmem
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-spec --HG-- extra : convert_revision : 50102b96ba07b2b132d649a111268ee1f08c2147
This commit is contained in:
commit
6ec510385d
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@ -154,6 +154,76 @@ def template ROrImmDecode {{
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}
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}};
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output header {{
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union DoubleSingle
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{
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double d;
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uint64_t ui;
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uint32_t s[2];
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DoubleSingle(double _d) : d(_d)
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{}
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DoubleSingle(uint64_t _ui) : ui(_ui)
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{}
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DoubleSingle(uint32_t _s0, uint32_t _s1)
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{
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s[0] = _s0;
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s[1] = _s1;
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}
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};
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}};
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let {{
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def filterDoubles(code):
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assignRE = re.compile(r'\s*=(?!=)', re.MULTILINE)
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for opName in ("Frd", "Frs1", "Frs2", "Frd_N"):
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next_pos = 0
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operandsREString = (r'''
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(?<![\w\.]) # neg. lookbehind assertion: prevent partial matches
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((%s)(?:\.(\w+))?) # match: operand with optional '.' then suffix
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(?![\w\.]) # neg. lookahead assertion: prevent partial matches
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''' % opName)
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operandsRE = re.compile(operandsREString, re.MULTILINE|re.VERBOSE)
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is_src = False
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is_dest = False
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extension = None
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foundOne = False
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while 1:
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match = operandsRE.search(code, next_pos)
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if not match:
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break
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foundOne = True
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op = match.groups()
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(op_full, op_base, op_ext) = op
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is_dest_local = (assignRE.match(code, match.end()) != None)
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is_dest = is_dest or is_dest_local
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is_src = is_src or not is_dest_local
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if extension and extension != op_ext:
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raise Exception, "Inconsistent extensions in double filter."
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extension = op_ext
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next_pos = match.end()
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if foundOne:
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# Get rid of any unwanted extension
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code = operandsRE.sub(op_base, code)
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is_int = False
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member = "d"
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if extension in ("sb", "ub", "shw", "uhw", "sw", "uw", "sdw", "udw"):
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is_int = True
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member = "ui"
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if is_src:
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code = ("%s = DoubleSingle(%s_high, %s_low).%s;" % \
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(opName, opName, opName, member)) + code
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if is_dest:
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code += '''
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%s_low = DoubleSingle(%s).s[1];
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%s_high = DoubleSingle(%s).s[0];''' % \
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(opName, opName, opName, opName)
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if is_int:
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code = ("uint64_t %s;" % opName) + code
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else:
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code = ("double %s;" % opName) + code
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return code
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}};
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let {{
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def splitOutImm(code):
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matcher = re.compile(r'Rs(?P<rNum>\d)_or_imm(?P<iNum>\d+)(?P<typeQual>\.\w+)?')
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@ -97,6 +97,7 @@ def template BasicDecodeWithMnemonic {{
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// The most basic instruction format... used only for a few misc. insts
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def format BasicOperate(code, *flags) {{
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code = filterDoubles(code)
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iop = InstObjParams(name, Name, 'SparcStaticInst', code, flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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@ -140,6 +141,7 @@ def format FpBasic(code, *flags) {{
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fesetround(oldrnd);
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#endif
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"""
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fp_code = filterDoubles(fp_code)
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iop = InstObjParams(name, Name, 'SparcStaticInst', fp_code, flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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@ -71,6 +71,7 @@ let {{
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}};
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def format LoadAlt(code, asi, *opt_flags) {{
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code = filterDoubles(code)
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(header_output,
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decoder_output,
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exec_output,
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@ -79,6 +80,7 @@ def format LoadAlt(code, asi, *opt_flags) {{
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}};
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def format StoreAlt(code, asi, *opt_flags) {{
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code = filterDoubles(code)
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(header_output,
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decoder_output,
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exec_output,
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@ -87,6 +89,7 @@ def format StoreAlt(code, asi, *opt_flags) {{
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}};
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def format Load(code, *opt_flags) {{
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code = filterDoubles(code)
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(header_output,
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decoder_output,
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exec_output,
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@ -95,6 +98,7 @@ def format Load(code, *opt_flags) {{
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}};
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def format Store(code, *opt_flags) {{
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code = filterDoubles(code)
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(header_output,
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decoder_output,
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exec_output,
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@ -317,6 +317,7 @@ let {{
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}};
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def format BlockLoad(code, asi, *opt_flags) {{
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code = filterDoubles(code)
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# We need to make sure to check the highest priority fault last.
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# That way, if other faults have been detected, they'll be overwritten
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# rather than the other way around.
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@ -329,6 +330,7 @@ def format BlockLoad(code, asi, *opt_flags) {{
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}};
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def format BlockStore(code, asi, *opt_flags) {{
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code = filterDoubles(code)
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# We need to make sure to check the highest priority fault last.
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# That way, if other faults have been detected, they'll be overwritten
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# rather than the other way around.
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@ -1,4 +1,4 @@
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// Copyright (c) 2006 The Regents of The University of Michigan
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// Copyright (c) 2006-2007 The Regents of The University of Michigan
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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@ -26,6 +26,33 @@
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//
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// Authors: Gabe Black
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//This delcares the initiateAcc function in memory operations
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def template MacroInitiateAcc {{
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Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const
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{
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panic("Tried to execute a macroop directly!\n");
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return NoFault;
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}
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}};
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def template MacroCompleteAcc {{
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Fault completeAcc(PacketPtr, %(CPU_exec_context)s *,
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Trace::InstRecord *) const
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{
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panic("Tried to execute a macroop directly!\n");
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return NoFault;
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}
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}};
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//This template provides the execute functions for a store
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def template MacroExecute {{
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Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
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{
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panic("Tried to execute a macroop directly!\n");
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return NoFault;
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}
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}};
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output header {{
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class SparcMacroInst : public SparcStaticInst
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@ -60,7 +87,9 @@ output header {{
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return microOps[microPC];
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}
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%(BasicExecPanic)s
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%(MacroExecute)s
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%(MacroInitiateAcc)s
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%(MacroCompleteAcc)s
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};
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class SparcMicroInst : public SparcStaticInst
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@ -52,6 +52,16 @@ output header {{
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{
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return (regNum & (~1)) | ((regNum & 1) << 5);
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}
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static inline unsigned int dfprl(unsigned int regNum)
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{
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return dfpr(regNum) & (~0x1);
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}
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static inline unsigned int dfprh(unsigned int regNum)
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{
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return dfpr(regNum) | 0x1;
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}
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}};
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def operands {{
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# differently, they get different operands. The single precision versions
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# have an s post pended to their name.
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'Frds': ('FloatReg', 'sf', 'RD', 'IsFloating', 10),
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'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
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#'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
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'Frd_low': ('FloatReg', 'uw', 'dfprl(RD)', 'IsFloating', 10),
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'Frd_high': ('FloatReg', 'uw', 'dfprh(RD)', 'IsFloating', 10),
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# Each Frd_N refers to the Nth double precision register from Frd.
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# Note that this adds twice N to the register number.
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'Frd_0': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
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'Frd_1': ('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10),
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'Frd_2': ('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10),
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'Frd_3': ('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10),
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'Frd_4': ('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10),
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'Frd_5': ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10),
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'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10),
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'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10),
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#'Frd_0': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
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'Frd_0_low': ('FloatReg', 'uw', 'dfprl(RD)', 'IsFloating', 10),
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'Frd_0_high': ('FloatReg', 'uw', 'dfprh(RD)', 'IsFloating', 10),
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#'Frd_1': ('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10),
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'Frd_1_low': ('FloatReg', 'uw', 'dfprl(RD) + 2', 'IsFloating', 10),
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'Frd_1_high': ('FloatReg', 'uw', 'dfprh(RD) + 2', 'IsFloating', 10),
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#'Frd_2': ('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10),
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'Frd_2_low': ('FloatReg', 'uw', 'dfprl(RD) + 4', 'IsFloating', 10),
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'Frd_2_high': ('FloatReg', 'uw', 'dfprh(RD) + 4', 'IsFloating', 10),
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#'Frd_3': ('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10),
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'Frd_3_low': ('FloatReg', 'uw', 'dfprl(RD) + 6', 'IsFloating', 10),
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'Frd_3_high': ('FloatReg', 'uw', 'dfprh(RD) + 6', 'IsFloating', 10),
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#'Frd_4': ('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10),
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'Frd_4_low': ('FloatReg', 'uw', 'dfprl(RD) + 8', 'IsFloating', 10),
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'Frd_4_high': ('FloatReg', 'uw', 'dfprh(RD) + 8', 'IsFloating', 10),
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#'Frd_5': ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10),
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'Frd_5_low': ('FloatReg', 'uw', 'dfprl(RD) + 10', 'IsFloating', 10),
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'Frd_5_high': ('FloatReg', 'uw', 'dfprh(RD) + 10', 'IsFloating', 10),
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#'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10),
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'Frd_6_low': ('FloatReg', 'uw', 'dfprl(RD) + 12', 'IsFloating', 10),
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'Frd_6_high': ('FloatReg', 'uw', 'dfprh(RD) + 12', 'IsFloating', 10),
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#'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10),
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'Frd_7_low': ('FloatReg', 'uw', 'dfprl(RD) + 14', 'IsFloating', 10),
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'Frd_7_high': ('FloatReg', 'uw', 'dfprh(RD) + 14', 'IsFloating', 10),
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'Frs1s': ('FloatReg', 'sf', 'RS1', 'IsFloating', 11),
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'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11),
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#'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11),
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'Frs1_low': ('FloatReg', 'uw', 'dfprl(RS1)', 'IsFloating', 11),
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'Frs1_high': ('FloatReg', 'uw', 'dfprh(RS1)', 'IsFloating', 11),
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'Frs2s': ('FloatReg', 'sf', 'RS2', 'IsFloating', 12),
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'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12),
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#'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12),
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'Frs2_low': ('FloatReg', 'uw', 'dfprl(RS2)', 'IsFloating', 12),
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'Frs2_high': ('FloatReg', 'uw', 'dfprh(RS2)', 'IsFloating', 12),
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'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 31),
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'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 32),
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# Registers which are used explicitly in instructions
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