CPU: Fix a case where timing simple cpu faults can nest.
If we fault, change the state to faulting so that we don't fault again in the same cycle.
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89e7bcca82
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6e634beb8a
2 changed files with 17 additions and 5 deletions
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@ -124,6 +124,7 @@ class BaseSimpleCPU : public BaseCPU
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enum Status {
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Idle,
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Running,
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Faulting,
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ITBWaitResponse,
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IcacheRetry,
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IcacheWaitResponse,
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@ -725,6 +725,7 @@ TimingSimpleCPU::fetch()
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bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst;
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if (needToFetch) {
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_status = Running;
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Request *ifetch_req = new Request();
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ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0);
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setupFetchRequest(ifetch_req);
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@ -771,7 +772,20 @@ TimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc)
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void
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TimingSimpleCPU::advanceInst(Fault fault)
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{
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if (fault != NoFault || !stayAtPC)
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if (_status == Faulting)
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return;
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if (fault != NoFault) {
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advancePC(fault);
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DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n");
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reschedule(fetchEvent, nextCycle(), true);
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_status = Faulting;
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return;
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}
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if (!stayAtPC)
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advancePC(fault);
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if (_status == Running) {
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@ -786,8 +800,6 @@ TimingSimpleCPU::advanceInst(Fault fault)
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void
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TimingSimpleCPU::completeIfetch(PacketPtr pkt)
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{
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DPRINTF(SimpleCPU, "Complete ICache Fetch\n");
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// received a response from the icache: execute the received
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// instruction
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@ -878,8 +890,7 @@ TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
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tickEvent.schedule(pkt, next_tick);
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return true;
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}
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else if (pkt->wasNacked()) {
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} else if (pkt->wasNacked()) {
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assert(cpu->_status == IcacheWaitResponse);
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pkt->reinitNacked();
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if (!sendTiming(pkt)) {
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