cpu: Initialize the O3 pipeline from startup()

The entire O3 pipeline used to be initialized from init(), which is
called before initState() or unserialize(). This causes the pipeline
to be initialized from an incorrect thread context. This doesn't
currently lead to correctness problems as instructions fetched from
the incorrect start PC will be squashed a few cycles after
initialization.

This patch will affect the regressions since the O3 CPU now issues its
first instruction fetch to the correct PC instead of 0x0.
This commit is contained in:
Andreas Sandberg 2013-01-07 13:05:44 -05:00
parent e2dad8236a
commit 6daada2701
10 changed files with 23 additions and 17 deletions

View file

@ -195,7 +195,7 @@ class DefaultCommit
void setROB(ROB *rob_ptr); void setROB(ROB *rob_ptr);
/** Initializes stage by sending back the number of free entries. */ /** Initializes stage by sending back the number of free entries. */
void initStage(); void startupStage();
/** Initializes the draining of commit. */ /** Initializes the draining of commit. */
bool drain(); bool drain();

View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2010-2011 ARM Limited * Copyright (c) 2010-2012 ARM Limited
* All rights reserved * All rights reserved
* *
* The license below extends only to copyright in the software and shall * The license below extends only to copyright in the software and shall
@ -348,7 +348,7 @@ DefaultCommit<Impl>::setROB(ROB *rob_ptr)
template <class Impl> template <class Impl>
void void
DefaultCommit<Impl>::initStage() DefaultCommit<Impl>::startupStage()
{ {
rob->setActiveThreads(activeThreads); rob->setActiveThreads(activeThreads);
rob->resetEntries(); rob->resetEntries();

View file

@ -679,15 +679,19 @@ FullO3CPU<Impl>::init()
for (int tid = 0; tid < numThreads; ++tid) for (int tid = 0; tid < numThreads; ++tid)
thread[tid]->noSquashFromTC = false; thread[tid]->noSquashFromTC = false;
// Initialize stages.
fetch.initStage();
iew.initStage();
rename.initStage();
commit.initStage();
commit.setThreads(thread); commit.setThreads(thread);
} }
template <class Impl>
void
FullO3CPU<Impl>::startup()
{
fetch.startupStage();
iew.startupStage();
rename.startupStage();
commit.startupStage();
}
template <class Impl> template <class Impl>
void void
FullO3CPU<Impl>::activateThread(ThreadID tid) FullO3CPU<Impl>::activateThread(ThreadID tid)

View file

@ -369,6 +369,8 @@ class FullO3CPU : public BaseO3CPU
/** Initialize the CPU */ /** Initialize the CPU */
void init(); void init();
void startup();
/** Returns the Number of Active Threads in the CPU */ /** Returns the Number of Active Threads in the CPU */
int numActiveThreads() int numActiveThreads()
{ return activeThreads.size(); } { return activeThreads.size(); }

View file

@ -215,7 +215,7 @@ class DefaultFetch
void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
/** Initialize stage. */ /** Initialize stage. */
void initStage(); void startupStage();
/** Tells the fetch stage that the Icache is set. */ /** Tells the fetch stage that the Icache is set. */
void setIcache(); void setIcache();

View file

@ -302,7 +302,7 @@ DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
template<class Impl> template<class Impl>
void void
DefaultFetch<Impl>::initStage() DefaultFetch<Impl>::startupStage()
{ {
// Setup PC and nextPC with initial state. // Setup PC and nextPC with initial state.
for (ThreadID tid = 0; tid < numThreads; tid++) { for (ThreadID tid = 0; tid < numThreads; tid++) {

View file

@ -133,7 +133,7 @@ class DefaultIEW
void regStats(); void regStats();
/** Initializes stage; sends back the number of free IQ and LSQ entries. */ /** Initializes stage; sends back the number of free IQ and LSQ entries. */
void initStage(); void startupStage();
/** Sets main time buffer used for backwards communication. */ /** Sets main time buffer used for backwards communication. */
void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);

View file

@ -283,7 +283,7 @@ DefaultIEW<Impl>::regStats()
template<class Impl> template<class Impl>
void void
DefaultIEW<Impl>::initStage() DefaultIEW<Impl>::startupStage()
{ {
for (ThreadID tid = 0; tid < numThreads; tid++) { for (ThreadID tid = 0; tid < numThreads; tid++) {
toRename->iewInfo[tid].usedIQ = true; toRename->iewInfo[tid].usedIQ = true;
@ -408,7 +408,7 @@ DefaultIEW<Impl>::takeOverFrom()
ldstQueue.takeOverFrom(); ldstQueue.takeOverFrom();
fuPool->takeOver(); fuPool->takeOver();
initStage(); startupStage();
cpu->activityThisCycle(); cpu->activityThisCycle();
for (ThreadID tid = 0; tid < numThreads; tid++) { for (ThreadID tid = 0; tid < numThreads; tid++) {

View file

@ -143,7 +143,7 @@ class DefaultRename
public: public:
/** Initializes variables for the stage. */ /** Initializes variables for the stage. */
void initStage(); void startupStage();
/** Sets pointer to list of active threads. */ /** Sets pointer to list of active threads. */
void setActiveThreads(std::list<ThreadID> *at_ptr); void setActiveThreads(std::list<ThreadID> *at_ptr);

View file

@ -228,7 +228,7 @@ DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
template <class Impl> template <class Impl>
void void
DefaultRename<Impl>::initStage() DefaultRename<Impl>::startupStage()
{ {
// Grab the number of free entries directly from the stages. // Grab the number of free entries directly from the stages.
for (ThreadID tid = 0; tid < numThreads; tid++) { for (ThreadID tid = 0; tid < numThreads; tid++) {
@ -317,7 +317,7 @@ void
DefaultRename<Impl>::takeOverFrom() DefaultRename<Impl>::takeOverFrom()
{ {
_status = Inactive; _status = Inactive;
initStage(); startupStage();
// Reset all state prior to taking over from the other CPU. // Reset all state prior to taking over from the other CPU.
for (ThreadID tid = 0; tid < numThreads; tid++) { for (ThreadID tid = 0; tid < numThreads; tid++) {