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Fixed up the isa description. Also added some capability to the isa_parser in the InstObjParams constructor.

Browse source 
arch/isa_parser.py:
    Expanded the capability of the InstObjParams constructor to allow adding in extra keys for use in templates. These are added as key, value tuples as optional arguements.
arch/sparc/isa/base.isa:
arch/sparc/isa/formats/mem.isa:
arch/sparc/isa/formats/priv.isa:
    The genCompositeIop function is no longer needed, as this functionality is now in the InstObjParams constructor.
arch/sparc/isa/decoder.isa:
    Fixed up alot of instructions, and fixed indentation.
arch/sparc/isa/formats/integerop.isa:
    The genCompositeIop function is no longer needed, as this functionality is now in the InstObjParams constructor. Also changed the immediate values to be signed.
base/traceflags.py:
    Added SPARC traceflag
configs/test/hello_sparc:
    Recompiled without -mflat
cpu/cpu_exec_context.cc:
    Used the regfile clear function rather than memsetting to 0.

--HG--
extra : convert_revision : b9da6f264f3ebc4ce1815008dfff7f476b247ee9
This commit is contained in:
Gabe Black 2006-04-06 14:52:44 -04:00
parent a4b31e8f6b
commit 6d8d6d15cd
9 changed files with 490 additions and 411 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

22
arch/isa_parser.py
View file

@ -1618,13 +1618,27 @@ opClassRE = re.compile(r'.*Op|No_OpClass')
class InstObjParams: class InstObjParams:
def __init__(self, mnem, class_name, base_class = '', def __init__(self, mnem, class_name, base_class = '',
code_block = None, opt_args = []): code = None, opt_args = [], *extras):
self.mnemonic = mnem self.mnemonic = mnem
self.class_name = class_name self.class_name = class_name
self.base_class = base_class self.base_class = base_class
if code_block: if code:
for code_attr in code_block.__dict__.keys(): #If the user already made a CodeBlock, pick the parts from it
setattr(self, code_attr, getattr(code_block, code_attr)) if isinstance(code, CodeBlock):
origCode = code.orig_code
codeBlock = code
else:
origCode = code
codeBlock = CodeBlock(code)
compositeCode = '\n'.join([origCode] +
[pair[1] for pair in extras])
compositeBlock = CodeBlock(compositeCode)
for code_attr in compositeBlock.__dict__.keys():
setattr(self, code_attr, getattr(compositeBlock, code_attr))
for (key, snippet) in extras:
setattr(self, key, CodeBlock(snippet).code)
self.code = codeBlock.code
self.orig_code = origCode
else: else:
self.constructor = '' self.constructor = ''
self.flags = [] self.flags = []

15
arch/sparc/isa/base.isa
View file

@ -60,7 +60,7 @@ output header {{
inline int64_t sign_ext(uint64_t data, int origWidth) inline int64_t sign_ext(uint64_t data, int origWidth)
{ {
int shiftAmount = sizeof(uint64_t) - origWidth; int shiftAmount = 64 - origWidth;
return (((int64_t)data) << shiftAmount) >> shiftAmount; return (((int64_t)data) << shiftAmount) >> shiftAmount;
} }
}}; }};
@ -84,19 +84,6 @@ let {{
code = matcher.sub('Rs' + rOrImmMatch.group("rNum"), orig_code) code = matcher.sub('Rs' + rOrImmMatch.group("rNum"), orig_code)
imm_code = matcher.sub('imm', orig_code) imm_code = matcher.sub('imm', orig_code)
return (True, code, imm_code, rString, iString) return (True, code, imm_code, rString, iString)
def genCompositeIop(code, name, Name, parent, opt_flags, **extras):
origBlock = CodeBlock(code)
composite = code
for snippet in extras.values():
composite += ('\n' + snippet)
compositeBlock = CodeBlock(composite)
iop = InstObjParams(name, Name, parent, compositeBlock, opt_flags)
iop.code = origBlock.code
iop.orig_code = origBlock.orig_code
for (name, snippet) in extras.items():
exec "iop.%s = CodeBlock(snippet).code" % name
return iop
}}; }};
output decoder {{ output decoder {{

698
arch/sparc/isa/decoder.isa
View file

@ -14,7 +14,6 @@ decode OP default Unknown::unknown()
format Branch19 format Branch19
{ {
0x0: bpcci({{ 0x0: bpcci({{
NNPC = xc->readNextNPC();
if(passesCondition(CcrIcc, COND2)) if(passesCondition(CcrIcc, COND2))
NNPC = xc->readPC() + disp; NNPC = xc->readPC() + disp;
}}); }});
@ -64,7 +63,6 @@ decode OP default Unknown::unknown()
0x6: Trap::fbfcc({{fault = new FpDisabled;}}); 0x6: Trap::fbfcc({{fault = new FpDisabled;}});
} }
0x1: Branch30::call({{ 0x1: Branch30::call({{
//branch here
R15 = xc->readPC(); R15 = xc->readPC();
NNPC = R15 + disp; NNPC = R15 + disp;
}}); }});
@ -74,7 +72,7 @@ decode OP default Unknown::unknown()
0x01: and({{Rd = Rs1.udw & Rs2_or_imm13;}}); 0x01: and({{Rd = Rs1.udw & Rs2_or_imm13;}});
0x02: or({{Rd = Rs1.udw | Rs2_or_imm13;}}); 0x02: or({{Rd = Rs1.udw | Rs2_or_imm13;}});
0x03: xor({{Rd = Rs1.udw ^ Rs2_or_imm13;}}); 0x03: xor({{Rd = Rs1.udw ^ Rs2_or_imm13;}});
0x04: sub({{Rd = Rs1.sdw + (~Rs2_or_imm13)+1;}}); 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}});
0x05: andn({{Rd = Rs1.udw & ~Rs2_or_imm13;}}); 0x05: andn({{Rd = Rs1.udw & ~Rs2_or_imm13;}});
0x06: orn({{Rd = Rs1.udw | ~Rs2_or_imm13;}}); 0x06: orn({{Rd = Rs1.udw | ~Rs2_or_imm13;}});
0x07: xnor({{Rd = ~(Rs1.udw ^ Rs2_or_imm13);}}); 0x07: xnor({{Rd = ~(Rs1.udw ^ Rs2_or_imm13);}});
@ -113,7 +111,7 @@ decode OP default Unknown::unknown()
else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF) else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF)
Rd.udw = 0xFFFFFFFF80000000; Rd.udw = 0xFFFFFFFF80000000;
} }
}});//SDIV }});
} }
format IntOpCc { format IntOpCc {
0x10: addcc({{ 0x10: addcc({{
@ -123,19 +121,19 @@ decode OP default Unknown::unknown()
{{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
{{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
);//ADDcc );
0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}}); 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}});
0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}}); 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}});
0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}}); 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}});
0x14: subcc({{ 0x14: subcc({{
int64_t resTemp, val2 = Rs2_or_imm13; int64_t resTemp, val2 = Rs2_or_imm13;
Rd = resTemp = Rs1 - val2;}}, Rd = resTemp = Rs1 - val2;}},
{{((Rs1 & 0xFFFFFFFF + (~val2) & 0xFFFFFFFF + 1) >> 31)}}, {{((Rs1 & 0xFFFFFFFF - val2 & 0xFFFFFFFF) >> 31)}},
{{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}}, {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
{{(((Rs1 >> 1) + (~val2) >> 1) + {{(((Rs1 >> 1) + (~val2) >> 1) +
((Rs1 | ~val2) & 0x1))<63:>}}, ((Rs1 | ~val2) & 0x1))<63:>}},
{{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}} {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
);//SUBcc );
0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}}); 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}});
0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}}); 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}});
0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}}); 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}});
@ -149,17 +147,17 @@ decode OP default Unknown::unknown()
{{((Rs1 >> 1) + (val2 >> 1) + {{((Rs1 >> 1) + (val2 >> 1) +
((Rs1 & val2) | (carryin & (Rs1 | val2)) & 0x1))<63:>}}, ((Rs1 & val2) | (carryin & (Rs1 | val2)) & 0x1))<63:>}},
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
);//ADDCcc );
0x1A: umulcc({{ 0x1A: umulcc({{
uint64_t resTemp, val2 = Rs2_or_imm13; uint64_t resTemp, val2 = Rs2_or_imm13;
Rd = resTemp = Rs1.udw<31:0> * val2<31:0>; Rd = resTemp = Rs1.udw<31:0> * val2<31:0>;
YValue = resTemp<63:32>;}}, YValue = resTemp<63:32>;}},
{{0}},{{0}},{{0}},{{0}});//UMULcc {{0}},{{0}},{{0}},{{0}});
0x1B: smulcc({{ 0x1B: smulcc({{
int64_t resTemp, val2 = Rs2_or_imm13; int64_t resTemp, val2 = Rs2_or_imm13;
Rd = resTemp = Rs1.sdw<31:0> * val2<31:0>; Rd = resTemp = Rs1.sdw<31:0> * val2<31:0>;
YValue = resTemp<63:32>;}} YValue = resTemp<63:32>;}},
,{{0}},{{0}},{{0}},{{0}});//SMULcc {{0}},{{0}},{{0}},{{0}});
0x1C: subccc({{ 0x1C: subccc({{
int64_t resTemp, val2 = Rs2_or_imm13; int64_t resTemp, val2 = Rs2_or_imm13;
int64_t carryin = CcrIccC; int64_t carryin = CcrIccC;
@ -168,11 +166,11 @@ decode OP default Unknown::unknown()
{{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}}, {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
{{(((Rs1 >> 1) + (~(val2 + carryin)) >> 1) + ((Rs1 | ~(val2+carryin)) & 0x1))<63:>}}, {{(((Rs1 >> 1) + (~(val2 + carryin)) >> 1) + ((Rs1 | ~(val2+carryin)) & 0x1))<63:>}},
{{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}} {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
);//SUBCcc );
0x1D: udivxcc({{ 0x1D: udivxcc({{
if(Rs2_or_imm13 == 0) fault = new DivisionByZero; if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
else Rd = Rs1.udw / Rs2_or_imm13;}} else Rd = Rs1.udw / Rs2_or_imm13;}}
,{{0}},{{0}},{{0}},{{0}});//UDIVXcc ,{{0}},{{0}},{{0}},{{0}});
0x1E: udivcc({{ 0x1E: udivcc({{
uint32_t resTemp, val2 = Rs2_or_imm13; uint32_t resTemp, val2 = Rs2_or_imm13;
int32_t overflow; int32_t overflow;
@ -188,7 +186,7 @@ decode OP default Unknown::unknown()
{{overflow}}, {{overflow}},
{{0}}, {{0}},
{{0}} {{0}}
);//UDIVcc );
0x1F: sdivcc({{ 0x1F: sdivcc({{
int32_t resTemp, val2 = Rs2_or_imm13; int32_t resTemp, val2 = Rs2_or_imm13;
int32_t overflow, underflow; int32_t overflow, underflow;
@ -206,7 +204,7 @@ decode OP default Unknown::unknown()
{{overflow || underflow}}, {{overflow || underflow}},
{{0}}, {{0}},
{{0}} {{0}}
);//SDIVcc );
0x20: taddcc({{ 0x20: taddcc({{
int64_t resTemp, val2 = Rs2_or_imm13; int64_t resTemp, val2 = Rs2_or_imm13;
Rd = resTemp = Rs1 + val2; Rd = resTemp = Rs1 + val2;
@ -215,7 +213,7 @@ decode OP default Unknown::unknown()
{{overflow}}, {{overflow}},
{{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
);//TADDcc );
0x21: tsubcc({{ 0x21: tsubcc({{
int64_t resTemp, val2 = Rs2_or_imm13; int64_t resTemp, val2 = Rs2_or_imm13;
Rd = resTemp = Rs1 + val2; Rd = resTemp = Rs1 + val2;
@ -224,7 +222,7 @@ decode OP default Unknown::unknown()
{{overflow}}, {{overflow}},
{{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
);//TSUBcc );
0x22: taddcctv({{ 0x22: taddcctv({{
int64_t resTemp, val2 = Rs2_or_imm13; int64_t resTemp, val2 = Rs2_or_imm13;
Rd = resTemp = Rs1 + val2; Rd = resTemp = Rs1 + val2;
@ -234,7 +232,7 @@ decode OP default Unknown::unknown()
{{overflow}}, {{overflow}},
{{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
);//TADDccTV );
0x23: tsubcctv({{ 0x23: tsubcctv({{
int64_t resTemp, val2 = Rs2_or_imm13; int64_t resTemp, val2 = Rs2_or_imm13;
Rd = resTemp = Rs1 + val2; Rd = resTemp = Rs1 + val2;
@ -244,7 +242,7 @@ decode OP default Unknown::unknown()
{{overflow}}, {{overflow}},
{{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
);//TSUBccTV );
0x24: mulscc({{ 0x24: mulscc({{
int64_t resTemp, multiplicand = Rs2_or_imm13; int64_t resTemp, multiplicand = Rs2_or_imm13;
int32_t multiplier = Rs1<31:0>; int32_t multiplier = Rs1<31:0>;
@ -260,305 +258,387 @@ decode OP default Unknown::unknown()
{{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}}, {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}},
{{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}}, {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}},
{{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}} {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}}
);//MULScc );
}
format IntOp
{
0x25: decode X {
0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}});
0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}});
} }
format IntOp 0x26: decode X {
0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}});
0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});
}
0x27: decode X {
0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}});
0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
}
0x28: decode RS1 {
0x0: rdy({{Rd = YValue;}});
0x2: rdccr({{Rd = Ccr;}});
0x3: rdasi({{Rd = Asi;}});
0x4: PrivTick::rdtick({{Rd = Tick;}});
0x5: rdpc({{Rd = xc->readPC();}});
0x6: rdfprs({{Rd = Fprs;}});
0xF: decode I {
0x0: Nop::membar({{/*Membar isn't needed yet*/}});
0x1: Nop::stbar({{/*Stbar isn't needed yet*/}});
}
}
0x2A: decode RS1 {
format Priv
{
0x0: rdprtpc({{
Rd = xc->readMiscReg(MISCREG_TPC_BASE + Tl);
}});
0x1: rdprtnpc({{
Rd = xc->readMiscReg(MISCREG_TNPC_BASE + Tl);
}});
0x2: rdprtstate({{
Rd = xc->readMiscReg(MISCREG_TSTATE_BASE + Tl);
}});
0x3: rdprtt({{
Rd = xc->readMiscReg(MISCREG_TT_BASE + Tl);
}});
0x4: rdprtick({{Rd = Tick;}});
0x5: rdprtba({{Rd = Tba;}});
0x6: rdprpstate({{Rd = Pstate;}});
0x7: rdprtl({{Rd = Tl;}});
0x8: rdprpil({{Rd = Pil;}});
0x9: rdprcwp({{Rd = Cwp;}});
0xA: rdprcansave({{Rd = Cansave;}});
0xB: rdprcanrestore({{Rd = Canrestore;}});
0xC: rdprcleanwin({{Rd = Cleanwin;}});
0xD: rdprotherwin({{Rd = Otherwin;}});
0xE: rdprwstate({{Rd = Wstate;}});
}
//The floating point queue isn't implemented right now.
0xF: Trap::rdprfq({{fault = new IllegalInstruction;}});
0x1F: Priv::rdprver({{Rd = Ver;}});
}
0x2B: BasicOperate::flushw({{
if(NWindows - 2 - Cansave == 0)
{
if(Otherwin)
fault = new SpillNOther(WstateOther);
else
fault = new SpillNNormal(WstateNormal);
}
}});
0x2C: decode MOVCC3
{ {
0x25: decode X { 0x0: Trap::movccfcc({{fault = new FpDisabled;}});
0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); 0x1: decode CC
0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}});
}
0x26: decode X {
0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}});
0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});
}
0x27: decode X {
0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}}); //SRA
0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});//SRAX
}
0x28: decode RS1 {
0x0: rdy({{Rd = YValue;}}); //RDY
0x2: rdccr({{Rd = Ccr;}}); //RDCCR
0x3: rdasi({{Rd = Asi;}}); //RDASI
0x4: PrivTick::rdtick({{Rd = Tick;}});
0x5: rdpc({{Rd = xc->readPC();}}); //RDPC
0x6: rdfprs({{Rd = Fprs;}}); //RDFPRS
0xF: decode I {
0x0: Nop::membar({{/*Membar isn't needed yet*/}});
0x1: Nop::stbar({{/*Stbar isn't needed yet*/}});
}
}
0x2A: decode RS1 {
format Priv
{
0x0: rdprtpc({{
Rd = xc->readMiscReg(MISCREG_TPC_BASE + Tl);
}});
0x1: rdprtnpc({{
Rd = xc->readMiscReg(MISCREG_TNPC_BASE + Tl);
}});
0x2: rdprtstate({{
Rd = xc->readMiscReg(MISCREG_TSTATE_BASE + Tl);
}});
0x3: rdprtt({{
Rd = xc->readMiscReg(MISCREG_TT_BASE + Tl);
}});
0x4: rdprtick({{Rd = Tick;}});
0x5: rdprtba({{Rd = Tba;}});
0x6: rdprpstate({{Rd = Pstate;}});
0x7: rdprtl({{Rd = Tl;}});
0x8: rdprpil({{Rd = Pil;}});
0x9: rdprcwp({{Rd = Cwp;}});
0xA: rdprcansave({{Rd = Cansave;}});
0xB: rdprcanrestore({{Rd = Canrestore;}});
0xC: rdprcleanwin({{Rd = Cleanwin;}});
0xD: rdprotherwin({{Rd = Otherwin;}});
0xE: rdprwstate({{Rd = Wstate;}});
}
//The floating point queue isn't implemented right now.
0xF: Trap::rdprfq({{fault = new IllegalInstruction;}});
0x1F: Priv::rdprver({{Rd = Ver;}});
}
0x2B: BasicOperate::flushw({{/*window toilet*/}});
0x2C: decode MOVCC3
{ {
0x0: Trap::movccfcc({{fault = new FpDisabled;}}); 0x0: movcci({{
0x1: decode CC if(passesCondition(CcrIcc, COND4))
{ Rd = (I ? SIMM11 : RS2);
0x0: movcci({{
if(passesCondition(CcrIcc, COND4))
Rd = (I ? SIMM11 : RS2);
}});
0x2: movccx({{
if(passesCondition(CcrXcc, COND4))
Rd = (I ? SIMM11 : RS2);
}});
}
}
0x2D: sdivx({{
if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
else Rd.sdw = Rs1.sdw / Rs2_or_imm13;
}});//SDIVX
0x2E: decode RS1 {
0x0: IntOp::popc({{
int64_t count = 0;
uint64_t temp = Rs2_or_imm13;
//Count the 1s in the front 4bits until none are left
uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4};
while(temp)
{
count += oneBits[temp & 0xF];
temp = temp >> 4;
}
}});//POPC
}
0x2F: decode RCOND3
{
0x1: movreq({{if(Rs1 == 0) Rd = Rs2_or_imm10;}});
0x2: movrle({{if(Rs1 <= 0) Rd = Rs2_or_imm10;}});
0x3: movrl({{if(Rs1 < 0) Rd = Rs2_or_imm10;}});
0x5: movrne({{if(Rs1 != 0) Rd = Rs2_or_imm10;}});
0x6: movrg({{if(Rs1 > 0) Rd = Rs2_or_imm10;}});
0x7: movrge({{if(Rs1 >= 0) Rd = Rs2_or_imm10;}});
}
0x30: decode RD {
0x0: wry({{Y = Rs1 ^ Rs2_or_imm13;}});
0x2: wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}});
0x3: wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}});
0x6: wrfprs({{Asi = Rs1 ^ Rs2_or_imm13;}});
0xF: Trap::sir({{fault = new SoftwareInitiatedReset;}});
}
0x31: decode FCN {
0x0: BasicOperate::saved({{/*Boogy Boogy*/}});
0x1: BasicOperate::restored({{/*Boogy Boogy*/}});
}
0x32: decode RD {
format Priv
{
0x0: wrprtpc({{
xc->setMiscReg(MISCREG_TPC_BASE + Tl,
Rs1 ^ Rs2_or_imm13);
}});
0x1: wrprtnpc({{
xc->setMiscReg(MISCREG_TNPC_BASE + Tl,
Rs1 ^ Rs2_or_imm13);
}});
0x2: wrprtstate({{
xc->setMiscReg(MISCREG_TSTATE_BASE + Tl,
Rs1 ^ Rs2_or_imm13);
}});
0x3: wrprtt({{
xc->setMiscReg(MISCREG_TT_BASE + Tl,
Rs1 ^ Rs2_or_imm13);
}});
0x4: wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}});
0x5: wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}});
0x6: wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}});
0x7: wrprtl({{Tl = Rs1 ^ Rs2_or_imm13;}});
0x8: wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}});
0x9: wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}});
0xA: wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}});
0xB: wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}});
0xC: wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}});
0xD: wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}});
0xE: wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}});
}
}
0x34: Trap::fpop1({{fault = new FpDisabled;}});
0x35: Trap::fpop2({{fault = new FpDisabled;}});
0x38: Branch::jmpl({{
Addr target = Rs1 + Rs2_or_imm13;
if(target && 0x3)
fault = new MemAddressNotAligned;
else
{
Rd = xc->readPC();
NNPC = target;
}
}});
0x39: Branch::return({{
Addr target = Rs1 + Rs2_or_imm13;
if(target && 0x3)
fault = new MemAddressNotAligned;
else
NNPC = target;
//This needs to change the register window
//like restore does
}});
0x3A: decode CC
{
0x0: Trap::tcci({{
#if FULL_SYSTEM
fault = new TrapInstruction;
#else
if(passesCondition(CcrIcc, machInst<25:28>))
// At least glibc only uses trap 0,
// solaris/sunos may use others
assert((I ? Rs1 + Rs2 : Rs1 + SW_TRAP) == 0);
xc->syscall();
#endif
}}); }});
0x2: Trap::tccx({{ 0x2: movccx({{
#if FULL_SYSTEM if(passesCondition(CcrXcc, COND4))
fault = new TrapInstruction; Rd = (I ? SIMM11 : RS2);
#else
if(passesCondition(CcrXcc, machInst<25:28>))
// At least glibc only uses trap 0,
// solaris/sunos may use others
assert((I ? Rs1 + Rs2 : Rs1 + SW_TRAP) == 0);
xc->syscall();
#endif
}}); }});
} }
0x3B: BasicOperate::flush({{/*Lala*/}});
0x3C: BasicOperate::save({{/*leprechauns*/}});
0x3D: BasicOperate::restore({{/*Eat my short int*/}});
0x3E: decode FCN {
0x1: BasicOperate::done({{/*Done thing*/}});
0x2: BasicOperate::retry({{/*Retry thing*/}});
}
} }
0x2D: sdivx({{
if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
else Rd.sdw = Rs1.sdw / Rs2_or_imm13;
}});
0x2E: decode RS1 {
0x0: IntOp::popc({{
int64_t count = 0;
uint64_t temp = Rs2_or_imm13;
//Count the 1s in the front 4bits until none are left
uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4};
while(temp)
{
count += oneBits[temp & 0xF];
temp = temp >> 4;
}
}});
}
0x2F: decode RCOND3
{
0x1: movreq({{if(Rs1 == 0) Rd = Rs2_or_imm10;}});
0x2: movrle({{if(Rs1 <= 0) Rd = Rs2_or_imm10;}});
0x3: movrl({{if(Rs1 < 0) Rd = Rs2_or_imm10;}});
0x5: movrne({{if(Rs1 != 0) Rd = Rs2_or_imm10;}});
0x6: movrg({{if(Rs1 > 0) Rd = Rs2_or_imm10;}});
0x7: movrge({{if(Rs1 >= 0) Rd = Rs2_or_imm10;}});
}
0x30: decode RD {
0x0: wry({{Y = Rs1 ^ Rs2_or_imm13;}});
0x2: wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}});
0x3: wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}});
0x6: wrfprs({{Asi = Rs1 ^ Rs2_or_imm13;}});
0xF: Trap::sir({{fault = new SoftwareInitiatedReset;}});
}
0x31: decode FCN {
0x0: BasicOperate::saved({{/*Boogy Boogy*/}});
0x1: BasicOperate::restored({{/*Boogy Boogy*/}});
}
0x32: decode RD {
format Priv
{
0x0: wrprtpc({{
xc->setMiscReg(MISCREG_TPC_BASE + Tl,
Rs1 ^ Rs2_or_imm13);
}});
0x1: wrprtnpc({{
xc->setMiscReg(MISCREG_TNPC_BASE + Tl,
Rs1 ^ Rs2_or_imm13);
}});
0x2: wrprtstate({{
xc->setMiscReg(MISCREG_TSTATE_BASE + Tl,
Rs1 ^ Rs2_or_imm13);
}});
0x3: wrprtt({{
xc->setMiscReg(MISCREG_TT_BASE + Tl,
Rs1 ^ Rs2_or_imm13);
}});
0x4: wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}});
0x5: wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}});
0x6: wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}});
0x7: wrprtl({{Tl = Rs1 ^ Rs2_or_imm13;}});
0x8: wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}});
0x9: wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}});
0xA: wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}});
0xB: wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}});
0xC: wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}});
0xD: wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}});
0xE: wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}});
}
}
0x34: Trap::fpop1({{fault = new FpDisabled;}});
0x35: Trap::fpop2({{fault = new FpDisabled;}});
0x38: Branch::jmpl({{
Addr target = Rs1 + Rs2_or_imm13;
if(target & 0x3)
fault = new MemAddressNotAligned;
else
{
Rd = xc->readPC();
NNPC = target;
}
}});
0x39: Branch::return({{
Addr target = Rs1 + Rs2_or_imm13;
if(target & 0x3)
fault = new MemAddressNotAligned;
else
NNPC = target;
//This needs to change the register window
//like restore does
}});
0x3A: decode CC
{
0x0: Trap::tcci({{
#if FULL_SYSTEM
fault = new TrapInstruction;
#else
if(passesCondition(CcrIcc, machInst<25:28>))
{
// At least glibc only uses trap 0,
// solaris/sunos may use others
assert((I ? Rs1 + Rs2 : Rs1 + SW_TRAP) == 0);
xc->syscall();
}
#endif
}});
0x2: Trap::tccx({{
#if FULL_SYSTEM
fault = new TrapInstruction;
#else
if(passesCondition(CcrXcc, machInst<25:28>))
{
// At least glibc only uses trap 0,
// solaris/sunos may use others
assert((I ? Rs1 + Rs2 : Rs1 + SW_TRAP) == 0);
xc->syscall();
}
#endif
}});
}
0x3B: Nop::flush({{/*Instruction memory flush*/}});
0x3C: save({{
//CWP should be set directly so that it always happens
//Also, this will allow writing to the new window and
//reading from the old one
if(Cansave == 0)
{
if(Otherwin)
fault = new SpillNOther(WstateOther);
else
fault = new SpillNNormal(WstateNormal);
Cwp = (Cwp + 2) % NWindows;
}
else if(Cleanwin - Canrestore == 0)
{
Cwp = (Cwp + 1) % NWindows;
fault = new CleanWindow;
}
else
{
Cwp = (Cwp + 1) % NWindows;
Rd = Rs1 + Rs2_or_imm13;
Cansave--;
Canrestore++;
}
//This is here to make sure the CWP is written
//no matter what. This ensures that the results
//are written in the new window as well.
xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
}});
0x3D: restore({{
//CWP should be set directly so that it always happens
//Also, this will allow writing to the new window and
//reading from the old one
Cwp = (Cwp - 1 + NWindows) % NWindows;
if(Canrestore == 0)
{
if(Otherwin)
fault = new FillNOther(WstateOther);
else
fault = new FillNNormal(WstateNormal);
}
else
{
Rd = Rs1 + Rs2_or_imm13;
Cansave++;
Canrestore--;
}
//This is here to make sure the CWP is written
//no matter what. This ensures that the results
//are written in the new window as well.
xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
}});
0x3E: decode FCN {
0x0: Priv::done({{
if(Tl == 0)
return new IllegalInstruction;
Cwp = xc->readMiscReg(MISCREG_TSTATE_CWP_BASE + Tl);
Asi = xc->readMiscReg(MISCREG_TSTATE_ASI_BASE + Tl);
Ccr = xc->readMiscReg(MISCREG_TSTATE_CCR_BASE + Tl);
Pstate = xc->readMiscReg(MISCREG_TSTATE_PSTATE_BASE + Tl);
NPC = xc->readMiscReg(MISCREG_TNPC_BASE + Tl);
NNPC = NPC + 4;
Tl = Tl - 1;
}});
0x1: BasicOperate::retry({{
if(Tl == 0)
return new IllegalInstruction;
Cwp = xc->readMiscReg(MISCREG_TSTATE_CWP_BASE + Tl);
Asi = xc->readMiscReg(MISCREG_TSTATE_ASI_BASE + Tl);
Ccr = xc->readMiscReg(MISCREG_TSTATE_CCR_BASE + Tl);
Pstate = xc->readMiscReg(MISCREG_TSTATE_PSTATE_BASE + Tl);
NPC = xc->readMiscReg(MISCREG_TPC_BASE + Tl);
NNPC = xc->readMiscReg(MISCREG_TNPC_BASE + Tl);
Tl = Tl - 1;
}});
}
}
} }
0x3: decode OP3 { 0x3: decode OP3 {
format Mem { format Load {
0x00: lduw({{Rd.uw = Mem.uw;}}); //LDUW 0x00: lduw({{Rd = Mem;}}, {{32}});
0x01: ldub({{Rd.ub = Mem.ub;}}); //LDUB 0x01: ldub({{Rd = Mem;}}, {{8}});
0x02: lduh({{Rd.uhw = Mem.uhw;}}); //LDUH 0x02: lduh({{Rd = Mem;}}, {{16}});
0x03: ldd({{ 0x03: ldd({{
uint64_t val = Mem.udw; uint64_t val = Mem;
RdLow = val<31:0>; RdLow = val<31:0>;
RdHigh = val<63:32>; RdHigh = val<63:32>;
}});//LDD }}, {{64}});
0x04: stw({{Mem.sw = Rd.sw;}}); //STW }
0x05: stb({{Mem.sb = Rd.sb;}}); //STB format Store {
0x06: sth({{Mem.shw = Rd.shw;}}); //STH 0x04: stw({{Mem = Rd.sw;}}, {{32}});
0x07: std({{ 0x05: stb({{Mem = Rd.sb;}}, {{8}});
Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32; 0x06: sth({{Mem = Rd.shw;}}, {{16}});
}});//STD 0x07: std({{Mem = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{64}});
0x08: ldsw({{Rd.sw = Mem.sw;}}); //LDSW }
0x09: ldsb({{Rd.sb = Mem.sb;}}); //LDSB format Load {
0x0A: ldsh({{Rd.shw = Mem.shw;}}); //LDSH 0x08: ldsw({{Rd = (int32_t)Mem;}}, {{32}});
0x0B: ldx({{Rd.udw = Mem.udw;}}); //LDX 0x09: ldsb({{Rd = (int8_t)Mem;}}, {{8}});
0x0A: ldsh({{Rd = (int16_t)Mem;}}, {{16}});
0x0D: ldstub({{ 0x0B: ldx({{Rd = (int64_t)Mem;}}, {{64}});
Rd.ub = Mem.ub; 0x0D: ldstub({{
Mem.ub = 0xFF; Rd = Mem;
}}); //LDSTUB Mem = 0xFF;
0x0E: stx({{Rd.udw = Mem.udw;}}); //STX }}, {{8}});
0x0F: swap({{ }
uint32_t temp = Rd.uw; 0x0E: Store::stx({{Mem = Rd}}, {{64}});
Rd.uw = Mem.uw; 0x0F: LoadStore::swap({{
Mem.uw = temp; uint32_t temp = Rd;
}}); //SWAP Rd = Mem;
0x10: lduwa({{Rd.uw = Mem.uw;}}); //LDUWA Mem = temp;
0x11: lduba({{Rd.ub = Mem.ub;}}); //LDUBA }}, {{32}});
0x12: lduha({{Rd.uhw = Mem.uhw;}}); //LDUHA format Load {
0x13: ldda({{ 0x10: lduwa({{Rd = Mem;}}, {{32}});
uint64_t val = Mem.udw; 0x11: lduba({{Rd = Mem;}}, {{8}});
RdLow = val<31:0>; 0x12: lduha({{Rd = Mem;}}, {{16}});
RdHigh = val<63:32>; 0x13: ldda({{
}}); //LDDA uint64_t val = Mem;
0x14: stwa({{Mem.uw = Rd.uw;}}); //STWA RdLow = val<31:0>;
0x15: stba({{Mem.ub = Rd.ub;}}); //STBA RdHigh = val<63:32>;
0x16: stha({{Mem.uhw = Rd.uhw;}}); //STHA }}, {{64}});
0x17: stda({{ }
Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32; format Store {
}}); //STDA 0x14: stwa({{Mem = Rd;}}, {{32}});
0x18: ldswa({{Rd.sw = Mem.sw;}}); //LDSWA 0x15: stba({{Mem = Rd;}}, {{8}});
0x19: ldsba({{Rd.sb = Mem.sb;}}); //LDSBA 0x16: stha({{Mem = Rd;}}, {{16}});
0x1A: ldsha({{Rd.shw = Mem.shw;}}); //LDSHA 0x17: stda({{Mem = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{64}});
0x1B: ldxa({{Rd.sdw = Mem.sdw;}}); //LDXA }
format Load {
0x1D: ldstuba({{ 0x18: ldswa({{Rd = (int32_t)Mem;}}, {{32}});
Rd.ub = Mem.ub; 0x19: ldsba({{Rd = (int8_t)Mem;}}, {{8}});
Mem.ub = 0xFF; 0x1A: ldsha({{Rd = (int16_t)Mem;}}, {{16}});
}}); //LDSTUBA 0x1B: ldxa({{Rd = (int64_t)Mem;}}, {{64}});
0x1E: stxa({{Mem.sdw = Rd.sdw}}); //STXA }
0x1F: swapa({{ 0x1D: LoadStore::ldstuba({{
uint32_t temp = Rd.uw; Rd = Mem;
Rd.uw = Mem.uw; Mem = 0xFF;
Mem.uw = temp; }}, {{8}});
}}); //SWAPA 0x1E: Store::stxa({{Mem = Rd}}, {{64}});
0x20: Trap::ldf({{fault = new FpDisabled;}}); 0x1F: LoadStore::swapa({{
0x21: decode X { uint32_t temp = Rd;
0x0: Trap::ldfsr({{fault = new FpDisabled;}}); Rd = Mem;
0x1: Trap::ldxfsr({{fault = new FpDisabled;}}); Mem = temp;
} }}, {{32}});
0x22: Trap::ldqf({{fault = new FpDisabled;}}); format Trap {
0x23: Trap::lddf({{fault = new FpDisabled;}}); 0x20: ldf({{fault = new FpDisabled;}});
0x24: Trap::stf({{fault = new FpDisabled;}}); 0x21: decode X {
0x25: decode X { 0x0: ldfsr({{fault = new FpDisabled;}});
0x0: Trap::stfsr({{fault = new FpDisabled;}}); 0x1: ldxfsr({{fault = new FpDisabled;}});
0x1: Trap::stxfsr({{fault = new FpDisabled;}});
}
0x26: Trap::stqf({{fault = new FpDisabled;}});
0x27: Trap::stdf({{fault = new FpDisabled;}});
0x2D: Nop::prefetch({{ }}); //PREFETCH
0x30: Trap::ldfa({{return new FpDisabled;}});
0x32: Trap::ldqfa({{fault = new FpDisabled;}});
0x33: Trap::lddfa({{fault = new FpDisabled;}});
0x34: Trap::stfa({{fault = new FpDisabled;}});
0x35: Trap::stqfa({{fault = new FpDisabled;}});
0x36: Trap::stdfa({{fault = new FpDisabled;}});
0x3C: Cas::casa(
{{uint64_t val = Mem.uw;
if(Rs2.uw == val)
Mem.uw = Rd.uw;
Rd.uw = val;
}}); //CASA
0x3D: Nop::prefetcha({{ }}); //PREFETCHA
0x3E: Cas::casxa({{
uint64_t val = Mem.udw;
if(Rs2 == val)
Mem.udw = Rd;
Rd = val;
}}); //CASXA
} }
0x22: ldqf({{fault = new FpDisabled;}});
0x23: lddf({{fault = new FpDisabled;}});
0x24: stf({{fault = new FpDisabled;}});
0x25: decode X {
0x0: stfsr({{fault = new FpDisabled;}});
0x1: stxfsr({{fault = new FpDisabled;}});
}
0x26: stqf({{fault = new FpDisabled;}});
0x27: stdf({{fault = new FpDisabled;}});
0x2D: Nop::prefetch({{ }});
0x30: ldfa({{return new FpDisabled;}});
0x32: ldqfa({{fault = new FpDisabled;}});
0x33: lddfa({{fault = new FpDisabled;}});
0x34: stfa({{fault = new FpDisabled;}});
0x35: stqfa({{fault = new FpDisabled;}});
0x36: stdfa({{fault = new FpDisabled;}});
0x3C: Cas::casa({{
uint64_t val = Mem.uw;
if(Rs2.uw == val)
Mem.uw = Rd.uw;
Rd.uw = val;
}});
0x3D: Nop::prefetcha({{ }});
0x3E: Cas::casxa({{
uint64_t val = Mem.udw;
if(Rs2 == val)
Mem.udw = Rd;
Rd = val;
}});
}
} }
} }

20
arch/sparc/isa/formats/integerop.isa
View file

@ -37,7 +37,7 @@ output header {{
{ {
} }
uint32_t imm; int32_t imm;
std::string generateDisassembly(Addr pc, std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const; const SymbolTable *symtab) const;
@ -57,7 +57,7 @@ output header {{
OpClass __opClass) : OpClass __opClass) :
IntOpImm(mnem, _machInst, __opClass) IntOpImm(mnem, _machInst, __opClass)
{ {
imm = SIMM10; imm = sign_ext(SIMM10, 10);
} }
}; };
@ -72,7 +72,7 @@ output header {{
OpClass __opClass) : OpClass __opClass) :
IntOpImm(mnem, _machInst, __opClass) IntOpImm(mnem, _machInst, __opClass)
{ {
imm = SIMM13; imm = sign_ext(SIMM13, 13);
} }
}; };
@ -195,7 +195,7 @@ output decoder {{
if(!printPseudoOps(response, pc, symtab)) if(!printPseudoOps(response, pc, symtab))
{ {
printMnemonic(response, mnemonic); printMnemonic(response, mnemonic);
if (_numSrcRegs > 1) if (_numSrcRegs > 0)
{ {
printReg(response, _srcRegIdx[0]); printReg(response, _srcRegIdx[0]);
for(int x = 1; x < _numSrcRegs - 1; x++) for(int x = 1; x < _numSrcRegs - 1; x++)
@ -254,14 +254,14 @@ let {{
def doIntFormat(code, ccCode, name, Name, opt_flags): def doIntFormat(code, ccCode, name, Name, opt_flags):
(usesImm, code, immCode, (usesImm, code, immCode,
rString, iString) = splitOutImm(code) rString, iString) = splitOutImm(code)
iop = genCompositeIop(code, name, Name, iop = InstObjParams(name, Name, 'IntOp', code,
'IntOp', opt_flags, cc_code=ccCode) opt_flags, ("cc_code", ccCode))
header_output = BasicDeclare.subst(iop) header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop) decoder_output = BasicConstructor.subst(iop)
exec_output = IntOpExecute.subst(iop) exec_output = IntOpExecute.subst(iop)
if usesImm: if usesImm:
imm_iop = genCompositeIop(code, name, Name + 'Imm', imm_iop = InstObjParams(name, Name + 'Imm', 'IntOpImm' + iString,
'IntOpImm' + iString, opt_flags, cc_code=ccCode) immCode, opt_flags, ("cc_code", ccCode))
header_output += BasicDeclare.subst(imm_iop) header_output += BasicDeclare.subst(imm_iop)
decoder_output += BasicConstructor.subst(imm_iop) decoder_output += BasicConstructor.subst(imm_iop)
exec_output += IntOpExecute.subst(imm_iop) exec_output += IntOpExecute.subst(imm_iop)
@ -316,8 +316,8 @@ def format IntOpCcRes(code, *opt_flags) {{
}}; }};
def format SetHi(code, *opt_flags) {{ def format SetHi(code, *opt_flags) {{
iop = genCompositeIop(code, name, Name, 'SetHi', iop = InstObjParams(name, Name, 'SetHi',
opt_flags, cc_code='') code, opt_flags, ("cc_code", ''))
header_output = BasicDeclare.subst(iop) header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop) decoder_output = BasicConstructor.subst(iop)
exec_output = IntOpExecute.subst(iop) exec_output = IntOpExecute.subst(iop)

53
arch/sparc/isa/formats/mem.isa
View file

@ -37,7 +37,7 @@ output header {{
std::string generateDisassembly(Addr pc, std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const; const SymbolTable *symtab) const;
int imm; int32_t imm;
}; };
}}; }};
@ -46,7 +46,7 @@ output decoder {{
const SymbolTable *symtab) const const SymbolTable *symtab) const
{ {
std::stringstream response; std::stringstream response;
bool load = (_numDestRegs == 1); bool load = flags[IsLoad];
printMnemonic(response, mnemonic); printMnemonic(response, mnemonic);
if(!load) if(!load)
@ -72,7 +72,7 @@ output decoder {{
const SymbolTable *symtab) const const SymbolTable *symtab) const
{ {
std::stringstream response; std::stringstream response;
bool load = (_numDestRegs == 1); bool load = flags[IsLoad];
printMnemonic(response, mnemonic); printMnemonic(response, mnemonic);
if(!load) if(!load)
@ -102,7 +102,9 @@ def template MemExecute {{
%(op_decl)s; %(op_decl)s;
%(op_rd)s; %(op_rd)s;
%(ea_code)s; %(ea_code)s;
%(load)s;
%(code)s; %(code)s;
%(store)s;
if(fault == NoFault) if(fault == NoFault)
{ {
@ -114,16 +116,49 @@ def template MemExecute {{
} }
}}; }};
// Primary format for memory instructions: let {{
def format Mem(code, *opt_flags) {{ # Leave memAccessFlags at 0 for now
loadString = "xc->read(EA, (uint%(width)s_t&)Mem, 0);"
storeString = "uint64_t write_result = 0; \
xc->write((uint%(width)s_t)Mem, EA, 0, &write_result);"
def doMemFormat(code, load, store, name, Name, opt_flags):
addrCalcReg = 'EA = Rs1 + Rs2;' addrCalcReg = 'EA = Rs1 + Rs2;'
addrCalcImm = 'EA = Rs1 + SIMM13;' addrCalcImm = 'EA = Rs1 + SIMM13;'
iop = genCompositeIop(code, name, Name, 'Mem', iop = InstObjParams(name, Name, 'Mem', code,
opt_flags, ea_code=addrCalcReg) opt_flags, ("ea_code", addrCalcReg),
iop_imm = genCompositeIop(code, name, Name + 'Imm', 'MemImm', ("load", load), ("store", store))
opt_flags, ea_code=addrCalcImm) iop_imm = InstObjParams(name, Name + 'Imm', 'MemImm', code,
opt_flags, ("ea_code", addrCalcImm),
("load", load), ("store", store))
header_output = BasicDeclare.subst(iop) + BasicDeclare.subst(iop_imm) header_output = BasicDeclare.subst(iop) + BasicDeclare.subst(iop_imm)
decoder_output = BasicConstructor.subst(iop) + BasicConstructor.subst(iop_imm) decoder_output = BasicConstructor.subst(iop) + BasicConstructor.subst(iop_imm)
decode_block = ROrImmDecode.subst(iop) decode_block = ROrImmDecode.subst(iop)
exec_output = MemExecute.subst(iop) + MemExecute.subst(iop_imm) exec_output = MemExecute.subst(iop) + MemExecute.subst(iop_imm)
return (header_output, decoder_output, exec_output, decode_block)
}};
def format Load(code, width, *opt_flags) {{
(header_output,
decoder_output,
exec_output,
decode_block) = doMemFormat(code,
loadString % {"width":width}, '', name, Name, opt_flags)
}};
def format Store(code, width, *opt_flags) {{
(header_output,
decoder_output,
exec_output,
decode_block) = doMemFormat(code, '',
storeString % {"width":width}, name, Name, opt_flags)
}};
def format LoadStore(code, width, *opt_flags) {{
(header_output,
decoder_output,
exec_output,
decode_block) = doMemFormat(code,
loadString % {"width":width}, storeString % {"width":width},
name, Name, opt_flags)
}}; }};

88
arch/sparc/isa/formats/priv.isa
View file

@ -50,7 +50,7 @@ output header {{
{ {
} }
uint32_t imm; int32_t imm;
}; };
/** /**
@ -66,7 +66,7 @@ output header {{
{ {
} }
uint32_t imm; int32_t imm;
}; };
}}; }};
@ -91,35 +91,8 @@ def template PrivExecute {{
%(op_decl)s; %(op_decl)s;
%(op_rd)s; %(op_rd)s;
//Since these are processed inside templates and not in codeblocks,
//They aren't translated by the isa_parser. Their names begin with
//underscores so they don't cause conflicts.
uint32_t _PstatePriv = xc->readMiscReg(MISCREG_PSTATE_PRIV);
//If the processor isn't in privileged mode, fault out right away //If the processor isn't in privileged mode, fault out right away
if(!_PstatePriv) if(%(check)s)
return new PrivilegedOpcode;
%(code)s;
%(op_wb)s;
return NoFault;
}
}};
def template PrivTickExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
%(op_decl)s;
%(op_rd)s;
//Since these are processed inside templates and not in codeblocks,
//They aren't translated by the isa_parser. Their names begin with
//underscores so they don't cause conflicts.
uint32_t _PstatePriv = xc->readMiscReg(MISCREG_PSTATE_PRIV);
uint32_t _TickNpt = xc->readMiscReg(MISCREG_TICK_NPT);
//If the processor isn't in privileged mode, fault out right away
if(!_PstatePriv && _TickNpt)
return new PrivilegedAction; return new PrivilegedAction;
%(code)s; %(code)s;
@ -128,50 +101,39 @@ def template PrivTickExecute {{
} }
}}; }};
// Primary format for integer operate instructions: let {{
def format Priv(code, *opt_flags) {{ def doPrivFormat(code, checkCode, name, Name, opt_flags):
uses_imm = (code.find('Rs2_or_imm13') != -1) (usesImm, code, immCode,
if uses_imm: rString, iString) = splitOutImm(code)
orig_code = code iop = InstObjParams(name, Name, 'Priv', code,
code = re.sub(r'Rs2_or_imm13', 'Rs2', orig_code) opt_flags, ("check", checkCode))
imm_code = re.sub(r'Rs2_or_imm13(\.\w+)?', 'imm', orig_code)
cblk = CodeBlock(code)
iop = InstObjParams(name, Name, 'Priv', cblk, opt_flags)
header_output = BasicDeclare.subst(iop) header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop) decoder_output = BasicConstructor.subst(iop)
exec_output = PrivExecute.subst(iop) exec_output = PrivExecute.subst(iop)
if uses_imm: if usesImm:
imm_cblk = CodeBlock(imm_code) imm_iop = InstObjParams(name, Name + 'Imm', 'PrivImm',
imm_iop = InstObjParams(name, Name + 'Imm', 'PrivImm', imm_cblk, immCode, opt_flags, ("check", checkCode))
opt_flags)
header_output += BasicDeclare.subst(imm_iop) header_output += BasicDeclare.subst(imm_iop)
decoder_output += BasicConstructor.subst(imm_iop) decoder_output += BasicConstructor.subst(imm_iop)
exec_output += PrivExecute.subst(imm_iop) exec_output += PrivExecute.subst(imm_iop)
decode_block = ROrImmDecode.subst(iop) decode_block = ROrImmDecode.subst(iop)
else: else:
decode_block = BasicDecode.subst(iop) decode_block = BasicDecode.subst(iop)
return (header_output, decoder_output, exec_output, decode_block)
}};
// Primary format for integer operate instructions:
def format Priv(code, *opt_flags) {{
checkCode = "(!PstatePriv)"
(header_output, decoder_output,
exec_output, decode_block) = doPrivFormat(code,
checkCode, name, Name, opt_flags)
}}; }};
// Primary format for integer operate instructions: // Primary format for integer operate instructions:
def format PrivTick(code, *opt_flags) {{ def format PrivTick(code, *opt_flags) {{
uses_imm = (code.find('Rs2_or_imm13') != -1) checkCode = "(!PstatePriv && TickNpt)"
if uses_imm: (header_output, decoder_output,
orig_code = code exec_output, decode_block) = doPrivFormat(code,
code = re.sub(r'Rs2_or_imm13', 'Rs2', orig_code) checkCode, name, Name, opt_flags)
imm_code = re.sub(r'Rs2_or_imm13(\.\w+)?', 'imm', orig_code)
cblk = CodeBlock(code)
iop = InstObjParams(name, Name, 'PrivTick', cblk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
exec_output = PrivTickExecute.subst(iop)
if uses_imm:
imm_cblk = CodeBlock(imm_code)
imm_iop = InstObjParams(name, Name + 'Imm', 'PrivTickImm', imm_cblk,
opt_flags)
header_output += BasicDeclare.subst(imm_iop)
decoder_output += BasicConstructor.subst(imm_iop)
exec_output += PrivTickExecute.subst(imm_iop)
decode_block = Rb2OrImmDecode.subst(iop)
else:
decode_block = BasicDecode.subst(iop)
}}; }};

1
base/traceflags.py
View file

@ -143,6 +143,7 @@ baseFlags = [
'HWPrefetch', 'HWPrefetch',
'Stack', 'Stack',
'SimpleCPU', 'SimpleCPU',
'Sparc',
] ]
# #

BIN
configs/test/hello_sparc
View file

Binary file not shown.

4
cpu/cpu_exec_context.cc
View file

@ -62,7 +62,7 @@ CPUExecContext::CPUExecContext(BaseCPU *_cpu, int _thread_num, System *_sys,
{ {
proxy = new ProxyExecContext<CPUExecContext>(this); proxy = new ProxyExecContext<CPUExecContext>(this);
memset(&regs, 0, sizeof(RegFile)); regs.clear();
if (cpu->params->profile) { if (cpu->params->profile) {
profile = new FunctionProfile(system->kernelSymtab); profile = new FunctionProfile(system->kernelSymtab);
@ -93,7 +93,7 @@ CPUExecContext::CPUExecContext(BaseCPU *_cpu, int _thread_num,
mem_port->setPeer(port); mem_port->setPeer(port);
port->setPeer(mem_port); port->setPeer(mem_port);
memset(&regs, 0, sizeof(RegFile)); regs.clear();
proxy = new ProxyExecContext<CPUExecContext>(this); proxy = new ProxyExecContext<CPUExecContext>(this);
} }