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1st full draft switch statement actions for all integer arithmetic operations and the majority of the load & store operations (not all of FP-Ops),

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Output,Format, & Template code needs to be adjusted to correctly take these "decoder.h" inputs ...

--HG--
extra : convert_revision : 3dcde1f2f587e2766fd61231a93d34d1d7727356
This commit is contained in:
Korey Sewell 2006-02-04 18:59:44 -05:00
parent 035b443093
commit 6d2807ded8
1 changed files with 104 additions and 63 deletions
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167
arch/mips/isa/decoder.def
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@ -18,8 +18,8 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x0: decode FUNCTION_LO { 0x0: decode FUNCTION_LO {
0x1: decode MOVCI { 0x1: decode MOVCI {
format Move { format Move {
0: movf({{ if( FPConditionCode(CC) == 0) Rd = Rs}}); 0: movf({{ if( xc->miscRegs.fpcr == 0) Rd = Rs}});
1: movt({{ if( FPConditionCode(CC) == 1) Rd = Rs}}); 1: movt({{ if( xc->miscRegs.fpcr == 1) Rd = Rs}});
} }
} }
@ -67,27 +67,45 @@ decode OPCODE_HI default FailUnimpl::unknown() {
} }
format Trap { format Trap {
0x4: Syscall::syscall({{ xc->syscall()}},IsNonSpeculative); 0x4: syscall({{ xc->syscall()}},IsNonSpeculative);
0x5: Break::break({{ }}); 0x5: break({{ }});
0x7: Synchronize::sync({{ }}); 0x7: sync({{ }});
} }
} }
0x2: decode FUNCTION_LO { 0x2: decode FUNCTION_LO {
format IntOp { format BasicOp {
0x0: mfhi({{ }}); 0x0: mfhi({{ Rd = xc->miscRegs.Hi; }});
0x1: mthi({{ }}); 0x1: mthi({{ xc->miscRegs.Hi = Rs; }});
0x2: mflo({{ }}); 0x2: mflo({{ Rd = xc->miscRegs.Lo; }});
0x3: mtlo({{ }}); 0x3: mtlo({{ xc->miscRegs.Lo = Rs; }});
} }
}; };
0x3: decode FUNCTION_LO { 0x3: decode FUNCTION_LO {
format IntOp { format IntOp {
0x0: mult({{ Rd.sw = Rs.sw * Rt.sw; }}); 0x0: mult({{
0x1: multu({{ Rd.sw = Rs.uw * Rt.uw;}}); INT64 temp1 = Rs.sw * Rt.sw;
0x2: div({{ Rd.sw = Rs.sw / Rt.sw;}}); xc->miscRegs.Hi->temp1<63:32>;
0x3: divu({{ Rd.sw = Rs.sw / Rt.uw;}}); xc->miscRegs.Lo->temp1<31:0>
}});
0x1: multu({{
INT64 temp1 = Rs.uw * Rt.uw;
xc->miscRegs.Hi->temp1<63:32>;
xc->miscRegs.Lo->temp1<31:0>
Rd.sw = Rs.uw * Rt.uw;
}});
0x2: div({{
xc->miscRegs.Hi = Rs.sw % Rt.sw;
xc->miscRegs.Lo = Rs.sw / Rt.sw;
}});
0x3: divu({{
xc->miscRegs.Hi = Rs.uw % Rt.uw;
xc->miscRegs.Lo = Rs.uw / Rt.uw;
}});
} }
}; };
@ -126,12 +144,12 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x1: decode REGIMM_HI { 0x1: decode REGIMM_HI {
0x0: decode REGIMM_LO { 0x0: decode REGIMM_LO {
format Branch { format Branch {
0x0: bltz({{ }}); 0x0: bltz({{ cond = (Rs.sq < 0); }});
0x1: bgez({{ }}); 0x1: bgez({{ cond = (Rs.sq >= 0); }});
//MIPS obsolete instructions //MIPS obsolete instructions
0x2: bltzl({{ }}); 0x2: bltzl({{ cond = (Rs.sq < 0); }});
0x3: bgezl({{ }}); 0x3: bgezl({{ cond = (Rs.sq >= 0); }});
} }
} }
@ -148,12 +166,12 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x2: decode REGIMM_LO { 0x2: decode REGIMM_LO {
format Branch { format Branch {
0x0: bltzal({{ }}); 0x0: bltzal({{ cond = (Rs.sq < 0); }});
0x1: bgezal({{ }}); 0x1: bgezal({{ cond = (Rs.sq >= 0); }});
//MIPS obsolete instructions //MIPS obsolete instructions
0x2: bltzall({{ }}); 0x2: bltzall({{ cond = (Rs.sq < 0); }});
0x3: bgezall({{ }}); 0x3: bgezall({{ cond = (Rs.sq >= 0); }});
} }
} }
@ -170,10 +188,10 @@ decode OPCODE_HI default FailUnimpl::unknown() {
} }
format Branch { format Branch {
0x4: beq({{ }}); 0x4: beq({{ cond = (Rs.sq == 0); }});
0x5: bne({{ }}); 0x5: bne({{ cond = (Rs.sq != 0); }});
0x6: blez({{ }}); 0x6: blez({{ cond = (Rs.sq <= 0); }});
0x7: bgtz({{ }}); 0x7: bgtz({{ cond = (Rs.sq > 0); }});
} }
}; };
@ -186,10 +204,7 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x4: andi({{ Rt.sw = Rs.sw & INTIMM;}}); 0x4: andi({{ Rt.sw = Rs.sw & INTIMM;}});
0x5: ori({{ Rt.sw = Rs.sw | INTIMM;}}); 0x5: ori({{ Rt.sw = Rs.sw | INTIMM;}});
0x6: xori({{ Rt.sw = Rs.sw ^ INTIMM;}}); 0x6: xori({{ Rt.sw = Rs.sw ^ INTIMM;}});
}; 0x7: lui({{ Rt = INTIMM << 16}});
format Memory {
0x7: lui({{ }});
}; };
}; };
@ -245,15 +260,15 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x1: decode ND { 0x1: decode ND {
0x0: decode TF { 0x0: decode TF {
format Branch { format Branch {
0x0: bc1f({{ }}); 0x0: bc1f({{ cond = (xc->miscRegs.fpcr == 0); }});
0x1: bc1t({{ }}); 0x1: bc1t({{ cond = (xc->miscRegs.fpcr == 1); }});
} }
} }
0x1: decode TF { 0x1: decode TF {
format Branch { format Branch {
0x0: bc1fl({{ }}); 0x0: bc1fl({{ cond = (xc->miscRegs.fpcr == 0); }});
0x1: bc1tl({{ }}); 0x1: bc1tl({{ cond = (xc->miscRegs.fpcr == 1); }});
} }
} }
} }
@ -440,15 +455,15 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x1: decode ND { 0x1: decode ND {
0x0: decode TF { 0x0: decode TF {
format Branch { format Branch {
0x0: bc2f({{ }}); 0x0: bc2f({{ cond = (xc->miscRegs.cop2cc == 0); }}, COP2);
0x1: bc2t({{ }}); 0x1: bc2t({{ cond = (xc->miscRegs.cop2cc == 1); }}, COP2}});
} }
} }
0x1: decode TF { 0x1: decode TF {
format Branch { format Branch {
0x0: bc2fl({{ }}); 0x0: bc2fl({{ cond = (xc->miscRegs.cop2cc == 0); }}, COP2}});
0x1: bc2tl({{ }}); 0x1: bc2tl({{ cond = (xc->miscRegs.cop2cc == 1); }}, COP2}});
} }
} }
} }
@ -500,10 +515,10 @@ decode OPCODE_HI default FailUnimpl::unknown() {
} }
//MIPS obsolete instructions //MIPS obsolete instructions
0x4: beql({{ }}); 0x4: beql({{ cond = (Rs.sq == 0); }});
0x5: bnel({{ }}); 0x5: bnel({{ cond = (Rs.sq != 0); }});
0x6: blezl({{ }}); 0x6: blezl({{ cond = (Rs.sq <= 0); }});
0x7: bgtzl({{ }}); 0x7: bgtzl({{ cond = (Rs.sq > 0); }});
}; };
0x3: decode OPCODE_LO default FailUnimpl::reserved() { 0x3: decode OPCODE_LO default FailUnimpl::reserved() {
@ -512,11 +527,37 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x4: decode FUNCTION_HI { 0x4: decode FUNCTION_HI {
0x0: decode FUNCTION_LO { 0x0: decode FUNCTION_LO {
0x0: madd({{ }}); format IntOp {
0x1: maddu({{ }}); 0x0: madd({{
0x2: mult({{ }}); INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32;
0x4: msub({{ }}); temp1 = temp1 + (Rs.sw * Rt.sw);
0x5: msubu({{ }}); xc->miscRegs.Hi->temp1<63:32>;
xc->miscRegs.Lo->temp1<31:0>
}});
0x1: maddu({{
INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32;
temp1 = temp1 + (Rs.uw * Rt.uw);
xc->miscRegs.Hi->temp1<63:32>;
xc->miscRegs.Lo->temp1<31:0>
}});
0x2: mul({{ Rd.sw = Rs.sw * Rt.sw; }});
0x4: msub({{
INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32;
temp1 = temp1 - (Rs.sw * Rt.sw);
xc->miscRegs.Hi->temp1<63:32>;
xc->miscRegs.Lo->temp1<31:0>
}});
0x5: msubu({{
INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32;
temp1 = temp1 - (Rs.uw * Rt.uw);
xc->miscRegs.Hi->temp1<63:32>;
xc->miscRegs.Lo->temp1<31:0>
}});
}
} }
0x4: decode FUNCTION_LO { 0x4: decode FUNCTION_LO {
@ -552,13 +593,13 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x4: decode OPCODE_LO default FailUnimpl::reserved() { 0x4: decode OPCODE_LO default FailUnimpl::reserved() {
format Memory { format Memory {
0x0: lb({{ }}); 0x0: lb({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sb; }});
0x1: lh({{ }}); 0x1: lh({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sh; }});
0x2: lwl({{ }}); 0x2: lwl({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sw; }}, WordAlign);
0x3: lw({{ }}); 0x3: lw({{ EA = Rs + disp; }}, {{ Rb.uq = Mem.sb; }});
0x4: lbu({{ }}); 0x4: lbu({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.ub; }});
0x5: lhu({{ }}); 0x5: lhu({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uh; }});
0x6: lhu({{ }}); 0x6: lwr({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uw; }}, WordAlign);
}; };
0x7: FailUnimpl::reserved({{ }}); 0x7: FailUnimpl::reserved({{ }});
@ -566,11 +607,11 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x5: decode OPCODE_LO default FailUnimpl::reserved() { 0x5: decode OPCODE_LO default FailUnimpl::reserved() {
format Memory { format Memory {
0x0: sb({{ }}); 0x0: sb({{ EA = Rs + disp; }}, {{ Mem.ub = Rt<7:0>; }});
0x1: sh({{ }}); 0x1: sh({{ EA = Rs + disp; }},{{ Mem.uh = Rt<15:0>; }});
0x2: swl({{ }}); 0x2: swl({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }},WordAlign);
0x3: sw({{ }}); 0x3: sw({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }});
0x6: swr({{ }}); 0x6: swr({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }},WordAlign);
}; };
format FailUnimpl { format FailUnimpl {
@ -584,16 +625,16 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x6: decode OPCODE_LO default FailUnimpl::reserved() { 0x6: decode OPCODE_LO default FailUnimpl::reserved() {
format Memory { format Memory {
0x0: ll({{ }}); 0x0: ll({{ }});
0x1: lwc1({{ }}); 0x1: lwc1({{ EA = Rs + disp; }},{{ Ft<31:0> = Mem.uf; }});
0x5: ldc1({{ }}); 0x5: ldc1({{ EA = Rs + disp; }},{{ Ft<63:0> = Mem.df; }});
}; };
}; };
0x7: decode OPCODE_LO default FailUnimpl::reserved() { 0x7: decode OPCODE_LO default FailUnimpl::reserved() {
format Memory { format Memory {
0x0: sc({{ }}); 0x0: sc({{ }});
0x1: swc1({{ }}); 0x1: swc1({{ EA = Rs + disp; }},{{ Mem.uf = Ft<31:0>; }});
0x5: sdc1({{ }}); 0x5: sdc1({{ EA = Rs + disp; }},{{ Mem.df = Ft<63:0>; }});
}; };
} }