dev, arm: Add support for automatic PCI interrupt routing

Add support for automatic PCI interrupt routing using a device's ID on
the PCI bus. Our current DTBs typically tell the kernel that we do
this or something similar when declaring the PCI controller. This
changeset adds an option to make the simulator behave in the same way.

Interrupt routing can be selected by setting the int_policy parameter
in the GenericArmPciHost. The following values are supported:

  * ARM_PCI_INT_STATIC: Use the old static routing policy using the
    interrupt line from a device's configurtion space.

  * ARM_PCI_INT_DEV: Use device number on the PCI bus to map to an
    interrupt in the GIC. The interrupt is computed as:

    gic_int = int_base + (pci_dev % int_count)

  * ARM_PCI_INT_PIN: Use device interrupt pin on the PCI bus to map to
    an interrupt in the GIC. The PCI specification reserves pin ID 0
    for devices without interrupts, the interrupt therefore computed
    as:

    gic_int = int_base + ((pin - 1) % int_count)

src/dev/arm/RealView.py

@@ -86,6 +86,20 @@ class A9SCU(BasicPioDevice):
     type = 'A9SCU'
     cxx_header = "dev/arm/a9scu.hh"
 
+class ArmPciIntRouting(Enum): vals = [
+    'ARM_PCI_INT_STATIC',
+    'ARM_PCI_INT_DEV',
+    'ARM_PCI_INT_PIN',
+    ]
+
+class GenericArmPciHost(GenericPciHost):
+    type = 'GenericArmPciHost'
+    cxx_header = "dev/arm/pci_host.hh"
+
+    int_policy = Param.ArmPciIntRouting("PCI interrupt routing policy")
+    int_base = Param.Unsigned("PCI interrupt base")
+    int_count = Param.Unsigned("Maximum number of interrupts used by this host")
+
 class RealViewCtrl(BasicPioDevice):
     type = 'RealViewCtrl'
     cxx_header = "dev/arm/rv_ctrl.hh"

src/dev/arm/SConscript

@@ -62,6 +62,7 @@ if env['TARGET_ISA'] == 'arm':
     Source('kmi.cc')
     Source('timer_sp804.cc')
     Source('gpu_nomali.cc')
+    Source('pci_host.cc')
     Source('rv_ctrl.cc')
     Source('realview.cc')
     Source('rtc_pl031.cc')

src/dev/arm/pci_host.cc

@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2015 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Andreas Sandberg
+ */
+
+#include "dev/arm/pci_host.hh"
+
+#include "params/GenericArmPciHost.hh"
+
+GenericArmPciHost::GenericArmPciHost(const GenericArmPciHostParams *p)
+    : GenericPciHost(p),
+      intPolicy(p->int_policy), intBase(p->int_base),
+      intCount(p->int_count)
+{
+}
+
+
+uint32_t
+GenericArmPciHost::mapPciInterrupt(const PciBusAddr &addr, PciIntPin pin) const
+{
+    fatal_if(pin == PciIntPin::NO_INT,
+             "%02x:%02x.%i: Interrupt from a device without interrupts\n",
+             addr.bus, addr.dev, addr.func);
+
+    switch (intPolicy) {
+      case Enums::ARM_PCI_INT_STATIC:
+        return GenericPciHost::mapPciInterrupt(addr, pin);
+
+      case Enums::ARM_PCI_INT_DEV:
+        return intBase + (addr.dev % intCount);
+
+      case Enums::ARM_PCI_INT_PIN:
+        return intBase + ((static_cast<uint8_t>(pin) - 1) % intCount);
+
+      default:
+        fatal("Unsupported PCI interrupt routing policy.");
+    }
+}
+
+
+GenericArmPciHost *
+GenericArmPciHostParams::create()
+{
+    return new GenericArmPciHost(this);
+}

src/dev/arm/pci_host.hh

@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2015 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Andreas Sandberg
+ */
+
+#ifndef __DEV_ARM_PCI_HOST_HH__
+#define __DEV_ARM_PCI_HOST_HH__
+
+#include "dev/pci/host.hh"
+#include "enums/ArmPciIntRouting.hh"
+
+class BaseGic;
+struct GenericArmPciHostParams;
+
+class GenericArmPciHost
+    : public GenericPciHost
+{
+  public:
+    GenericArmPciHost(const GenericArmPciHostParams *p);
+    virtual ~GenericArmPciHost() {}
+
+  protected:
+    uint32_t mapPciInterrupt(const PciBusAddr &addr,
+                             PciIntPin pin) const override;
+
+  protected:
+    const Enums::ArmPciIntRouting intPolicy;
+    const uint32_t intBase;
+    const uint32_t intCount;
+};
+
+#endif // __DEV_ARM_PCI_HOST_HH__