MEM: Fix residual bus ports and make them master/slave

This patch cleans up a number of remaining uses of bus.port which
is now split into bus.master and bus.slave. The only non-trivial change
is the memtest where the level building now has to be aware of the role
of the ports used in the previous level.

configs/example/memtest.py

@@ -147,11 +147,16 @@ def make_level(spec, prototypes, attach_obj, attach_port):
      fanout = spec[0]
      parent = attach_obj # use attach obj as config parent too
      if len(spec) > 1 and (fanout > 1 or options.force_bus):
+          port = getattr(attach_obj, attach_port)
           new_bus = Bus(clock="500MHz", width=16)
-          new_bus.port = getattr(attach_obj, attach_port)
+          if (port.role == 'MASTER'):
+               new_bus.slave = port
+               attach_port = "master"
+          else:
+               new_bus.master = port
+               attach_port = "slave"
           parent.cpu_side_bus = new_bus
           attach_obj = new_bus
-          attach_port = "port"
      objs = [prototypes[0]() for i in xrange(fanout)]
      if len(spec) > 1:
           # we just built caches, more levels to go
@@ -178,6 +183,10 @@ if options.atomic:
 else:
     root.system.mem_mode = 'timing'
 
+# The system port is never used in the tester so merely connect it
+# to avoid problems
+root.system.system_port = root.system.physmem.port
+
 # Not much point in this being higher than the L1 latency
 m5.ticks.setGlobalFrequency('1ns')
 

configs/splash2/cluster.py

@@ -221,19 +221,19 @@ system.l2 = L2(size = options.l2size, assoc = 8)
 # Connect the L2 cache and memory together
 # ----------------------
 
-system.physmem.port = system.membus.port
+system.physmem.port = system.membus.master
-system.l2.cpu_side = system.toL2bus.port
+system.l2.cpu_side = system.toL2bus.slave
-system.l2.mem_side = system.membus.port
+system.l2.mem_side = system.membus.master
 
 # ----------------------
 # Connect the L2 cache and clusters together
 # ----------------------
 for cluster in clusters:
-    cluster.l1.cpu_side = cluster.clusterbus.port
+    cluster.l1.cpu_side = cluster.clusterbus.master
-    cluster.l1.mem_side = system.toL2bus.port
+    cluster.l1.mem_side = system.toL2bus.slave
     for cpu in cluster.cpus:
-        cpu.icache_port = cluster.clusterbus.port
+        cpu.icache_port = cluster.clusterbus.slave
-        cpu.dcache_port = cluster.clusterbus.port
+        cpu.dcache_port = cluster.clusterbus.slave
 
 # ----------------------
 # Define the root

configs/splash2/run.py

@@ -207,10 +207,10 @@ system.l2 = L2(size = options.l2size, assoc = 8)
 # Connect the L2 cache and memory together
 # ----------------------
 
-system.physmem.port = system.membus.port
+system.physmem.port = system.membus.master
-system.l2.cpu_side = system.toL2bus.port
+system.l2.cpu_side = system.toL2bus.master
-system.l2.mem_side = system.membus.port
+system.l2.mem_side = system.membus.slave
-system.system_port = system.membus.port
+system.system_port = system.membus.slave
 
 # ----------------------
 # Connect the L2 cache and clusters together

src/dev/arm/RealView.py

@@ -376,7 +376,7 @@ class VExpress_ELT(RealView):
        self.elba_kmi1.pio       = bus.master
        self.cf_ctrl.pio         = bus.master
        self.cf_ctrl.config      = bus.master
-       self.cf_ctrl.dma         = bus.port
+       self.cf_ctrl.dma         = bus.slave
        self.ide.pio             = bus.master
        self.ide.config          = bus.master
        self.ide.dma             = bus.slave

src/dev/mips/Malta.py

@@ -63,6 +63,6 @@ class Malta(Platform):
     # earlier, since the bus object itself is typically defined at the
     # System level.
     def attachIO(self, bus):
-        self.cchip.pio = bus.port
+        self.cchip.pio = bus.master
-        self.io.pio = bus.port
+        self.io.pio = bus.master
-        self.uart.pio = bus.port
+        self.uart.pio = bus.master

src/dev/sparc/T1000.py

@@ -109,8 +109,8 @@ class T1000(Platform):
     iob = Iob()
     # Attach I/O devices that are on chip
     def attachOnChipIO(self, bus):
-        self.iob.pio = bus.port
+        self.iob.pio = bus.master
-        self.htod.pio = bus.port
+        self.htod.pio = bus.master
 
 
     # Attach I/O devices to specified bus object.  Can't do this
@@ -119,17 +119,17 @@ class T1000(Platform):
     def attachIO(self, bus):
         self.hvuart.terminal = self.hterm
         self.puart0.terminal = self.pterm
-        self.fake_clk.pio = bus.port
+        self.fake_clk.pio = bus.master
-        self.fake_membnks.pio = bus.port
+        self.fake_membnks.pio = bus.master
-        self.fake_l2_1.pio = bus.port
+        self.fake_l2_1.pio = bus.master
-        self.fake_l2_2.pio = bus.port
+        self.fake_l2_2.pio = bus.master
-        self.fake_l2_3.pio = bus.port
+        self.fake_l2_3.pio = bus.master
-        self.fake_l2_4.pio = bus.port
+        self.fake_l2_4.pio = bus.master
-        self.fake_l2esr_1.pio = bus.port
+        self.fake_l2esr_1.pio = bus.master
-        self.fake_l2esr_2.pio = bus.port
+        self.fake_l2esr_2.pio = bus.master
-        self.fake_l2esr_3.pio = bus.port
+        self.fake_l2esr_3.pio = bus.master
-        self.fake_l2esr_4.pio = bus.port
+        self.fake_l2esr_4.pio = bus.master
-        self.fake_ssi.pio = bus.port
+        self.fake_ssi.pio = bus.master
-        self.fake_jbi.pio = bus.port
+        self.fake_jbi.pio = bus.master
-        self.puart0.pio = bus.port
+        self.puart0.pio = bus.master
-        self.hvuart.pio = bus.port
+        self.hvuart.pio = bus.master