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ARM: Replace the ARM decode of CP15 MCR and MRC instructions.

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This commit is contained in:
Gabe Black 2010-06-02 12:58:08 -05:00
parent 35f0c01fea
commit 6c9ab5d898
1 changed files with 1 additions and 47 deletions
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48
src/arch/arm/isa/decoder/arm.isa
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@ -173,53 +173,7 @@ format DataOp {
}
} // MEDIA_OPCODE (MISC_OPCODE 0x1)
} // MISC_OPCODE (CPNUM 0xA)
0xf: decode RN {
// Barrriers, Cache Maintence, NOPS
7: decode OPCODE_23_21 {
0: decode RM {
0: decode OPC2 {
4: decode OPCODE_20 {
0: PredOp::mcr_cp15_nop1({{ }}); // was wfi
}
}
1: WarnUnimpl::cp15_cache_maint();
4: WarnUnimpl::cp15_par();
5: decode OPC2 {
0,1: WarnUnimpl::cp15_cache_maint2();
4: PredOp::cp15_isb({{ ; }}, IsMemBarrier, IsSerializeBefore);
6,7: WarnUnimpl::cp15_bp_maint();
}
6: WarnUnimpl::cp15_cache_maint3();
8: WarnUnimpl::cp15_va_to_pa();
10: decode OPC2 {
1,2: WarnUnimpl::cp15_cache_maint3();
4: PredOp::cp15_dsb({{ ; }}, IsMemBarrier, IsSerializeBefore);
5: PredOp::cp15_dmb({{ ; }}, IsMemBarrier, IsSerializeBefore);
}
11: WarnUnimpl::cp15_cache_maint4();
13: decode OPC2 {
1: decode OPCODE_20 {
0: PredOp::mcr_cp15_nop2({{ }}); // was prefetch
}
}
14: WarnUnimpl::cp15_cache_maint5();
} // RM
} // OPCODE_23_21 CR
// Thread ID and context ID registers
// Thread ID register needs cheaper access than miscreg
13: WarnUnimpl::mcr_mrc_cp15_c7();
// All the rest
default: decode OPCODE_20 {
0: PredOp::mcr_cp15({{
fault = setCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2);
}});
1: PredOp::mrc_cp15({{
fault = readCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2);
}});
}
} // RN
0xf: McrMrc15::mcrMrc15();
} // CPNUM (OP4 == 1)
} //OPCODE_4