ARM: Replace the ARM decode of CP15 MCR and MRC instructions.
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1 changed files with 1 additions and 47 deletions
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@ -173,53 +173,7 @@ format DataOp {
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}
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}
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} // MEDIA_OPCODE (MISC_OPCODE 0x1)
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} // MEDIA_OPCODE (MISC_OPCODE 0x1)
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} // MISC_OPCODE (CPNUM 0xA)
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} // MISC_OPCODE (CPNUM 0xA)
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0xf: decode RN {
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0xf: McrMrc15::mcrMrc15();
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// Barrriers, Cache Maintence, NOPS
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7: decode OPCODE_23_21 {
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0: decode RM {
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0: decode OPC2 {
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4: decode OPCODE_20 {
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0: PredOp::mcr_cp15_nop1({{ }}); // was wfi
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}
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}
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1: WarnUnimpl::cp15_cache_maint();
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4: WarnUnimpl::cp15_par();
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5: decode OPC2 {
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0,1: WarnUnimpl::cp15_cache_maint2();
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4: PredOp::cp15_isb({{ ; }}, IsMemBarrier, IsSerializeBefore);
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6,7: WarnUnimpl::cp15_bp_maint();
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}
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6: WarnUnimpl::cp15_cache_maint3();
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8: WarnUnimpl::cp15_va_to_pa();
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10: decode OPC2 {
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1,2: WarnUnimpl::cp15_cache_maint3();
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4: PredOp::cp15_dsb({{ ; }}, IsMemBarrier, IsSerializeBefore);
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5: PredOp::cp15_dmb({{ ; }}, IsMemBarrier, IsSerializeBefore);
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}
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11: WarnUnimpl::cp15_cache_maint4();
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13: decode OPC2 {
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1: decode OPCODE_20 {
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0: PredOp::mcr_cp15_nop2({{ }}); // was prefetch
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}
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}
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14: WarnUnimpl::cp15_cache_maint5();
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} // RM
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} // OPCODE_23_21 CR
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// Thread ID and context ID registers
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// Thread ID register needs cheaper access than miscreg
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13: WarnUnimpl::mcr_mrc_cp15_c7();
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// All the rest
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default: decode OPCODE_20 {
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0: PredOp::mcr_cp15({{
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fault = setCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2);
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}});
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1: PredOp::mrc_cp15({{
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fault = readCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2);
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}});
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}
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} // RN
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} // CPNUM (OP4 == 1)
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} // CPNUM (OP4 == 1)
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} //OPCODE_4
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} //OPCODE_4
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