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Remove unnecessary building of FreeList/RenameMap in InOrder. Clean-up comments and O3 extensions InOrder Thread Context

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This commit is contained in:
Korey Sewell 2009-02-20 11:02:48 -05:00
parent c41c9cf3a6
commit 6c5afe6346
5 changed files with 4 additions and 111 deletions
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6
src/arch/mips/regfile.cc
View file

@ -199,12 +199,6 @@ MipsISA::copyRegs(ThreadContext *src, ThreadContext *dest)
panic("Copy Regs Not Implemented Yet\n");
}
void
MipsISA::copyRegs(ThreadContext *src, ThreadContext *dest);
{
panic("Copy Regs Not Implemented Yet\n");
}
void
MipsISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
{

5
src/cpu/inorder/SConscript
View file

@ -42,13 +42,12 @@ if 'InOrderCPU' in env['CPU_MODELS']:
TraceFlag('InOrderCPU')
TraceFlag('InOrderMDU')
TraceFlag('RegDepMap')
TraceFlag('Rename')
TraceFlag('InOrderDynInst')
TraceFlag('Resource')
TraceFlag('RefCount')
CompoundFlag('InOrderCPUAll', [ 'InOrderStage', 'InOrderStall', 'InOrderCPU',
'InOrderMDU', 'RegDepMap', 'Resource', 'Rename'])
'InOrderMDU', 'RegDepMap', 'Resource'])
Source('pipeline_traits.cc')
Source('inorder_dyn_inst.cc')
@ -74,8 +73,6 @@ if 'InOrderCPU' in env['CPU_MODELS']:
Source('../o3/btb.cc')
Source('../o3/tournament_pred.cc')
Source('../o3/2bit_local_pred.cc')
Source('../o3/free_list.cc')
Source('../o3/rename_map.cc')
Source('../o3/ras.cc')
Source('thread_context.cc')
Source('cpu.cc')

9
src/cpu/inorder/cpu.hh
View file

@ -77,7 +77,6 @@ class InOrderCPU : public BaseCPU
typedef TheISA::FloatRegBits FloatRegBits;
typedef TheISA::MiscReg MiscReg;
typedef TheISA::RegFile RegFile;
typedef SimpleRenameMap RenameMap;
//DynInstPtr TypeDefs
typedef ThePipeline::DynInstPtr DynInstPtr;
@ -586,14 +585,6 @@ class InOrderCPU : public BaseCPU
std::list<unsigned> fetchPriorityList;
/** Rename Map for architectural-to-physical register mappings.
* In a In-order processor, the mapping is fixed
* (e.g. Thread 1: 0-31, Thread 1: 32-63, etc.)
* In a Out-of-Order processor, this is used to maintain
* sequential consistency (?right word here?).
*/
RenameMap renameMap[ThePipeline::MaxThreads];
protected:
/** Active Threads List */
std::list<unsigned> activeThreads;

93
src/cpu/inorder/thread_context.cc
View file

@ -44,7 +44,6 @@ InOrderThreadContext::takeOverFrom(ThreadContext *old_context)
// copy over functional state
setStatus(old_context->status());
copyArchRegs(old_context);
//setCpuId(0/*old_context->readCpuId()*/);
thread->funcExeInst = old_context->readFuncExeInst();
old_context->setStatus(ThreadContext::Unallocated);
@ -61,18 +60,8 @@ InOrderThreadContext::activate(int delay)
if (thread->status() == ThreadContext::Active)
return;
// @TODO: Make this process useful again...
//if (thread->status() == ThreadContext::Unallocated) {
// Allows the CPU to drain partitioned resources
// before inserting thread into the CPU
// (e.g. bind physical registers)
//cpu->activateWhenReady(thread->readTid());
//return;
//}
thread->setStatus(ThreadContext::Active);
// status() == Suspended
cpu->activateContext(thread->readTid(), delay);
}
@ -157,37 +146,9 @@ InOrderThreadContext:: getInst()
void
InOrderThreadContext::copyArchRegs(ThreadContext *tc)
InOrderThreadContext::copyArchRegs(ThreadContext *src_tc)
{
unsigned tid = thread->readTid();
PhysRegIndex renamed_reg;
// First loop through the integer registers.
for (int i = 0; i < TheISA::NumIntRegs; ++i) {
renamed_reg = cpu->renameMap[tid].lookup(i);
DPRINTF(InOrderCPU, "Copying over register %i, had data %lli, "
"now has data %lli.\n",
renamed_reg, cpu->readIntReg(renamed_reg, tid),
tc->readIntReg(i));
cpu->setIntReg(renamed_reg, tc->readIntReg(i), tid);
}
// Then loop through the floating point registers.
for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
renamed_reg = cpu->renameMap[tid].lookup(i + TheISA::FP_Base_DepTag);
cpu->setFloatRegBits(renamed_reg, tc->readFloatRegBits(i), tid);
}
// Copy the misc regs.
TheISA::copyMiscRegs(tc, this);
// Then finally set the PC and the next PC.
cpu->setPC(tc->readPC(), tid);
cpu->setNextPC(tc->readNextPC(), tid);
cpu->setNextNPC(tc->readNextNPC(), tid);
this->thread->funcExeInst = tc->readFuncExeInst();
TheISA::copyRegs(src_tc, this);
}
@ -236,33 +197,18 @@ void
InOrderThreadContext::setIntReg(int reg_idx, uint64_t val)
{
cpu->setIntReg(reg_idx, val, thread->readTid());
// Squash if we're not already in a state update mode.
//if (!thread->trapPending && !thread->inSyscall) {
// cpu->squashFromTC(thread->readTid());
//}
}
void
InOrderThreadContext::setFloatReg(int reg_idx, FloatReg val, int width)
{
cpu->setFloatReg(reg_idx, val, thread->readTid(), width);
// Squash if we're not already in a state update mode.
//if (!thread->trapPending && !thread->inSyscall) {
//cpu->squashFromTC(thread->readTid());
//}
}
void
InOrderThreadContext::setFloatReg(int reg_idx, FloatReg val)
{
cpu->setFloatReg(reg_idx, val, thread->readTid());
// Squash if we're not already in a state update mode.
//if (!thread->trapPending && !thread->inSyscall) {
//cpu->squashFromTC(thread->readTid());
//}
}
void
@ -270,22 +216,12 @@ InOrderThreadContext::setFloatRegBits(int reg_idx, FloatRegBits val,
int width)
{
cpu->setFloatRegBits(reg_idx, val, thread->readTid(), width);
// Squash if we're not already in a state update mode.
//if (!thread->trapPending && !thread->inSyscall) {
//cpu->squashFromTC(thread->readTid());
//}
}
void
InOrderThreadContext::setFloatRegBits(int reg_idx, FloatRegBits val)
{
cpu->setFloatRegBits(reg_idx, val, thread->readTid());
// Squash if we're not already in a state update mode.
//if (!thread->trapPending && !thread->inSyscall) {
//cpu->squashFromTC(thread->readTid());
//}
}
void
@ -299,11 +235,6 @@ InOrderThreadContext::setPC(uint64_t val)
{
DPRINTF(InOrderCPU, "Setting PC to %08p\n", val);
cpu->setPC(val, thread->readTid());
// Squash if we're not already in a state update mode.
//if (!thread->trapPending && !thread->inSyscall) {
//cpu->squashFromTC(thread->readTid());
//}
}
void
@ -311,11 +242,6 @@ InOrderThreadContext::setNextPC(uint64_t val)
{
DPRINTF(InOrderCPU, "Setting NPC to %08p\n", val);
cpu->setNextPC(val, thread->readTid());
// Squash if we're not already in a state update mode.
//if (!thread->trapPending && !thread->inSyscall) {
//cpu->squashFromTC(thread->readTid());
//}
}
void
@ -323,33 +249,18 @@ InOrderThreadContext::setNextNPC(uint64_t val)
{
DPRINTF(InOrderCPU, "Setting NNPC to %08p\n", val);
cpu->setNextNPC(val, thread->readTid());
// Squash if we're not already in a state update mode.
//if (!thread->trapPending && !thread->inSyscall) {
//cpu->squashFromTC(thread->readTid());
//}
}
void
InOrderThreadContext::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
{
cpu->setMiscRegNoEffect(misc_reg, val, thread->readTid());
// Squash if we're not already in a state update mode.
//if (!thread->trapPending && !thread->inSyscall) {
//cpu->squashFromTC(thread->readTid());
//}
}
void
InOrderThreadContext::setMiscReg(int misc_reg, const MiscReg &val)
{
cpu->setMiscReg(misc_reg, val, thread->readTid());
// Squash if we're not already in a state update mode.
//if (!thread->trapPending && !thread->inSyscall) {
//cpu->squashFromTC(thread->readTid());
//}
}
TheISA::IntReg

2
src/cpu/inorder/thread_context.hh
View file

@ -147,7 +147,7 @@ class InOrderThreadContext : public ThreadContext
virtual TheISA::MachInst getInst();
/** Copies the architectural registers from another TC into this TC. */
virtual void copyArchRegs(ThreadContext *tc);
virtual void copyArchRegs(ThreadContext *src_tc);
/** Resets all architectural registers to 0. */
virtual void clearArchRegs();