diff --git a/src/arch/x86/isa/insts/romutil.py b/src/arch/x86/isa/insts/romutil.py
index 2724637d1..9b4a80d44 100644
--- a/src/arch/x86/isa/insts/romutil.py
+++ b/src/arch/x86/isa/insts/romutil.py
@@ -43,18 +43,9 @@ def rom
     ld t2, idtr, [1, t0, t4], 8, dataSize=8, addressSize=8
     ld t4, idtr, [1, t0, t4], dataSize=8, addressSize=8
 
-    # Check permissions
+    # Make sure the descriptor is a legal gate.
     chks t1, t4, IntGateCheck
 
-    mov t1, t1, t4, dataSize=8
-
-    # Check that it's the right type
-    srli t4, t1, 40, dataSize=8
-    andi t4, t4, 0xe, dataSize=8
-    xori t4, t4, 0xe, flags=(EZF,), dataSize=8
-    fault "new GeneralProtection(0)", flags=(nCEZF,)
-
-
     #
     # Get the target CS descriptor using the selector in the gate
     # descriptor.
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index 492452a51..200024690 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -1067,9 +1067,15 @@ let {{
                         "not implemented.\\n");
                 break;
               case SegIntGateCheck:
+                // Check permissions.
                 if (desc.dpl < m5reg.cpl) {
                     fault = new GeneralProtection((uint16_t)selector);
                 }
+                // Make sure the gate's the right type.
+                if (m5reg.mode == LongMode && ((desc.type & 0xe) != 0xe) ||
+                        ((desc.type & 0x6) != 0x6)) {
+                    fault = new GeneralProtection(0);
+                }
                 break;
               case SegSSCheck:
                 if (selector.si || selector.ti) {