ARM: Allow accesses to the software thread id registers.
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1 changed files with 5 additions and 5 deletions
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@ -84,6 +84,9 @@ namespace ArmISA
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MISCREG_SCTLR = MISCREG_CP15_START,
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MISCREG_SCTLR = MISCREG_CP15_START,
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MISCREG_DCCISW,
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MISCREG_DCCISW,
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MISCREG_CONTEXTIDR,
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MISCREG_CONTEXTIDR,
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MISCREG_TPIDRURW,
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MISCREG_TPIDRURO,
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MISCREG_TPIDRPRW,
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MISCREG_CP15_UNIMP_START,
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MISCREG_CP15_UNIMP_START,
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MISCREG_CTR = MISCREG_CP15_UNIMP_START,
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MISCREG_CTR = MISCREG_CP15_UNIMP_START,
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MISCREG_TCMTR,
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MISCREG_TCMTR,
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@ -138,9 +141,6 @@ namespace ArmISA
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MISCREG_CP15DMB,
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MISCREG_CP15DMB,
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MISCREG_DCCMVAU,
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MISCREG_DCCMVAU,
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MISCREG_DCCIMVAC,
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MISCREG_DCCIMVAC,
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MISCREG_TPIDRURW,
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MISCREG_TPIDRURO,
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MISCREG_TPIDRPRW,
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MISCREG_CP15_END,
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MISCREG_CP15_END,
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@ -158,7 +158,8 @@ namespace ArmISA
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"cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
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"cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
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"spsr_mon", "spsr_und", "spsr_abt",
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"spsr_mon", "spsr_und", "spsr_abt",
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"fpsr", "fpsid", "fpscr", "fpexc",
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"fpsr", "fpsid", "fpscr", "fpexc",
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"sctlr", "dccisw", "contextidr", "ctr", "tcmtr", "mpuir", "mpidr", "midr",
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"sctlr", "dccisw", "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
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"ctr", "tcmtr", "mpuir", "mpidr", "midr",
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"id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
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"id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
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"id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
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"id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
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"id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
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"id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
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@ -168,7 +169,6 @@ namespace ArmISA
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"rgnr", "icialluis", "bpiallis", "iciallu", "icimvau",
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"rgnr", "icialluis", "bpiallis", "iciallu", "icimvau",
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"cp15isb", "bpiall", "bpimva", "dcimvac", "dcisw", "dccmvac", "mccsw",
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"cp15isb", "bpiall", "bpimva", "dcimvac", "dcisw", "dccmvac", "mccsw",
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"cp15dsb", "cp15dmb", "dccmvau", "dccimvac",
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"cp15dsb", "cp15dmb", "dccmvau", "dccimvac",
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"tpidrurw", "tpidruro", "tpidrprw",
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"nop", "raz"
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"nop", "raz"
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};
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};
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