ARM: Allow accesses to the software thread id registers.

This commit is contained in:
Gabe Black 2010-06-02 12:58:08 -05:00
parent 54850e4d23
commit 6ae4d34a12

View file

@ -84,6 +84,9 @@ namespace ArmISA
MISCREG_SCTLR = MISCREG_CP15_START, MISCREG_SCTLR = MISCREG_CP15_START,
MISCREG_DCCISW, MISCREG_DCCISW,
MISCREG_CONTEXTIDR, MISCREG_CONTEXTIDR,
MISCREG_TPIDRURW,
MISCREG_TPIDRURO,
MISCREG_TPIDRPRW,
MISCREG_CP15_UNIMP_START, MISCREG_CP15_UNIMP_START,
MISCREG_CTR = MISCREG_CP15_UNIMP_START, MISCREG_CTR = MISCREG_CP15_UNIMP_START,
MISCREG_TCMTR, MISCREG_TCMTR,
@ -138,9 +141,6 @@ namespace ArmISA
MISCREG_CP15DMB, MISCREG_CP15DMB,
MISCREG_DCCMVAU, MISCREG_DCCMVAU,
MISCREG_DCCIMVAC, MISCREG_DCCIMVAC,
MISCREG_TPIDRURW,
MISCREG_TPIDRURO,
MISCREG_TPIDRPRW,
MISCREG_CP15_END, MISCREG_CP15_END,
@ -158,7 +158,8 @@ namespace ArmISA
"cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
"spsr_mon", "spsr_und", "spsr_abt", "spsr_mon", "spsr_und", "spsr_abt",
"fpsr", "fpsid", "fpscr", "fpexc", "fpsr", "fpsid", "fpscr", "fpexc",
"sctlr", "dccisw", "contextidr", "ctr", "tcmtr", "mpuir", "mpidr", "midr", "sctlr", "dccisw", "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
"ctr", "tcmtr", "mpuir", "mpidr", "midr",
"id_pfr0", "id_pfr1", "id_dfr0", "id_afr0", "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
"id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3", "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
"id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5", "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
@ -168,7 +169,6 @@ namespace ArmISA
"rgnr", "icialluis", "bpiallis", "iciallu", "icimvau", "rgnr", "icialluis", "bpiallis", "iciallu", "icimvau",
"cp15isb", "bpiall", "bpimva", "dcimvac", "dcisw", "dccmvac", "mccsw", "cp15isb", "bpiall", "bpimva", "dcimvac", "dcisw", "dccmvac", "mccsw",
"cp15dsb", "cp15dmb", "dccmvau", "dccimvac", "cp15dsb", "cp15dmb", "dccmvau", "dccimvac",
"tpidrurw", "tpidruro", "tpidrprw",
"nop", "raz" "nop", "raz"
}; };