Get rid of Packet result field. Error responses are
now encoded in cmd field. --HG-- extra : convert_revision : d67819b7e3ee4b9a5bf08541104de0a89485e90b
This commit is contained in:
parent
749126e011
commit
6ab53415ef
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@ -1023,7 +1023,7 @@ doMmuReadError:
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panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
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(uint32_t)asi, va);
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}
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pkt->result = Packet::Success;
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pkt->makeAtomicResponse();
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return tc->getCpuPtr()->cycles(1);
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}
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@ -1268,7 +1268,7 @@ doMmuWriteError:
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panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
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(uint32_t)pkt->req->getAsi(), pkt->getAddr(), data);
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}
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pkt->result = Packet::Success;
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pkt->makeAtomicResponse();
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return tc->getCpuPtr()->cycles(1);
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}
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@ -628,12 +628,6 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid
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// Now do the timing access to see whether or not the instruction
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// exists within the cache.
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if (!icachePort->sendTiming(data_pkt)) {
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if (data_pkt->result == Packet::BadAddress) {
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fault = TheISA::genMachineCheckFault();
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delete mem_req;
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memReq[tid] = NULL;
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warn("Bad address!\n");
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}
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assert(retryPkt == NULL);
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assert(retryTid == -1);
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DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
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@ -653,8 +653,6 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
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data_pkt->senderState = state;
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if (!dcachePort->sendTiming(data_pkt)) {
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Packet::Result result = data_pkt->result;
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// Delete state and data packet because a load retry
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// initiates a pipeline restart; it does not retry.
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delete state;
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@ -663,10 +661,6 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
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req = NULL;
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if (result == Packet::BadAddress) {
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return TheISA::genMachineCheckFault();
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}
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// If the access didn't succeed, tell the LSQ by setting
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// the retry thread id.
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lsq->setRetryTid(lsqID);
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@ -690,9 +690,6 @@ LSQUnit<Impl>::writebackStores()
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}
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if (!dcachePort->sendTiming(data_pkt)) {
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if (data_pkt->result == Packet::BadAddress) {
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panic("LSQ sent out a bad address for a completed store!");
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}
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// Need to handle becoming blocked on a store.
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DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will"
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"retry later\n",
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@ -844,26 +841,6 @@ LSQUnit<Impl>::storePostSend(PacketPtr pkt)
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#endif
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}
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if (pkt->result != Packet::Success) {
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DPRINTF(LSQUnit,"D-Cache Write Miss on idx:%i!\n",
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storeWBIdx);
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DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
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storeQueue[storeWBIdx].inst->seqNum);
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//mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum);
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//DPRINTF(LSQUnit, "Added MSHR. count = %i\n",mshrSeqNums.size());
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// @todo: Increment stat here.
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} else {
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DPRINTF(LSQUnit,"D-Cache: Write Hit on idx:%i !\n",
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storeWBIdx);
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DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
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storeQueue[storeWBIdx].inst->seqNum);
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}
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incrStIdx(storeWBIdx);
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}
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@ -952,9 +929,6 @@ LSQUnit<Impl>::recvRetry()
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assert(retryPkt != NULL);
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if (dcachePort->sendTiming(retryPkt)) {
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if (retryPkt->result == Packet::BadAddress) {
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panic("LSQ sent out a bad address for a completed store!");
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}
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storePostSend(retryPkt);
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retryPkt = NULL;
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isStoreBlocked = false;
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@ -661,16 +661,6 @@ OzoneLWLSQ<Impl>::read(RequestPtr req, T &data, int load_idx)
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cpu->lockFlag = true;
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}
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if (data_pkt->result != Packet::Success) {
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DPRINTF(OzoneLSQ, "OzoneLSQ: D-cache miss!\n");
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DPRINTF(Activity, "Activity: ld accessing mem miss [sn:%lli]\n",
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inst->seqNum);
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} else {
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DPRINTF(OzoneLSQ, "OzoneLSQ: D-cache hit!\n");
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DPRINTF(Activity, "Activity: ld accessing mem hit [sn:%lli]\n",
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inst->seqNum);
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}
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return NoFault;
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}
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@ -853,24 +853,6 @@ OzoneLWLSQ<Impl>::storePostSend(PacketPtr pkt, DynInstPtr &inst)
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}
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#endif
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}
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if (pkt->result != Packet::Success) {
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DPRINTF(OzoneLSQ,"D-Cache Write Miss!\n");
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DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
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inst->seqNum);
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//mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum);
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//DPRINTF(OzoneLWLSQ, "Added MSHR. count = %i\n",mshrSeqNums.size());
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// @todo: Increment stat here.
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} else {
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DPRINTF(OzoneLSQ,"D-Cache: Write Hit!\n");
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DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
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inst->seqNum);
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}
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}
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template <class Impl>
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@ -148,23 +148,9 @@ AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
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icachePort.snoopRangeSent = false;
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dcachePort.snoopRangeSent = false;
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ifetch_req = new Request();
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ifetch_req->setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT
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ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast);
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ifetch_pkt->dataStatic(&inst);
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data_read_req = new Request();
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data_read_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
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data_read_pkt = new Packet(data_read_req, MemCmd::ReadReq,
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Packet::Broadcast);
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data_read_pkt->dataStatic(&dataReg);
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data_write_req = new Request();
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data_write_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
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data_write_pkt = new Packet(data_write_req, MemCmd::WriteReq,
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Packet::Broadcast);
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data_swap_pkt = new Packet(data_write_req, MemCmd::SwapReq,
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Packet::Broadcast);
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ifetch_req.setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT
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data_read_req.setThreadContext(p->cpu_id, 0); // Add thread ID here too
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data_write_req.setThreadContext(p->cpu_id, 0); // Add thread ID here too
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}
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@ -282,9 +268,7 @@ Fault
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AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
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{
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// use the CPU's statically allocated read request and packet objects
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Request *req = data_read_req;
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PacketPtr pkt = data_read_pkt;
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Request *req = &data_read_req;
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req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
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if (traceData) {
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@ -296,19 +280,15 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
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// Now do the access.
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if (fault == NoFault) {
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pkt->reinitFromRequest();
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Packet pkt = Packet(req, MemCmd::ReadReq, Packet::Broadcast);
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pkt.dataStatic(&data);
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if (req->isMmapedIpr())
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dcache_latency = TheISA::handleIprRead(thread->getTC(),pkt);
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dcache_latency = TheISA::handleIprRead(thread->getTC(), &pkt);
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else
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dcache_latency = dcachePort.sendAtomic(pkt);
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dcache_latency = dcachePort.sendAtomic(&pkt);
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dcache_access = true;
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#if !defined(NDEBUG)
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if (pkt->result != Packet::Success)
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panic("Unable to find responder for address pa = %#X va = %#X\n",
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pkt->req->getPaddr(), pkt->req->getVaddr());
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#endif
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data = pkt->get<T>();
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assert(!pkt.isError());
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if (req->isLocked()) {
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TheISA::handleLockedRead(thread, req);
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@ -378,16 +358,9 @@ Fault
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AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
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{
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// use the CPU's statically allocated write request and packet objects
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Request *req = data_write_req;
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PacketPtr pkt;
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Request *req = &data_write_req;
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req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
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if (req->isSwap())
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pkt = data_swap_pkt;
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else
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pkt = data_write_pkt;
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if (traceData) {
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traceData->setAddr(addr);
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}
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@ -397,6 +370,11 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
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// Now do the access.
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if (fault == NoFault) {
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Packet pkt =
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Packet(req, req->isSwap() ? MemCmd::SwapReq : MemCmd::WriteReq,
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Packet::Broadcast);
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pkt.dataStatic(&data);
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bool do_access = true; // flag to suppress cache access
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if (req->isLocked()) {
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@ -409,27 +387,19 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
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if (do_access) {
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pkt->reinitFromRequest();
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pkt->dataStatic(&data);
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if (req->isMmapedIpr()) {
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dcache_latency = TheISA::handleIprWrite(thread->getTC(), pkt);
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dcache_latency = TheISA::handleIprWrite(thread->getTC(), &pkt);
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} else {
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data = htog(data);
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dcache_latency = dcachePort.sendAtomic(pkt);
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dcache_latency = dcachePort.sendAtomic(&pkt);
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}
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dcache_access = true;
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#if !defined(NDEBUG)
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if (pkt->result != Packet::Success)
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panic("Unable to find responder for address pa = %#X va = %#X\n",
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pkt->req->getPaddr(), pkt->req->getVaddr());
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#endif
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assert(!pkt.isError());
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}
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if (req->isSwap()) {
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assert(res);
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*res = pkt->get<T>();
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*res = pkt.get<T>();
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} else if (res) {
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*res = req->getExtraData();
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}
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@ -513,7 +483,7 @@ AtomicSimpleCPU::tick()
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if (!curStaticInst || !curStaticInst->isDelayedCommit())
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checkForInterrupts();
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Fault fault = setupFetchRequest(ifetch_req);
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Fault fault = setupFetchRequest(&ifetch_req);
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if (fault == NoFault) {
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Tick icache_latency = 0;
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@ -524,9 +494,11 @@ AtomicSimpleCPU::tick()
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//if(predecoder.needMoreBytes())
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//{
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icache_access = true;
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ifetch_pkt->reinitFromRequest();
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Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq,
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Packet::Broadcast);
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ifetch_pkt.dataStatic(&inst);
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icache_latency = icachePort.sendAtomic(ifetch_pkt);
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icache_latency = icachePort.sendAtomic(&ifetch_pkt);
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// ifetch_req is initialized to read the instruction directly
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// into the CPU object's inst field.
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//}
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@ -121,13 +121,9 @@ class AtomicSimpleCPU : public BaseSimpleCPU
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};
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DcachePort dcachePort;
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Request *ifetch_req;
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PacketPtr ifetch_pkt;
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Request *data_read_req;
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PacketPtr data_read_pkt;
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Request *data_write_req;
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PacketPtr data_write_pkt;
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PacketPtr data_swap_pkt;
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Request ifetch_req;
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Request data_read_req;
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Request data_write_req;
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bool dcache_access;
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Tick dcache_latency;
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@ -131,9 +131,6 @@ class BaseSimpleCPU : public BaseCPU
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// The predecoder
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TheISA::Predecoder predecoder;
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// Static data storage
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TheISA::LargestRead dataReg;
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StaticInstPtr curStaticInst;
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StaticInstPtr curMacroStaticInst;
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@ -501,7 +501,7 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
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{
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// received a response from the icache: execute the received
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// instruction
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assert(pkt->result == Packet::Success);
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assert(!pkt->isError());
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assert(_status == IcacheWaitResponse);
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_status = Running;
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@ -569,7 +569,7 @@ TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
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return true;
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}
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else if (pkt->result == Packet::Nacked) {
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else if (pkt->wasNacked()) {
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assert(cpu->_status == IcacheWaitResponse);
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pkt->reinitNacked();
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if (!sendTiming(pkt)) {
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@ -600,7 +600,7 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
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{
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// received a response from the dcache: complete the load or store
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// instruction
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assert(pkt->result == Packet::Success);
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assert(!pkt->isError());
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assert(_status == DcacheWaitResponse);
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_status = Running;
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@ -663,7 +663,7 @@ TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
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return true;
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}
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else if (pkt->result == Packet::Nacked) {
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else if (pkt->wasNacked()) {
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assert(cpu->_status == DcacheWaitResponse);
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pkt->reinitNacked();
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if (!sendTiming(pkt)) {
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@ -102,7 +102,6 @@ AlphaConsole::read(PacketPtr pkt)
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* machine dependent address swizzle is required?
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*/
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assert(pkt->result == Packet::Unknown);
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assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
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Addr daddr = pkt->getAddr() - pioAddr;
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@ -130,7 +129,7 @@ AlphaConsole::read(PacketPtr pkt)
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/* Old console code read in everyting as a 32bit int
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* we now break that for better error checking.
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*/
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pkt->result = Packet::BadAddress;
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pkt->setBadAddress();
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}
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DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr,
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pkt->get<uint32_t>());
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@ -187,17 +186,15 @@ AlphaConsole::read(PacketPtr pkt)
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pkt->get<uint64_t>());
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break;
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default:
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pkt->result = Packet::BadAddress;
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pkt->setBadAddress();
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}
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if (pkt->result == Packet::Unknown)
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pkt->result = Packet::Success;
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pkt->makeAtomicResponse();
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return pioDelay;
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}
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Tick
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AlphaConsole::write(PacketPtr pkt)
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{
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assert(pkt->result == Packet::Unknown);
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assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
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Addr daddr = pkt->getAddr() - pioAddr;
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@ -245,7 +242,7 @@ AlphaConsole::write(PacketPtr pkt)
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panic("Unknown 64bit access, %#x\n", daddr);
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}
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pkt->result = Packet::Success;
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pkt->makeAtomicResponse();
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return pioDelay;
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}
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@ -78,7 +78,6 @@ TsunamiCChip::read(PacketPtr pkt)
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{
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DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt->getAddr(), pkt->getSize());
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assert(pkt->result == Packet::Unknown);
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assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
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Addr regnum = (pkt->getAddr() - pioAddr) >> 6;
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@ -181,7 +180,7 @@ TsunamiCChip::read(PacketPtr pkt)
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DPRINTF(Tsunami, "Tsunami CChip: read regnum=%#x size=%d data=%lld\n",
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regnum, pkt->getSize(), pkt->get<uint64_t>());
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pkt->result = Packet::Success;
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pkt->makeAtomicResponse();
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return pioDelay;
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}
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@ -365,7 +364,7 @@ TsunamiCChip::write(PacketPtr pkt)
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panic("default in cchip read reached, accessing 0x%x\n");
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} // swtich(regnum)
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} // not BIG_TSUNAMI write
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pkt->result = Packet::Success;
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pkt->makeAtomicResponse();
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return pioDelay;
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}
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@ -461,7 +461,6 @@ TsunamiIO::frequency() const
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Tick
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TsunamiIO::read(PacketPtr pkt)
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{
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assert(pkt->result == Packet::Unknown);
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assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
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Addr daddr = pkt->getAddr() - pioAddr;
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@ -520,14 +519,13 @@ TsunamiIO::read(PacketPtr pkt)
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} else {
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panic("I/O Read - invalid size - va %#x size %d\n", pkt->getAddr(), pkt->getSize());
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}
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pkt->result = Packet::Success;
|
||||
pkt->makeAtomicResponse();
|
||||
return pioDelay;
|
||||
}
|
||||
|
||||
Tick
|
||||
TsunamiIO::write(PacketPtr pkt)
|
||||
{
|
||||
assert(pkt->result == Packet::Unknown);
|
||||
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
|
||||
Addr daddr = pkt->getAddr() - pioAddr;
|
||||
|
||||
|
@ -600,7 +598,7 @@ TsunamiIO::write(PacketPtr pkt)
|
|||
panic("I/O Write - va%#x size %d data %#x\n", pkt->getAddr(), pkt->getSize(), pkt->get<uint8_t>());
|
||||
}
|
||||
|
||||
pkt->result = Packet::Success;
|
||||
pkt->makeAtomicResponse();
|
||||
return pioDelay;
|
||||
}
|
||||
|
||||
|
|
|
@ -71,7 +71,6 @@ TsunamiPChip::TsunamiPChip(Params *p)
|
|||
Tick
|
||||
TsunamiPChip::read(PacketPtr pkt)
|
||||
{
|
||||
assert(pkt->result == Packet::Unknown);
|
||||
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
|
||||
|
||||
pkt->allocate();
|
||||
|
@ -145,7 +144,7 @@ TsunamiPChip::read(PacketPtr pkt)
|
|||
default:
|
||||
panic("Default in PChip Read reached reading 0x%x\n", daddr);
|
||||
}
|
||||
pkt->result = Packet::Success;
|
||||
pkt->makeAtomicResponse();
|
||||
return pioDelay;
|
||||
|
||||
}
|
||||
|
@ -153,7 +152,6 @@ TsunamiPChip::read(PacketPtr pkt)
|
|||
Tick
|
||||
TsunamiPChip::write(PacketPtr pkt)
|
||||
{
|
||||
assert(pkt->result == Packet::Unknown);
|
||||
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
|
||||
Addr daddr = (pkt->getAddr() - pioAddr) >> 6;
|
||||
|
||||
|
@ -224,7 +222,7 @@ TsunamiPChip::write(PacketPtr pkt)
|
|||
|
||||
} // uint64_t
|
||||
|
||||
pkt->result = Packet::Success;
|
||||
pkt->makeAtomicResponse();
|
||||
return pioDelay;
|
||||
}
|
||||
|
||||
|
|
|
@ -271,7 +271,7 @@ IGbE::read(PacketPtr pkt)
|
|||
pkt->set<uint32_t>(0);
|
||||
};
|
||||
|
||||
pkt->result = Packet::Success;
|
||||
pkt->makeAtomicResponse();
|
||||
return pioDelay;
|
||||
}
|
||||
|
||||
|
@ -543,7 +543,7 @@ IGbE::write(PacketPtr pkt)
|
|||
panic("Write request to unknown register number: %#x\n", daddr);
|
||||
};
|
||||
|
||||
pkt->result = Packet::Success;
|
||||
pkt->makeAtomicResponse();
|
||||
return pioDelay;
|
||||
}
|
||||
|
||||
|
|
|
@ -295,7 +295,7 @@ IdeController::readConfig(PacketPtr pkt)
|
|||
default:
|
||||
panic("invalid access size(?) for PCI configspace!\n");
|
||||
}
|
||||
pkt->result = Packet::Success;
|
||||
pkt->makeAtomicResponse();
|
||||
return configDelay;
|
||||
|
||||
}
|
||||
|
@ -403,7 +403,7 @@ IdeController::writeConfig(PacketPtr pkt)
|
|||
bm_enabled = false;
|
||||
break;
|
||||
}
|
||||
pkt->result = Packet::Success;
|
||||
pkt->makeAtomicResponse();
|
||||
return configDelay;
|
||||
}
|
||||
|
||||
|
@ -423,7 +423,7 @@ IdeController::read(PacketPtr pkt)
|
|||
parseAddr(pkt->getAddr(), offset, channel, reg_type);
|
||||
|
||||
if (!io_enabled) {
|
||||
pkt->result = Packet::Success;
|
||||
pkt->makeAtomicResponse();
|
||||
return pioDelay;
|
||||
}
|
||||
|
||||
|
@ -490,7 +490,7 @@ IdeController::read(PacketPtr pkt)
|
|||
DPRINTF(IdeCtrl, "read from offset: %#x size: %#x data: %#x\n",
|
||||
offset, pkt->getSize(), pkt->get<uint32_t>());
|
||||
|
||||
pkt->result = Packet::Success;
|
||||
pkt->makeAtomicResponse();
|
||||
return pioDelay;
|
||||
}
|
||||
|
||||
|
@ -506,7 +506,7 @@ IdeController::write(PacketPtr pkt)
|
|||
parseAddr(pkt->getAddr(), offset, channel, reg_type);
|
||||
|
||||
if (!io_enabled) {
|
||||
pkt->result = Packet::Success;
|
||||
pkt->makeAtomicResponse();
|
||||
DPRINTF(IdeCtrl, "io not enabled\n");
|
||||
return pioDelay;
|
||||
}
|
||||
|
@ -514,7 +514,7 @@ IdeController::write(PacketPtr pkt)
|
|||
switch (reg_type) {
|
||||
case BMI_BLOCK:
|
||||
if (!bm_enabled) {
|
||||
pkt->result = Packet::Success;
|
||||
pkt->makeAtomicResponse();
|
||||
return pioDelay;
|
||||
}
|
||||
|
||||
|
@ -673,7 +673,7 @@ IdeController::write(PacketPtr pkt)
|
|||
offset, pkt->getSize(), pkt->get<uint32_t>());
|
||||
|
||||
|
||||
pkt->result = Packet::Success;
|
||||
pkt->makeAtomicResponse();
|
||||
return pioDelay;
|
||||
}
|
||||
|
||||
|
|
|
@ -100,9 +100,7 @@ DmaPort::DmaPort(DmaDevice *dev, System *s)
|
|||
bool
|
||||
DmaPort::recvTiming(PacketPtr pkt)
|
||||
{
|
||||
|
||||
|
||||
if (pkt->result == Packet::Nacked) {
|
||||
if (pkt->wasNacked()) {
|
||||
DPRINTF(DMA, "Received nacked Pkt %#x with State: %#x Addr: %#x\n",
|
||||
pkt, pkt->senderState, pkt->getAddr());
|
||||
|
||||
|
|
|
@ -56,7 +56,6 @@ IsaFake::IsaFake(Params *p)
|
|||
Tick
|
||||
IsaFake::read(PacketPtr pkt)
|
||||
{
|
||||
assert(pkt->result == Packet::Unknown);
|
||||
|
||||
if (params()->warnAccess != "")
|
||||
warn("Device %s accessed by read to address %#x size=%d\n",
|
||||
|
@ -64,7 +63,7 @@ IsaFake::read(PacketPtr pkt)
|
|||
if (params()->retBadAddr) {
|
||||
DPRINTF(Tsunami, "read to bad address va=%#x size=%d\n",
|
||||
pkt->getAddr(), pkt->getSize());
|
||||
pkt->result = Packet::BadAddress;
|
||||
pkt->setBadAddress();
|
||||
} else {
|
||||
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
|
||||
DPRINTF(Tsunami, "read va=%#x size=%d\n",
|
||||
|
@ -85,7 +84,7 @@ IsaFake::read(PacketPtr pkt)
|
|||
default:
|
||||
panic("invalid access size!\n");
|
||||
}
|
||||
pkt->result = Packet::Success;
|
||||
pkt->makeAtomicResponse();
|
||||
}
|
||||
return pioDelay;
|
||||
}
|
||||
|
@ -117,7 +116,7 @@ IsaFake::write(PacketPtr pkt)
|
|||
if (params()->retBadAddr) {
|
||||
DPRINTF(Tsunami, "write to bad address va=%#x size=%d \n",
|
||||
pkt->getAddr(), pkt->getSize());
|
||||
pkt->result = Packet::BadAddress;
|
||||
pkt->setBadAddress();
|
||||
} else {
|
||||
DPRINTF(Tsunami, "write - va=%#x size=%d \n",
|
||||
pkt->getAddr(), pkt->getSize());
|
||||
|
@ -140,7 +139,7 @@ IsaFake::write(PacketPtr pkt)
|
|||
panic("invalid access size!\n");
|
||||
}
|
||||
}
|
||||
pkt->result = Packet::Success;
|
||||
pkt->makeAtomicResponse();
|
||||
}
|
||||
return pioDelay;
|
||||
}
|
||||
|
|
|
@ -487,7 +487,7 @@ NSGigE::writeConfig(PacketPtr pkt)
|
|||
ioEnable = false;
|
||||
break;
|
||||
}
|
||||
pkt->result = Packet::Success;
|
||||
pkt->makeAtomicResponse();
|
||||
return configDelay;
|
||||
}
|
||||
|
||||
|
@ -519,7 +519,7 @@ NSGigE::read(PacketPtr pkt)
|
|||
// doesn't actually DEPEND upon their values
|
||||
// MIB are just hardware stats keepers
|
||||
pkt->set<uint32_t>(0);
|
||||
pkt->result = Packet::Success;
|
||||
pkt->makeAtomicResponse();
|
||||
return pioDelay;
|
||||
} else if (daddr > 0x3FC)
|
||||
panic("Something is messed up!\n");
|
||||
|
@ -715,7 +715,7 @@ NSGigE::read(PacketPtr pkt)
|
|||
DPRINTF(EthernetPIO, "read from %#x: data=%d data=%#x\n",
|
||||
daddr, reg, reg);
|
||||
|
||||
pkt->result = Packet::Success;
|
||||
pkt->makeAtomicResponse();
|
||||
return pioDelay;
|
||||
}
|
||||
|
||||
|
@ -1122,7 +1122,7 @@ NSGigE::write(PacketPtr pkt)
|
|||
} else {
|
||||
panic("Invalid Request Size");
|
||||
}
|
||||
pkt->result = Packet::Success;
|
||||
pkt->makeAtomicResponse();
|
||||
return pioDelay;
|
||||
}
|
||||
|
||||
|
|
|
@ -54,7 +54,6 @@ PciConfigAll::PciConfigAll(Params *p)
|
|||
Tick
|
||||
PciConfigAll::read(PacketPtr pkt)
|
||||
{
|
||||
assert(pkt->result == Packet::Unknown);
|
||||
|
||||
pkt->allocate();
|
||||
|
||||
|
@ -74,14 +73,13 @@ PciConfigAll::read(PacketPtr pkt)
|
|||
default:
|
||||
panic("invalid access size(?) for PCI configspace!\n");
|
||||
}
|
||||
pkt->result = Packet::Success;
|
||||
pkt->makeAtomicResponse();
|
||||
return params()->pio_delay;
|
||||
}
|
||||
|
||||
Tick
|
||||
PciConfigAll::write(PacketPtr pkt)
|
||||
{
|
||||
assert(pkt->result == Packet::Unknown);
|
||||
panic("Attempting to write to config space on non-existant device\n");
|
||||
M5_DUMMY_RETURN
|
||||
}
|
||||
|
|
|
@ -68,7 +68,6 @@ PciDev::PciConfigPort::PciConfigPort(PciDev *dev, int busid, int devid,
|
|||
Tick
|
||||
PciDev::PciConfigPort::recvAtomic(PacketPtr pkt)
|
||||
{
|
||||
assert(pkt->result == Packet::Unknown);
|
||||
assert(pkt->getAddr() >= configAddr &&
|
||||
pkt->getAddr() < configAddr + PCI_CONFIG_SIZE);
|
||||
return pkt->isRead() ? device->readConfig(pkt) : device->writeConfig(pkt);
|
||||
|
@ -156,7 +155,7 @@ PciDev::readConfig(PacketPtr pkt)
|
|||
default:
|
||||
panic("invalid access size(?) for PCI configspace!\n");
|
||||
}
|
||||
pkt->result = Packet::Success;
|
||||
pkt->makeAtomicResponse();
|
||||
return configDelay;
|
||||
|
||||
}
|
||||
|
@ -283,7 +282,7 @@ PciDev::writeConfig(PacketPtr pkt)
|
|||
default:
|
||||
panic("invalid access size(?) for PCI configspace!\n");
|
||||
}
|
||||
pkt->result = Packet::Success;
|
||||
pkt->makeAtomicResponse();
|
||||
return configDelay;
|
||||
|
||||
}
|
||||
|
|
|
@ -74,7 +74,6 @@ DumbTOD::DumbTOD(Params *p)
|
|||
Tick
|
||||
DumbTOD::read(PacketPtr pkt)
|
||||
{
|
||||
assert(pkt->result == Packet::Unknown);
|
||||
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
|
||||
assert(pkt->getSize() == 8);
|
||||
|
||||
|
@ -82,7 +81,7 @@ DumbTOD::read(PacketPtr pkt)
|
|||
pkt->set(todTime);
|
||||
todTime += 1000;
|
||||
|
||||
pkt->result = Packet::Success;
|
||||
pkt->makeAtomicResponse();
|
||||
return pioDelay;
|
||||
}
|
||||
|
||||
|
|
|
@ -72,7 +72,6 @@ Iob::Iob(Params *p)
|
|||
Tick
|
||||
Iob::read(PacketPtr pkt)
|
||||
{
|
||||
assert(pkt->result == Packet::Unknown);
|
||||
|
||||
if (pkt->getAddr() >= iobManAddr && pkt->getAddr() < iobManAddr + iobManSize)
|
||||
readIob(pkt);
|
||||
|
@ -81,7 +80,7 @@ Iob::read(PacketPtr pkt)
|
|||
else
|
||||
panic("Invalid address reached Iob\n");
|
||||
|
||||
pkt->result = Packet::Success;
|
||||
pkt->makeAtomicResponse();
|
||||
return pioDelay;
|
||||
}
|
||||
|
||||
|
@ -176,7 +175,7 @@ Iob::write(PacketPtr pkt)
|
|||
panic("Invalid address reached Iob\n");
|
||||
|
||||
|
||||
pkt->result = Packet::Success;
|
||||
pkt->makeAtomicResponse();
|
||||
return pioDelay;
|
||||
}
|
||||
|
||||
|
|
|
@ -61,7 +61,6 @@ MmDisk::read(PacketPtr pkt)
|
|||
uint32_t d32;
|
||||
uint64_t d64;
|
||||
|
||||
assert(pkt->result == Packet::Unknown);
|
||||
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
|
||||
accessAddr = pkt->getAddr() - pioAddr;
|
||||
|
||||
|
@ -101,7 +100,7 @@ MmDisk::read(PacketPtr pkt)
|
|||
panic("Invalid access size\n");
|
||||
}
|
||||
|
||||
pkt->result = Packet::Success;
|
||||
pkt->makeAtomicResponse();
|
||||
return pioDelay;
|
||||
}
|
||||
|
||||
|
@ -115,7 +114,6 @@ MmDisk::write(PacketPtr pkt)
|
|||
uint32_t d32;
|
||||
uint64_t d64;
|
||||
|
||||
assert(pkt->result == Packet::Unknown);
|
||||
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
|
||||
accessAddr = pkt->getAddr() - pioAddr;
|
||||
|
||||
|
@ -157,7 +155,7 @@ MmDisk::write(PacketPtr pkt)
|
|||
panic("Invalid access size\n");
|
||||
}
|
||||
|
||||
pkt->result = Packet::Success;
|
||||
pkt->makeAtomicResponse();
|
||||
return pioDelay;
|
||||
}
|
||||
|
||||
|
|
|
@ -111,7 +111,6 @@ Uart8250::Uart8250(Params *p)
|
|||
Tick
|
||||
Uart8250::read(PacketPtr pkt)
|
||||
{
|
||||
assert(pkt->result == Packet::Unknown);
|
||||
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
|
||||
assert(pkt->getSize() == 1);
|
||||
|
||||
|
@ -186,7 +185,7 @@ Uart8250::read(PacketPtr pkt)
|
|||
/* uint32_t d32 = *data;
|
||||
DPRINTF(Uart, "Register read to register %#x returned %#x\n", daddr, d32);
|
||||
*/
|
||||
pkt->result = Packet::Success;
|
||||
pkt->makeAtomicResponse();
|
||||
return pioDelay;
|
||||
}
|
||||
|
||||
|
@ -194,7 +193,6 @@ Tick
|
|||
Uart8250::write(PacketPtr pkt)
|
||||
{
|
||||
|
||||
assert(pkt->result == Packet::Unknown);
|
||||
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
|
||||
assert(pkt->getSize() == 1);
|
||||
|
||||
|
@ -272,7 +270,7 @@ Uart8250::write(PacketPtr pkt)
|
|||
panic("Tried to access a UART port that doesn't exist\n");
|
||||
break;
|
||||
}
|
||||
pkt->result = Packet::Success;
|
||||
pkt->makeAtomicResponse();
|
||||
return pioDelay;
|
||||
}
|
||||
|
||||
|
|
|
@ -121,14 +121,13 @@ Bridge::BridgePort::recvTiming(PacketPtr pkt)
|
|||
otherPort->sendQueue.size(), otherPort->queuedRequests,
|
||||
otherPort->outstandingResponses);
|
||||
|
||||
if (pkt->isRequest() && otherPort->reqQueueFull() && pkt->result !=
|
||||
Packet::Nacked) {
|
||||
if (pkt->isRequest() && otherPort->reqQueueFull() && !pkt->wasNacked()) {
|
||||
DPRINTF(BusBridge, "Remote queue full, nacking\n");
|
||||
nackRequest(pkt);
|
||||
return true;
|
||||
}
|
||||
|
||||
if (pkt->needsResponse() && pkt->result != Packet::Nacked)
|
||||
if (pkt->needsResponse() && !pkt->wasNacked())
|
||||
if (respQueueFull()) {
|
||||
DPRINTF(BusBridge, "Local queue full, no space for response, nacking\n");
|
||||
DPRINTF(BusBridge, "queue size: %d outreq: %d outstanding resp: %d\n",
|
||||
|
@ -149,7 +148,7 @@ void
|
|||
Bridge::BridgePort::nackRequest(PacketPtr pkt)
|
||||
{
|
||||
// Nack the packet
|
||||
pkt->result = Packet::Nacked;
|
||||
pkt->setNacked();
|
||||
pkt->setDest(pkt->getSrc());
|
||||
|
||||
//put it on the list to send
|
||||
|
@ -194,7 +193,7 @@ Bridge::BridgePort::nackRequest(PacketPtr pkt)
|
|||
void
|
||||
Bridge::BridgePort::queueForSendTiming(PacketPtr pkt)
|
||||
{
|
||||
if (pkt->isResponse() || pkt->result == Packet::Nacked) {
|
||||
if (pkt->isResponse() || pkt->wasNacked()) {
|
||||
// This is a response for a request we forwarded earlier. The
|
||||
// corresponding PacketBuffer should be stored in the packet's
|
||||
// senderState field.
|
||||
|
@ -206,7 +205,7 @@ Bridge::BridgePort::queueForSendTiming(PacketPtr pkt)
|
|||
|
||||
// Check if this packet was expecting a response and it's a nacked
|
||||
// packet, in which case we will never being seeing it
|
||||
if (buf->expectResponse && pkt->result == Packet::Nacked)
|
||||
if (buf->expectResponse && pkt->wasNacked())
|
||||
--outstandingResponses;
|
||||
|
||||
|
||||
|
@ -217,7 +216,7 @@ Bridge::BridgePort::queueForSendTiming(PacketPtr pkt)
|
|||
}
|
||||
|
||||
|
||||
if (pkt->isRequest() && pkt->result != Packet::Nacked) {
|
||||
if (pkt->isRequest() && !pkt->wasNacked()) {
|
||||
++queuedRequests;
|
||||
}
|
||||
|
||||
|
@ -251,7 +250,7 @@ Bridge::BridgePort::trySend()
|
|||
|
||||
// Ugly! @todo When multilevel coherence works this will be removed
|
||||
if (pkt->cmd == MemCmd::WriteInvalidateReq && fixPartialWrite &&
|
||||
pkt->result != Packet::Nacked) {
|
||||
!pkt->wasNacked()) {
|
||||
PacketPtr funcPkt = new Packet(pkt->req, MemCmd::WriteReq,
|
||||
Packet::Broadcast);
|
||||
funcPkt->dataStatic(pkt->getPtr<uint8_t>());
|
||||
|
@ -264,7 +263,7 @@ Bridge::BridgePort::trySend()
|
|||
buf->origSrc, pkt->getDest(), pkt->getAddr());
|
||||
|
||||
bool wasReq = pkt->isRequest();
|
||||
bool wasNacked = pkt->result == Packet::Nacked;
|
||||
bool wasNacked = pkt->wasNacked();
|
||||
|
||||
if (sendTiming(pkt)) {
|
||||
// send successful
|
||||
|
|
|
@ -86,7 +86,7 @@ class Bridge : public MemObject
|
|||
expectResponse(_pkt->needsResponse() && !nack)
|
||||
|
||||
{
|
||||
if (!pkt->isResponse() && !nack && pkt->result != Packet::Nacked)
|
||||
if (!pkt->isResponse() && !nack && !pkt->wasNacked())
|
||||
pkt->senderState = this;
|
||||
}
|
||||
|
||||
|
|
|
@ -173,9 +173,8 @@ bool
|
|||
Bus::recvTiming(PacketPtr pkt)
|
||||
{
|
||||
Port *port;
|
||||
DPRINTF(Bus, "recvTiming: packet src %d dest %d addr 0x%x cmd %s result %d\n",
|
||||
pkt->getSrc(), pkt->getDest(), pkt->getAddr(), pkt->cmdString(),
|
||||
pkt->result);
|
||||
DPRINTF(Bus, "recvTiming: packet src %d dest %d addr 0x%x cmd %s\n",
|
||||
pkt->getSrc(), pkt->getDest(), pkt->getAddr(), pkt->cmdString());
|
||||
|
||||
BusPort *pktPort;
|
||||
if (pkt->getSrc() == defaultId)
|
||||
|
@ -329,6 +328,8 @@ Bus::functionalSnoop(PacketPtr pkt, Port *responder)
|
|||
// id after each
|
||||
int src_id = pkt->getSrc();
|
||||
|
||||
assert(pkt->isRequest()); // hasn't already been satisfied
|
||||
|
||||
for (SnoopIter s_iter = snoopPorts.begin();
|
||||
s_iter != snoopPorts.end();
|
||||
s_iter++) {
|
||||
|
@ -336,7 +337,7 @@ Bus::functionalSnoop(PacketPtr pkt, Port *responder)
|
|||
if (p != responder && p->getId() != src_id) {
|
||||
p->sendFunctional(pkt);
|
||||
}
|
||||
if (pkt->result == Packet::Success) {
|
||||
if (pkt->isResponse()) {
|
||||
break;
|
||||
}
|
||||
pkt->setSrc(src_id);
|
||||
|
@ -369,14 +370,15 @@ Bus::recvAtomic(PacketPtr pkt)
|
|||
DPRINTF(Bus, "recvAtomic: packet src %d dest %d addr 0x%x cmd %s\n",
|
||||
pkt->getSrc(), pkt->getDest(), pkt->getAddr(), pkt->cmdString());
|
||||
assert(pkt->getDest() == Packet::Broadcast);
|
||||
assert(pkt->isRequest());
|
||||
|
||||
// Variables for recording original command and snoop response (if
|
||||
// any)... if a snooper respondes, we will need to restore
|
||||
// original command so that additional snoops can take place
|
||||
// properly
|
||||
MemCmd orig_cmd = pkt->cmd;
|
||||
Packet::Result response_result = Packet::Unknown;
|
||||
MemCmd response_cmd = MemCmd::InvalidCmd;
|
||||
int orig_src = pkt->getSrc();
|
||||
|
||||
Port *target_port = findPort(pkt->getAddr(), pkt->getSrc());
|
||||
|
||||
|
@ -387,20 +389,18 @@ Bus::recvAtomic(PacketPtr pkt)
|
|||
assert(p != target_port);
|
||||
if (p->getId() != pkt->getSrc()) {
|
||||
p->sendAtomic(pkt);
|
||||
if (pkt->result != Packet::Unknown) {
|
||||
if (pkt->isResponse()) {
|
||||
// response from snoop agent
|
||||
assert(pkt->cmd != orig_cmd);
|
||||
assert(pkt->memInhibitAsserted());
|
||||
assert(pkt->isResponse());
|
||||
// should only happen once
|
||||
assert(response_result == Packet::Unknown);
|
||||
assert(response_cmd == MemCmd::InvalidCmd);
|
||||
// save response state
|
||||
response_result = pkt->result;
|
||||
response_cmd = pkt->cmd;
|
||||
// restore original packet state for remaining snoopers
|
||||
pkt->cmd = orig_cmd;
|
||||
pkt->result = Packet::Unknown;
|
||||
pkt->setSrc(orig_src);
|
||||
pkt->setDest(Packet::Broadcast);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
@ -408,13 +408,11 @@ Bus::recvAtomic(PacketPtr pkt)
|
|||
Tick response_time = target_port->sendAtomic(pkt);
|
||||
|
||||
// if we got a response from a snooper, restore it here
|
||||
if (response_result != Packet::Unknown) {
|
||||
assert(response_cmd != MemCmd::InvalidCmd);
|
||||
if (response_cmd != MemCmd::InvalidCmd) {
|
||||
// no one else should have responded
|
||||
assert(pkt->result == Packet::Unknown);
|
||||
assert(!pkt->isResponse());
|
||||
assert(pkt->cmd == orig_cmd);
|
||||
pkt->cmd = response_cmd;
|
||||
pkt->result = response_result;
|
||||
}
|
||||
|
||||
// why do we have this packet field and the return value both???
|
||||
|
@ -434,8 +432,8 @@ Bus::recvFunctional(PacketPtr pkt)
|
|||
Port* port = findPort(pkt->getAddr(), pkt->getSrc());
|
||||
functionalSnoop(pkt, port ? port : interfaces[pkt->getSrc()]);
|
||||
|
||||
// If the snooping found what we were looking for, we're done.
|
||||
if (pkt->result != Packet::Success && port) {
|
||||
// If the snooping hasn't found what we were looking for, keep going.
|
||||
if (!pkt->isResponse() && port) {
|
||||
port->sendFunctional(pkt);
|
||||
}
|
||||
}
|
||||
|
|
2
src/mem/cache/base_cache.cc
vendored
2
src/mem/cache/base_cache.cc
vendored
|
@ -82,7 +82,7 @@ void
|
|||
BaseCache::CachePort::checkAndSendFunctional(PacketPtr pkt)
|
||||
{
|
||||
checkFunctional(pkt);
|
||||
if (pkt->result != Packet::Success)
|
||||
if (!pkt->isResponse())
|
||||
sendFunctional(pkt);
|
||||
}
|
||||
|
||||
|
|
12
src/mem/cache/cache_impl.hh
vendored
12
src/mem/cache/cache_impl.hh
vendored
|
@ -502,7 +502,6 @@ Cache<TagStore>::atomicAccess(PacketPtr pkt)
|
|||
|
||||
if (pkt->needsResponse()) {
|
||||
pkt->makeAtomicResponse();
|
||||
pkt->result = Packet::Success;
|
||||
}
|
||||
|
||||
return lat;
|
||||
|
@ -648,14 +647,13 @@ Cache<TagStore>::handleResponse(PacketPtr pkt)
|
|||
MSHR *mshr = dynamic_cast<MSHR*>(pkt->senderState);
|
||||
assert(mshr);
|
||||
|
||||
if (pkt->result == Packet::Nacked) {
|
||||
if (pkt->wasNacked()) {
|
||||
//pkt->reinitFromRequest();
|
||||
warn("NACKs from devices not connected to the same bus "
|
||||
"not implemented\n");
|
||||
return;
|
||||
}
|
||||
assert(pkt->result != Packet::BadAddress);
|
||||
assert(pkt->result == Packet::Success);
|
||||
assert(!pkt->isError());
|
||||
DPRINTF(Cache, "Handling response to %x\n", pkt->getAddr());
|
||||
|
||||
MSHRQueue *mq = mshr->queue;
|
||||
|
@ -1142,7 +1140,7 @@ void
|
|||
Cache<TagStore>::CpuSidePort::recvFunctional(PacketPtr pkt)
|
||||
{
|
||||
checkFunctional(pkt);
|
||||
if (pkt->result != Packet::Success)
|
||||
if (!pkt->isResponse())
|
||||
myCache()->functionalAccess(pkt, cache->memSidePort);
|
||||
}
|
||||
|
||||
|
@ -1180,7 +1178,7 @@ Cache<TagStore>::MemSidePort::recvTiming(PacketPtr pkt)
|
|||
// this needs to be fixed so that the cache updates the mshr and sends the
|
||||
// packet back out on the link, but it probably won't happen so until this
|
||||
// gets fixed, just panic when it does
|
||||
if (pkt->result == Packet::Nacked)
|
||||
if (pkt->wasNacked())
|
||||
panic("Need to implement cache resending nacked packets!\n");
|
||||
|
||||
if (pkt->isRequest() && blocked) {
|
||||
|
@ -1216,7 +1214,7 @@ void
|
|||
Cache<TagStore>::MemSidePort::recvFunctional(PacketPtr pkt)
|
||||
{
|
||||
checkFunctional(pkt);
|
||||
if (pkt->result != Packet::Success)
|
||||
if (!pkt->isResponse())
|
||||
myCache()->functionalAccess(pkt, cache->cpuSidePort);
|
||||
}
|
||||
|
||||
|
|
|
@ -115,7 +115,13 @@ MemCmd::commandInfo[] =
|
|||
SwapResp, "SwapReq" },
|
||||
/* SwapResp -- for Swap ldstub type operations */
|
||||
{ SET5(IsRead, IsWrite, NeedsExclusive, IsResponse, HasData),
|
||||
InvalidCmd, "SwapResp" }
|
||||
InvalidCmd, "SwapResp" },
|
||||
/* NetworkNackError -- nacked at network layer (not by protocol) */
|
||||
{ SET2(IsRequest, IsError), InvalidCmd, "NetworkNackError" },
|
||||
/* InvalidDestError -- packet dest field invalid */
|
||||
{ SET2(IsRequest, IsError), InvalidCmd, "InvalidDestError" },
|
||||
/* BadAddressError -- memory address invalid */
|
||||
{ SET2(IsRequest, IsError), InvalidCmd, "BadAddressError" }
|
||||
};
|
||||
|
||||
|
||||
|
@ -205,7 +211,7 @@ Packet::checkFunctional(Addr addr, int size, uint8_t *data)
|
|||
if (func_start >= val_start && func_end <= val_end) {
|
||||
allocate();
|
||||
std::memcpy(getPtr<uint8_t>(), data + offset, getSize());
|
||||
result = Packet::Success;
|
||||
makeResponse();
|
||||
return true;
|
||||
} else {
|
||||
// In this case the timing packet only partially satisfies
|
||||
|
@ -245,15 +251,6 @@ operator<<(std::ostream &o, const Packet &p)
|
|||
o << p.getAddr() + p.getSize() - 1 << "] ";
|
||||
o.unsetf(std::ios_base::hex| std::ios_base::showbase);
|
||||
|
||||
if (p.result == Packet::Success)
|
||||
o << "Successful ";
|
||||
if (p.result == Packet::BadAddress)
|
||||
o << "BadAddress ";
|
||||
if (p.result == Packet::Nacked)
|
||||
o << "Nacked ";
|
||||
if (p.result == Packet::Unknown)
|
||||
o << "Inflight ";
|
||||
|
||||
if (p.isRead())
|
||||
o << "Read ";
|
||||
if (p.isWrite())
|
||||
|
|
|
@ -84,6 +84,13 @@ class MemCmd
|
|||
StoreCondResp,
|
||||
SwapReq,
|
||||
SwapResp,
|
||||
// Error responses
|
||||
// @TODO these should be classified as responses rather than
|
||||
// requests; coding them as requests initially for backwards
|
||||
// compatibility
|
||||
NetworkNackError, // nacked at network layer (not by protocol)
|
||||
InvalidDestError, // packet dest field invalid
|
||||
BadAddressError, // memory address invalid
|
||||
NUM_MEM_CMDS
|
||||
};
|
||||
|
||||
|
@ -103,6 +110,7 @@ class MemCmd
|
|||
IsHWPrefetch,
|
||||
IsLocked, //!< Alpha/MIPS LL or SC access
|
||||
HasData, //!< There is an associated payload
|
||||
IsError, //!< Error response
|
||||
NUM_COMMAND_ATTRIBUTES
|
||||
};
|
||||
|
||||
|
@ -141,6 +149,7 @@ class MemCmd
|
|||
bool hasData() const { return testCmdAttrib(HasData); }
|
||||
bool isReadWrite() const { return isRead() && isWrite(); }
|
||||
bool isLocked() const { return testCmdAttrib(IsLocked); }
|
||||
bool isError() const { return testCmdAttrib(IsError); }
|
||||
|
||||
const Command responseCommand() const {
|
||||
return commandInfo[cmd].response;
|
||||
|
@ -184,6 +193,12 @@ class Packet : public FastAlloc
|
|||
|
||||
typedef MemCmd::Command Command;
|
||||
|
||||
/** The command field of the packet. */
|
||||
MemCmd cmd;
|
||||
|
||||
/** A pointer to the original request. */
|
||||
RequestPtr req;
|
||||
|
||||
private:
|
||||
/** A pointer to the data being transfered. It can be differnt
|
||||
* sizes at each level of the heirarchy so it belongs in the
|
||||
|
@ -223,19 +238,28 @@ class Packet : public FastAlloc
|
|||
* (unlike * addr, size, and src). */
|
||||
short dest;
|
||||
|
||||
/** The original value of the command field. Only valid when the
|
||||
* current command field is an error condition; in that case, the
|
||||
* previous contents of the command field are copied here. This
|
||||
* field is *not* set on non-error responses.
|
||||
*/
|
||||
MemCmd origCmd;
|
||||
|
||||
/** Are the 'addr' and 'size' fields valid? */
|
||||
bool addrSizeValid;
|
||||
/** Is the 'src' field valid? */
|
||||
bool srcValid;
|
||||
bool destValid;
|
||||
|
||||
enum SnoopFlag {
|
||||
enum Flag {
|
||||
// Snoop flags
|
||||
MemInhibit,
|
||||
Shared,
|
||||
NUM_SNOOP_FLAGS
|
||||
NUM_PACKET_FLAGS
|
||||
};
|
||||
|
||||
/** Coherence snoopFlags for snooping */
|
||||
std::bitset<NUM_SNOOP_FLAGS> snoopFlags;
|
||||
/** Status flags */
|
||||
std::bitset<NUM_PACKET_FLAGS> flags;
|
||||
|
||||
public:
|
||||
|
||||
|
@ -252,22 +276,6 @@ class Packet : public FastAlloc
|
|||
* should be routed based on its address. */
|
||||
static const short Broadcast = -1;
|
||||
|
||||
/** A pointer to the original request. */
|
||||
RequestPtr req;
|
||||
|
||||
/** A virtual base opaque structure used to hold coherence-related
|
||||
* state. A specific subclass would be derived from this to
|
||||
* carry state specific to a particular coherence protocol. */
|
||||
class CoherenceState : public FastAlloc {
|
||||
public:
|
||||
virtual ~CoherenceState() {}
|
||||
};
|
||||
|
||||
/** This packet's coherence state. Caches should use
|
||||
* dynamic_cast<> to cast to the state appropriate for the
|
||||
* system's coherence protocol. */
|
||||
CoherenceState *coherence;
|
||||
|
||||
/** A virtual base opaque structure used to hold state associated
|
||||
* with the packet but specific to the sending device (e.g., an
|
||||
* MSHR). A pointer to this state is returned in the packet's
|
||||
|
@ -284,11 +292,6 @@ class Packet : public FastAlloc
|
|||
* to cast to the state appropriate to the sender. */
|
||||
SenderState *senderState;
|
||||
|
||||
public:
|
||||
|
||||
/** The command field of the packet. */
|
||||
MemCmd cmd;
|
||||
|
||||
/** Return the string name of the cmd field (for debugging and
|
||||
* tracing). */
|
||||
const std::string &cmdString() const { return cmd.toString(); }
|
||||
|
@ -296,8 +299,6 @@ class Packet : public FastAlloc
|
|||
/** Return the index of this command. */
|
||||
inline int cmdToIndex() const { return cmd.toInt(); }
|
||||
|
||||
public:
|
||||
|
||||
bool isRead() const { return cmd.isRead(); }
|
||||
bool isWrite() const { return cmd.isWrite(); }
|
||||
bool isRequest() const { return cmd.isRequest(); }
|
||||
|
@ -308,26 +309,24 @@ class Packet : public FastAlloc
|
|||
bool hasData() const { return cmd.hasData(); }
|
||||
bool isReadWrite() const { return cmd.isReadWrite(); }
|
||||
bool isLocked() const { return cmd.isLocked(); }
|
||||
bool isError() const { return cmd.isError(); }
|
||||
|
||||
void assertMemInhibit() { snoopFlags[MemInhibit] = true; }
|
||||
void assertShared() { snoopFlags[Shared] = true; }
|
||||
bool memInhibitAsserted() { return snoopFlags[MemInhibit]; }
|
||||
bool sharedAsserted() { return snoopFlags[Shared]; }
|
||||
// Snoop flags
|
||||
void assertMemInhibit() { flags[MemInhibit] = true; }
|
||||
void assertShared() { flags[Shared] = true; }
|
||||
bool memInhibitAsserted() { return flags[MemInhibit]; }
|
||||
bool sharedAsserted() { return flags[Shared]; }
|
||||
|
||||
// Network error conditions... encapsulate them as methods since
|
||||
// their encoding keeps changing (from result field to command
|
||||
// field, etc.)
|
||||
void setNacked() { origCmd = cmd; cmd = MemCmd::NetworkNackError; }
|
||||
void setBadAddress() { origCmd = cmd; cmd = MemCmd::BadAddressError; }
|
||||
bool wasNacked() { return cmd == MemCmd::NetworkNackError; }
|
||||
bool hadBadAddress() { return cmd == MemCmd::BadAddressError; }
|
||||
|
||||
bool nic_pkt() { panic("Unimplemented"); M5_DUMMY_RETURN }
|
||||
|
||||
/** Possible results of a packet's request. */
|
||||
enum Result
|
||||
{
|
||||
Success,
|
||||
BadAddress,
|
||||
Nacked,
|
||||
Unknown
|
||||
};
|
||||
|
||||
/** The result of this packet's request. */
|
||||
Result result;
|
||||
|
||||
/** Accessor function that returns the source index of the packet. */
|
||||
short getSrc() const { assert(srcValid); return src; }
|
||||
void setSrc(short _src) { src = _src; srcValid = true; }
|
||||
|
@ -336,28 +335,23 @@ class Packet : public FastAlloc
|
|||
|
||||
/** Accessor function that returns the destination index of
|
||||
the packet. */
|
||||
short getDest() const { return dest; }
|
||||
void setDest(short _dest) { dest = _dest; }
|
||||
short getDest() const { assert(destValid); return dest; }
|
||||
void setDest(short _dest) { dest = _dest; destValid = true; }
|
||||
|
||||
Addr getAddr() const { assert(addrSizeValid); return addr; }
|
||||
int getSize() const { assert(addrSizeValid); return size; }
|
||||
Addr getOffset(int blkSize) const { return addr & (Addr)(blkSize - 1); }
|
||||
|
||||
void addrOverride(Addr newAddr) { assert(addrSizeValid); addr = newAddr; }
|
||||
void cmdOverride(MemCmd newCmd) { cmd = newCmd; }
|
||||
|
||||
/** Constructor. Note that a Request object must be constructed
|
||||
* first, but the Requests's physical address and size fields
|
||||
* need not be valid. The command and destination addresses
|
||||
* must be supplied. */
|
||||
Packet(Request *_req, MemCmd _cmd, short _dest)
|
||||
: data(NULL), staticData(false), dynamicData(false), arrayData(false),
|
||||
: cmd(_cmd), req(_req),
|
||||
data(NULL), staticData(false), dynamicData(false), arrayData(false),
|
||||
addr(_req->paddr), size(_req->size), dest(_dest),
|
||||
addrSizeValid(_req->validPaddr), srcValid(false),
|
||||
snoopFlags(0),
|
||||
time(curTick),
|
||||
req(_req), coherence(NULL), senderState(NULL), cmd(_cmd),
|
||||
result(Unknown)
|
||||
addrSizeValid(_req->validPaddr), srcValid(false), destValid(true),
|
||||
flags(0), time(curTick), senderState(NULL)
|
||||
{
|
||||
}
|
||||
|
||||
|
@ -365,13 +359,11 @@ class Packet : public FastAlloc
|
|||
* a request that is for a whole block, not the address from the req.
|
||||
* this allows for overriding the size/addr of the req.*/
|
||||
Packet(Request *_req, MemCmd _cmd, short _dest, int _blkSize)
|
||||
: data(NULL), staticData(false), dynamicData(false), arrayData(false),
|
||||
: cmd(_cmd), req(_req),
|
||||
data(NULL), staticData(false), dynamicData(false), arrayData(false),
|
||||
addr(_req->paddr & ~(_blkSize - 1)), size(_blkSize), dest(_dest),
|
||||
addrSizeValid(_req->validPaddr), srcValid(false),
|
||||
snoopFlags(0),
|
||||
time(curTick),
|
||||
req(_req), coherence(NULL), senderState(NULL), cmd(_cmd),
|
||||
result(Unknown)
|
||||
addrSizeValid(_req->validPaddr), srcValid(false), destValid(true),
|
||||
flags(0), time(curTick), senderState(NULL)
|
||||
{
|
||||
}
|
||||
|
||||
|
@ -382,15 +374,14 @@ class Packet : public FastAlloc
|
|||
* dynamic data, user must guarantee that the new packet's
|
||||
* lifetime is less than that of the original packet. */
|
||||
Packet(Packet *origPkt)
|
||||
: data(NULL), staticData(false), dynamicData(false), arrayData(false),
|
||||
: cmd(origPkt->cmd), req(origPkt->req),
|
||||
data(NULL), staticData(false), dynamicData(false), arrayData(false),
|
||||
addr(origPkt->addr), size(origPkt->size),
|
||||
src(origPkt->src), dest(origPkt->dest),
|
||||
addrSizeValid(origPkt->addrSizeValid), srcValid(origPkt->srcValid),
|
||||
snoopFlags(origPkt->snoopFlags),
|
||||
time(curTick),
|
||||
req(origPkt->req), coherence(origPkt->coherence),
|
||||
senderState(origPkt->senderState), cmd(origPkt->cmd),
|
||||
result(origPkt->result)
|
||||
addrSizeValid(origPkt->addrSizeValid),
|
||||
srcValid(origPkt->srcValid), destValid(origPkt->destValid),
|
||||
flags(origPkt->flags),
|
||||
time(curTick), senderState(origPkt->senderState)
|
||||
{
|
||||
}
|
||||
|
||||
|
@ -405,12 +396,11 @@ class Packet : public FastAlloc
|
|||
* multiple transactions. */
|
||||
void reinitFromRequest() {
|
||||
assert(req->validPaddr);
|
||||
snoopFlags = 0;
|
||||
flags = 0;
|
||||
addr = req->paddr;
|
||||
size = req->size;
|
||||
time = req->time;
|
||||
addrSizeValid = true;
|
||||
result = Unknown;
|
||||
if (dynamicData) {
|
||||
deleteData();
|
||||
dynamicData = false;
|
||||
|
@ -424,34 +414,24 @@ class Packet : public FastAlloc
|
|||
* destination fields are *not* modified, as is appropriate for
|
||||
* atomic accesses.
|
||||
*/
|
||||
void makeAtomicResponse()
|
||||
void makeResponse()
|
||||
{
|
||||
assert(needsResponse());
|
||||
assert(isRequest());
|
||||
assert(result == Unknown);
|
||||
cmd = cmd.responseCommand();
|
||||
result = Success;
|
||||
}
|
||||
|
||||
/**
|
||||
* Perform the additional work required for timing responses above
|
||||
* and beyond atomic responses; i.e., change the destination to
|
||||
* point back to the requester and clear the source field.
|
||||
*/
|
||||
void convertAtomicToTimingResponse()
|
||||
{
|
||||
dest = getSrc();
|
||||
dest = src;
|
||||
destValid = srcValid;
|
||||
srcValid = false;
|
||||
}
|
||||
|
||||
/**
|
||||
* Take a request packet and modify it in place to be suitable for
|
||||
* returning as a response to a timing request.
|
||||
*/
|
||||
void makeAtomicResponse()
|
||||
{
|
||||
makeResponse();
|
||||
}
|
||||
|
||||
void makeTimingResponse()
|
||||
{
|
||||
makeAtomicResponse();
|
||||
convertAtomicToTimingResponse();
|
||||
makeResponse();
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -462,9 +442,10 @@ class Packet : public FastAlloc
|
|||
void
|
||||
reinitNacked()
|
||||
{
|
||||
assert(needsResponse() && result == Nacked);
|
||||
dest = Broadcast;
|
||||
result = Unknown;
|
||||
assert(wasNacked());
|
||||
cmd = origCmd;
|
||||
assert(needsResponse());
|
||||
setDest(Broadcast);
|
||||
}
|
||||
|
||||
|
||||
|
|
|
@ -322,7 +322,7 @@ PhysicalMemory::doFunctionalAccess(PacketPtr pkt)
|
|||
pkt->cmdString());
|
||||
}
|
||||
|
||||
pkt->result = Packet::Success;
|
||||
pkt->makeAtomicResponse();
|
||||
}
|
||||
|
||||
|
||||
|
|
|
@ -58,12 +58,11 @@ void
|
|||
Port::blobHelper(Addr addr, uint8_t *p, int size, MemCmd cmd)
|
||||
{
|
||||
Request req;
|
||||
Packet pkt(&req, cmd, Packet::Broadcast);
|
||||
|
||||
for (ChunkGenerator gen(addr, size, peerBlockSize());
|
||||
!gen.done(); gen.next()) {
|
||||
req.setPhys(gen.addr(), gen.size(), 0);
|
||||
pkt.reinitFromRequest();
|
||||
Packet pkt(&req, cmd, Packet::Broadcast);
|
||||
pkt.dataStatic(p);
|
||||
sendFunctional(&pkt);
|
||||
p += gen.size();
|
||||
|
|
|
@ -55,7 +55,7 @@ SimpleTimingPort::recvFunctional(PacketPtr pkt)
|
|||
checkFunctional(pkt);
|
||||
|
||||
// Just do an atomic access and throw away the returned latency
|
||||
if (pkt->result != Packet::Success)
|
||||
if (!pkt->isResponse())
|
||||
recvAtomic(pkt);
|
||||
}
|
||||
|
||||
|
@ -68,7 +68,6 @@ SimpleTimingPort::recvTiming(PacketPtr pkt)
|
|||
// correctly with the drain code, so that would need to be fixed
|
||||
// if we ever added it back.
|
||||
assert(pkt->isRequest());
|
||||
assert(pkt->result == Packet::Unknown);
|
||||
|
||||
if (pkt->memInhibitAsserted()) {
|
||||
// snooper will supply based on copy of packet
|
||||
|
@ -85,7 +84,6 @@ SimpleTimingPort::recvTiming(PacketPtr pkt)
|
|||
// recvAtomic() should already have turned packet into
|
||||
// atomic response
|
||||
assert(pkt->isResponse());
|
||||
pkt->convertAtomicToTimingResponse();
|
||||
schedSendTiming(pkt, curTick + latency);
|
||||
} else {
|
||||
delete pkt->req;
|
||||
|
@ -138,12 +136,15 @@ void
|
|||
SimpleTimingPort::sendDeferredPacket()
|
||||
{
|
||||
assert(deferredPacketReady());
|
||||
bool success = sendTiming(transmitList.front().pkt);
|
||||
// take packet off list here; if recvTiming() on the other side
|
||||
// calls sendTiming() back on us (like SimpleTimingCpu does), then
|
||||
// we get confused by having a non-active packet on transmitList
|
||||
DeferredPacket dp = transmitList.front();
|
||||
transmitList.pop_front();
|
||||
bool success = sendTiming(dp.pkt);
|
||||
|
||||
if (success) {
|
||||
//send successful, remove packet
|
||||
transmitList.pop_front();
|
||||
if (!transmitList.empty()) {
|
||||
if (!transmitList.empty() && !sendEvent->scheduled()) {
|
||||
Tick time = transmitList.front().tick;
|
||||
sendEvent->schedule(time <= curTick ? curTick+1 : time);
|
||||
}
|
||||
|
@ -152,6 +153,12 @@ SimpleTimingPort::sendDeferredPacket()
|
|||
drainEvent->process();
|
||||
drainEvent = NULL;
|
||||
}
|
||||
} else {
|
||||
// Unsuccessful, need to put back on transmitList. Callee
|
||||
// should not have messed with it (since it didn't accept that
|
||||
// packet), so we can just push it back on the front.
|
||||
assert(!sendEvent->scheduled());
|
||||
transmitList.push_front(dp);
|
||||
}
|
||||
|
||||
waitingOnRetry = !success;
|
||||
|
|
Loading…
Reference in a new issue