Edit Fetch DPRINT in simple CPU
src/arch/mips/isa/formats/mt.isa: change copyright to 2006 src/cpu/simple/base.cc: Only DPRINT NNPC if we are not using ALPHA src/cpu/static_inst.hh: Take Out MIPS Specific functions ... --HG-- extra : convert_revision : 7a69e80cd1564fa3b778b9dade0e9fe3cef94e64
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@ -1,6 +1,6 @@
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// -*- mode:c++ -*-
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// Copyright (c) 2003-2006 The Regents of The University of Michigan
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// Copyright (c) 2006 The Regents of The University of Michigan
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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@ -35,14 +35,15 @@
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output header {{
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/**
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* Base class for integer operations.
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* Base class for MIPS MT ASE operations.
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*/
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class MT : public MipsStaticInst
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{
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protected:
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/// Constructor
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MT(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass)
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MT(const char *mnem, MachInst _machInst, OpClass __opClass) :
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MipsStaticInst(mnem, _machInst, __opClass)
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{
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}
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@ -26,6 +26,7 @@
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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* Korey Sewell
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*/
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#include "arch/utility.hh"
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@ -358,8 +359,13 @@ Fault
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BaseSimpleCPU::setupFetchRequest(Request *req)
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{
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// set up memory request for instruction fetch
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#if THE_ISA == ALPHA_ISA
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DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p",thread->readPC(),
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thread->readNextPC());
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#else
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DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",thread->readPC(),
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thread->readNextPC(),thread->readNextNPC());
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#endif
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req->setVirt(0, thread->readPC() & ~3, sizeof(MachInst),
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(FULL_SYSTEM && (thread->readPC() & 1)) ? PHYSICAL : 0,
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@ -34,6 +34,7 @@
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#include <bitset>
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#include <string>
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#include "base/bitfield.hh"
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#include "base/hashmap.hh"
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#include "base/misc.hh"
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#include "base/refcnt.hh"
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@ -411,16 +412,10 @@ class StaticInst : public StaticInstBase
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//This is defined as inline below.
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static StaticInstPtr decode(ExtMachInst mach_inst);
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//MIPS Decoder Debug Functions
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int getOpcode() { return (machInst & 0xFC000000) >> 26 ; }//31..26
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int getRs() { return (machInst & 0x03E00000) >> 21; } //25...21
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int getRt() { return (machInst & 0x001F0000) >> 16; } //20...16
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int getRd() { return (machInst & 0x0000F800) >> 11; } //15...11
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int getImm() { return (machInst & 0x0000FFFF); } //15...0
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int getFunction(){ return (machInst & 0x0000003F); }//5...0
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int getBranch(){ return (machInst & 0x0000FFFF); }//15...0
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int getJump(){ return (machInst & 0x03FFFFFF); }//5...0
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int getHint(){ return (machInst & 0x000007C0) >> 6; } //10...6
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/// Return opcode of machine instruction
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uint32_t getOpcode() { return bits(machInst, 31, 26);}
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/// Return name of machine instruction
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std::string getName() { return mnemonic; }
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};
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