ruby: split CPU and GPU latency stats
This commit is contained in:
David Hashe
parent
1a7d3f9fcb
commit
698866d461
5 changed files with 254 additions and 78 deletions
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@ -42,6 +42,8 @@
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----------------------------------------------------------------------
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*/
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#include "mem/ruby/profiler/Profiler.hh"
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#include <sys/types.h>
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#include <unistd.h>
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@ -54,7 +56,7 @@
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#include "mem/protocol/RubyRequest.hh"
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#include "mem/ruby/network/Network.hh"
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#include "mem/ruby/profiler/AddressProfiler.hh"
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#include "mem/ruby/profiler/Profiler.hh"
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#include "mem/ruby/system/GPUCoalescer.hh"
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#include "mem/ruby/system/Sequencer.hh"
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using namespace std;
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@ -106,131 +108,217 @@ Profiler::regStats(const std::string &pName)
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.flags(Stats::nozero | Stats::pdf | Stats::oneline);
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}
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m_outstandReqHist
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m_outstandReqHistSeqr
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.init(10)
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.name(pName + ".outstanding_req_hist")
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.name(pName + ".outstanding_req_hist_seqr")
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.desc("")
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.flags(Stats::nozero | Stats::pdf | Stats::oneline);
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m_latencyHist
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m_outstandReqHistCoalsr
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.init(10)
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.name(pName + ".latency_hist")
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.name(pName + ".outstanding_req_hist_coalsr")
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.desc("")
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.flags(Stats::nozero | Stats::pdf | Stats::oneline);
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m_hitLatencyHist
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m_latencyHistSeqr
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.init(10)
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.name(pName + ".hit_latency_hist")
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.name(pName + ".latency_hist_seqr")
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.desc("")
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.flags(Stats::nozero | Stats::pdf | Stats::oneline);
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m_missLatencyHist
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m_latencyHistCoalsr
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.init(10)
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.name(pName + ".miss_latency_hist")
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.name(pName + ".latency_hist_coalsr")
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.desc("")
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.flags(Stats::nozero | Stats::pdf | Stats::oneline);
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m_hitLatencyHistSeqr
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.init(10)
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.name(pName + ".hit_latency_hist_seqr")
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.desc("")
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.flags(Stats::nozero | Stats::pdf | Stats::oneline);
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m_missLatencyHistSeqr
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.init(10)
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.name(pName + ".miss_latency_hist_seqr")
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.desc("")
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.flags(Stats::nozero | Stats::pdf | Stats::oneline);
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m_missLatencyHistCoalsr
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.init(10)
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.name(pName + ".miss_latency_hist_coalsr")
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.desc("")
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.flags(Stats::nozero | Stats::pdf | Stats::oneline);
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for (int i = 0; i < RubyRequestType_NUM; i++) {
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m_typeLatencyHist.push_back(new Stats::Histogram());
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m_typeLatencyHist[i]
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m_typeLatencyHistSeqr.push_back(new Stats::Histogram());
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m_typeLatencyHistSeqr[i]
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->init(10)
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.name(pName + csprintf(".%s.latency_hist",
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.name(pName + csprintf(".%s.latency_hist_seqr",
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RubyRequestType(i)))
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.desc("")
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.flags(Stats::nozero | Stats::pdf | Stats::oneline);
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m_hitTypeLatencyHist.push_back(new Stats::Histogram());
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m_hitTypeLatencyHist[i]
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m_typeLatencyHistCoalsr.push_back(new Stats::Histogram());
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m_typeLatencyHistCoalsr[i]
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->init(10)
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.name(pName + csprintf(".%s.hit_latency_hist",
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.name(pName + csprintf(".%s.latency_hist_coalsr",
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RubyRequestType(i)))
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.desc("")
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.flags(Stats::nozero | Stats::pdf | Stats::oneline);
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m_missTypeLatencyHist.push_back(new Stats::Histogram());
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m_missTypeLatencyHist[i]
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m_hitTypeLatencyHistSeqr.push_back(new Stats::Histogram());
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m_hitTypeLatencyHistSeqr[i]
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->init(10)
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.name(pName + csprintf(".%s.miss_latency_hist",
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.name(pName + csprintf(".%s.hit_latency_hist_seqr",
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RubyRequestType(i)))
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.desc("")
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.flags(Stats::nozero | Stats::pdf | Stats::oneline);
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m_missTypeLatencyHistSeqr.push_back(new Stats::Histogram());
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m_missTypeLatencyHistSeqr[i]
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->init(10)
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.name(pName + csprintf(".%s.miss_latency_hist_seqr",
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RubyRequestType(i)))
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.desc("")
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.flags(Stats::nozero | Stats::pdf | Stats::oneline);
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m_missTypeLatencyHistCoalsr.push_back(new Stats::Histogram());
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m_missTypeLatencyHistCoalsr[i]
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->init(10)
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.name(pName + csprintf(".%s.miss_latency_hist_coalsr",
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RubyRequestType(i)))
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.desc("")
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.flags(Stats::nozero | Stats::pdf | Stats::oneline);
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}
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for (int i = 0; i < MachineType_NUM; i++) {
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m_hitMachLatencyHist.push_back(new Stats::Histogram());
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m_hitMachLatencyHist[i]
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m_hitMachLatencyHistSeqr.push_back(new Stats::Histogram());
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m_hitMachLatencyHistSeqr[i]
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->init(10)
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.name(pName + csprintf(".%s.hit_mach_latency_hist",
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.name(pName + csprintf(".%s.hit_mach_latency_hist_seqr",
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MachineType(i)))
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.desc("")
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.flags(Stats::nozero | Stats::pdf | Stats::oneline);
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m_missMachLatencyHist.push_back(new Stats::Histogram());
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m_missMachLatencyHist[i]
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m_missMachLatencyHistSeqr.push_back(new Stats::Histogram());
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m_missMachLatencyHistSeqr[i]
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->init(10)
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.name(pName + csprintf(".%s.miss_mach_latency_hist",
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.name(pName + csprintf(".%s.miss_mach_latency_hist_seqr",
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MachineType(i)))
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.desc("")
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.flags(Stats::nozero | Stats::pdf | Stats::oneline);
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m_IssueToInitialDelayHist.push_back(new Stats::Histogram());
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m_IssueToInitialDelayHist[i]
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m_missMachLatencyHistCoalsr.push_back(new Stats::Histogram());
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m_missMachLatencyHistCoalsr[i]
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->init(10)
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.name(pName + csprintf(".%s.miss_mach_latency_hist_coalsr",
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MachineType(i)))
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.desc("")
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.flags(Stats::nozero | Stats::pdf | Stats::oneline);
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m_IssueToInitialDelayHistSeqr.push_back(new Stats::Histogram());
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m_IssueToInitialDelayHistSeqr[i]
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->init(10)
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.name(pName + csprintf(
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".%s.miss_latency_hist.issue_to_initial_request",
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".%s.miss_latency_hist_seqr.issue_to_initial_request",
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MachineType(i)))
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.desc("")
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.flags(Stats::nozero | Stats::pdf | Stats::oneline);
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m_InitialToForwardDelayHist.push_back(new Stats::Histogram());
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m_InitialToForwardDelayHist[i]
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->init(10)
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.name(pName + csprintf(".%s.miss_latency_hist.initial_to_forward",
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MachineType(i)))
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.desc("")
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.flags(Stats::nozero | Stats::pdf | Stats::oneline);
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m_ForwardToFirstResponseDelayHist.push_back(new Stats::Histogram());
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m_ForwardToFirstResponseDelayHist[i]
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m_IssueToInitialDelayHistCoalsr.push_back(new Stats::Histogram());
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m_IssueToInitialDelayHistCoalsr[i]
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->init(10)
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.name(pName + csprintf(
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".%s.miss_latency_hist.forward_to_first_response",
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".%s.miss_latency_hist_coalsr.issue_to_initial_request",
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MachineType(i)))
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.desc("")
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.flags(Stats::nozero | Stats::pdf | Stats::oneline);
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m_FirstResponseToCompletionDelayHist.push_back(new Stats::Histogram());
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m_FirstResponseToCompletionDelayHist[i]
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m_InitialToForwardDelayHistSeqr.push_back(new Stats::Histogram());
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m_InitialToForwardDelayHistSeqr[i]
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->init(10)
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.name(pName + csprintf(".%s.miss_latency_hist_seqr.initial_to_forward",
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MachineType(i)))
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.desc("")
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.flags(Stats::nozero | Stats::pdf | Stats::oneline);
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m_InitialToForwardDelayHistCoalsr.push_back(new Stats::Histogram());
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m_InitialToForwardDelayHistCoalsr[i]
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->init(10)
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.name(pName + csprintf(".%s.miss_latency_hist_coalsr.initial_to_forward",
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MachineType(i)))
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.desc("")
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.flags(Stats::nozero | Stats::pdf | Stats::oneline);
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m_ForwardToFirstResponseDelayHistSeqr.push_back(new Stats::Histogram());
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m_ForwardToFirstResponseDelayHistSeqr[i]
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->init(10)
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.name(pName + csprintf(
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".%s.miss_latency_hist.first_response_to_completion",
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".%s.miss_latency_hist_seqr.forward_to_first_response",
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MachineType(i)))
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.desc("")
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.flags(Stats::nozero | Stats::pdf | Stats::oneline);
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m_IncompleteTimes[i]
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.name(pName + csprintf(".%s.incomplete_times", MachineType(i)))
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m_ForwardToFirstResponseDelayHistCoalsr.push_back(new Stats::Histogram());
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m_ForwardToFirstResponseDelayHistCoalsr[i]
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->init(10)
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.name(pName + csprintf(
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".%s.miss_latency_hist_coalsr.forward_to_first_response",
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MachineType(i)))
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.desc("")
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.flags(Stats::nozero | Stats::pdf | Stats::oneline);
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m_FirstResponseToCompletionDelayHistSeqr.push_back(new Stats::Histogram());
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m_FirstResponseToCompletionDelayHistSeqr[i]
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->init(10)
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.name(pName + csprintf(
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".%s.miss_latency_hist_seqr.first_response_to_completion",
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MachineType(i)))
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.desc("")
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.flags(Stats::nozero | Stats::pdf | Stats::oneline);
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m_FirstResponseToCompletionDelayHistCoalsr.push_back(new Stats::Histogram());
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m_FirstResponseToCompletionDelayHistCoalsr[i]
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->init(10)
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.name(pName + csprintf(
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".%s.miss_latency_hist_coalsr.first_response_to_completion",
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MachineType(i)))
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.desc("")
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.flags(Stats::nozero | Stats::pdf | Stats::oneline);
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m_IncompleteTimesSeqr[i]
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.name(pName + csprintf(".%s.incomplete_times_seqr", MachineType(i)))
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.desc("")
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.flags(Stats::nozero);
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}
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for (int i = 0; i < RubyRequestType_NUM; i++) {
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m_hitTypeMachLatencyHist.push_back(std::vector<Stats::Histogram *>());
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m_missTypeMachLatencyHist.push_back(std::vector<Stats::Histogram *>());
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m_hitTypeMachLatencyHistSeqr.push_back(std::vector<Stats::Histogram *>());
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m_missTypeMachLatencyHistSeqr.push_back(std::vector<Stats::Histogram *>());
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m_missTypeMachLatencyHistCoalsr.push_back(std::vector<Stats::Histogram *>());
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for (int j = 0; j < MachineType_NUM; j++) {
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m_hitTypeMachLatencyHist[i].push_back(new Stats::Histogram());
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m_hitTypeMachLatencyHist[i][j]
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m_hitTypeMachLatencyHistSeqr[i].push_back(new Stats::Histogram());
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m_hitTypeMachLatencyHistSeqr[i][j]
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->init(10)
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.name(pName + csprintf(".%s.%s.hit_type_mach_latency_hist",
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.name(pName + csprintf(".%s.%s.hit_type_mach_latency_hist_seqr",
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RubyRequestType(i), MachineType(j)))
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.desc("")
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.flags(Stats::nozero | Stats::pdf | Stats::oneline);
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m_missTypeMachLatencyHist[i].push_back(new Stats::Histogram());
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m_missTypeMachLatencyHist[i][j]
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m_missTypeMachLatencyHistSeqr[i].push_back(new Stats::Histogram());
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m_missTypeMachLatencyHistSeqr[i][j]
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->init(10)
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.name(pName + csprintf(".%s.%s.miss_type_mach_latency_hist",
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.name(pName + csprintf(".%s.%s.miss_type_mach_latency_hist_seqr",
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RubyRequestType(i), MachineType(j)))
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.desc("")
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.flags(Stats::nozero | Stats::pdf | Stats::oneline);
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m_missTypeMachLatencyHistCoalsr[i].push_back(new Stats::Histogram());
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m_missTypeMachLatencyHistCoalsr[i][j]
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->init(10)
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.name(pName + csprintf(".%s.%s.miss_type_mach_latency_hist_coalsr",
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RubyRequestType(i), MachineType(j)))
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.desc("")
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.flags(Stats::nozero | Stats::pdf | Stats::oneline);
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@ -271,7 +359,11 @@ Profiler::collateStats()
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AbstractController *ctr = (*it).second;
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Sequencer *seq = ctr->getCPUSequencer();
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if (seq != NULL) {
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m_outstandReqHist.add(seq->getOutstandReqHist());
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m_outstandReqHistSeqr.add(seq->getOutstandReqHist());
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}
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GPUCoalescer *coal = ctr->getGPUCoalescer();
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if (coal != NULL) {
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m_outstandReqHistCoalsr.add(coal->getOutstandReqHist());
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}
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}
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}
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@ -285,52 +377,93 @@ Profiler::collateStats()
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Sequencer *seq = ctr->getCPUSequencer();
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if (seq != NULL) {
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// add all the latencies
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m_latencyHist.add(seq->getLatencyHist());
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m_hitLatencyHist.add(seq->getHitLatencyHist());
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m_missLatencyHist.add(seq->getMissLatencyHist());
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m_latencyHistSeqr.add(seq->getLatencyHist());
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m_hitLatencyHistSeqr.add(seq->getHitLatencyHist());
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m_missLatencyHistSeqr.add(seq->getMissLatencyHist());
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// add the per request type latencies
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for (uint32_t j = 0; j < RubyRequestType_NUM; ++j) {
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m_typeLatencyHist[j]
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m_typeLatencyHistSeqr[j]
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->add(seq->getTypeLatencyHist(j));
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m_hitTypeLatencyHist[j]
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m_hitTypeLatencyHistSeqr[j]
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->add(seq->getHitTypeLatencyHist(j));
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m_missTypeLatencyHist[j]
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m_missTypeLatencyHistSeqr[j]
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->add(seq->getMissTypeLatencyHist(j));
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}
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// add the per machine type miss latencies
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for (uint32_t j = 0; j < MachineType_NUM; ++j) {
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m_hitMachLatencyHist[j]
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m_hitMachLatencyHistSeqr[j]
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->add(seq->getHitMachLatencyHist(j));
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m_missMachLatencyHist[j]
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m_missMachLatencyHistSeqr[j]
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->add(seq->getMissMachLatencyHist(j));
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m_IssueToInitialDelayHist[j]->add(
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m_IssueToInitialDelayHistSeqr[j]->add(
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seq->getIssueToInitialDelayHist(MachineType(j)));
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m_InitialToForwardDelayHist[j]->add(
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m_InitialToForwardDelayHistSeqr[j]->add(
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seq->getInitialToForwardDelayHist(MachineType(j)));
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m_ForwardToFirstResponseDelayHist[j]->add(seq->
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m_ForwardToFirstResponseDelayHistSeqr[j]->add(seq->
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getForwardRequestToFirstResponseHist(MachineType(j)));
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m_FirstResponseToCompletionDelayHist[j]->add(seq->
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m_FirstResponseToCompletionDelayHistSeqr[j]->add(seq->
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getFirstResponseToCompletionDelayHist(
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MachineType(j)));
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m_IncompleteTimes[j] +=
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m_IncompleteTimesSeqr[j] +=
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seq->getIncompleteTimes(MachineType(j));
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}
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// add the per (request, machine) type miss latencies
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for (uint32_t j = 0; j < RubyRequestType_NUM; j++) {
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for (uint32_t k = 0; k < MachineType_NUM; k++) {
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m_hitTypeMachLatencyHist[j][k]->add(
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m_hitTypeMachLatencyHistSeqr[j][k]->add(
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seq->getHitTypeMachLatencyHist(j,k));
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m_missTypeMachLatencyHist[j][k]->add(
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m_missTypeMachLatencyHistSeqr[j][k]->add(
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seq->getMissTypeMachLatencyHist(j,k));
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}
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}
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}
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GPUCoalescer *coal = ctr->getGPUCoalescer();
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if (coal != NULL) {
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// add all the latencies
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m_latencyHistCoalsr.add(coal->getLatencyHist());
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m_missLatencyHistCoalsr.add(coal->getMissLatencyHist());
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// add the per request type latencies
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for (uint32_t j = 0; j < RubyRequestType_NUM; ++j) {
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m_typeLatencyHistCoalsr[j]
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->add(coal->getTypeLatencyHist(j));
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m_missTypeLatencyHistCoalsr[j]
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->add(coal->getMissTypeLatencyHist(j));
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}
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// add the per machine type miss latencies
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for (uint32_t j = 0; j < MachineType_NUM; ++j) {
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m_missMachLatencyHistCoalsr[j]
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->add(coal->getMissMachLatencyHist(j));
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m_IssueToInitialDelayHistCoalsr[j]->add(
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coal->getIssueToInitialDelayHist(MachineType(j)));
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m_InitialToForwardDelayHistCoalsr[j]->add(
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coal->getInitialToForwardDelayHist(MachineType(j)));
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m_ForwardToFirstResponseDelayHistCoalsr[j]->add(coal->
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getForwardRequestToFirstResponseHist(MachineType(j)));
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m_FirstResponseToCompletionDelayHistCoalsr[j]->add(coal->
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getFirstResponseToCompletionDelayHist(
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MachineType(j)));
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}
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// add the per (request, machine) type miss latencies
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for (uint32_t j = 0; j < RubyRequestType_NUM; j++) {
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for (uint32_t k = 0; k < MachineType_NUM; k++) {
|
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m_missTypeMachLatencyHistCoalsr[j][k]->add(
|
||||
coal->getMissTypeMachLatencyHist(j,k));
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -94,38 +94,49 @@ class Profiler
|
|||
std::vector<Stats::Histogram *> delayVCHistogram;
|
||||
|
||||
//! Histogram for number of outstanding requests per cycle.
|
||||
Stats::Histogram m_outstandReqHist;
|
||||
Stats::Histogram m_outstandReqHistSeqr;
|
||||
Stats::Histogram m_outstandReqHistCoalsr;
|
||||
|
||||
//! Histogram for holding latency profile of all requests.
|
||||
Stats::Histogram m_latencyHist;
|
||||
std::vector<Stats::Histogram *> m_typeLatencyHist;
|
||||
Stats::Histogram m_latencyHistSeqr;
|
||||
Stats::Histogram m_latencyHistCoalsr;
|
||||
std::vector<Stats::Histogram *> m_typeLatencyHistSeqr;
|
||||
std::vector<Stats::Histogram *> m_typeLatencyHistCoalsr;
|
||||
|
||||
//! Histogram for holding latency profile of all requests that
|
||||
//! hit in the controller connected to this sequencer.
|
||||
Stats::Histogram m_hitLatencyHist;
|
||||
std::vector<Stats::Histogram *> m_hitTypeLatencyHist;
|
||||
Stats::Histogram m_hitLatencyHistSeqr;
|
||||
std::vector<Stats::Histogram *> m_hitTypeLatencyHistSeqr;
|
||||
|
||||
//! Histograms for profiling the latencies for requests that
|
||||
//! did not required external messages.
|
||||
std::vector<Stats::Histogram *> m_hitMachLatencyHist;
|
||||
std::vector< std::vector<Stats::Histogram *> > m_hitTypeMachLatencyHist;
|
||||
std::vector<Stats::Histogram *> m_hitMachLatencyHistSeqr;
|
||||
std::vector< std::vector<Stats::Histogram *> > m_hitTypeMachLatencyHistSeqr;
|
||||
|
||||
//! Histogram for holding latency profile of all requests that
|
||||
//! miss in the controller connected to this sequencer.
|
||||
Stats::Histogram m_missLatencyHist;
|
||||
std::vector<Stats::Histogram *> m_missTypeLatencyHist;
|
||||
Stats::Histogram m_missLatencyHistSeqr;
|
||||
Stats::Histogram m_missLatencyHistCoalsr;
|
||||
std::vector<Stats::Histogram *> m_missTypeLatencyHistSeqr;
|
||||
std::vector<Stats::Histogram *> m_missTypeLatencyHistCoalsr;
|
||||
|
||||
//! Histograms for profiling the latencies for requests that
|
||||
//! required external messages.
|
||||
std::vector<Stats::Histogram *> m_missMachLatencyHist;
|
||||
std::vector< std::vector<Stats::Histogram *> > m_missTypeMachLatencyHist;
|
||||
std::vector<Stats::Histogram *> m_missMachLatencyHistSeqr;
|
||||
std::vector< std::vector<Stats::Histogram *> > m_missTypeMachLatencyHistSeqr;
|
||||
std::vector<Stats::Histogram *> m_missMachLatencyHistCoalsr;
|
||||
std::vector< std::vector<Stats::Histogram *> > m_missTypeMachLatencyHistCoalsr;
|
||||
|
||||
//! Histograms for recording the breakdown of miss latency
|
||||
std::vector<Stats::Histogram *> m_IssueToInitialDelayHist;
|
||||
std::vector<Stats::Histogram *> m_InitialToForwardDelayHist;
|
||||
std::vector<Stats::Histogram *> m_ForwardToFirstResponseDelayHist;
|
||||
std::vector<Stats::Histogram *> m_FirstResponseToCompletionDelayHist;
|
||||
Stats::Scalar m_IncompleteTimes[MachineType_NUM];
|
||||
std::vector<Stats::Histogram *> m_IssueToInitialDelayHistSeqr;
|
||||
std::vector<Stats::Histogram *> m_InitialToForwardDelayHistSeqr;
|
||||
std::vector<Stats::Histogram *> m_ForwardToFirstResponseDelayHistSeqr;
|
||||
std::vector<Stats::Histogram *> m_FirstResponseToCompletionDelayHistSeqr;
|
||||
Stats::Scalar m_IncompleteTimesSeqr[MachineType_NUM];
|
||||
std::vector<Stats::Histogram *> m_IssueToInitialDelayHistCoalsr;
|
||||
std::vector<Stats::Histogram *> m_InitialToForwardDelayHistCoalsr;
|
||||
std::vector<Stats::Histogram *> m_ForwardToFirstResponseDelayHistCoalsr;
|
||||
std::vector<Stats::Histogram *> m_FirstResponseToCompletionDelayHistCoalsr;
|
||||
|
||||
//added by SS
|
||||
const bool m_hot_lines;
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@
|
|||
#include "mem/protocol/MemoryMsg.hh"
|
||||
#include "mem/ruby/system/RubySystem.hh"
|
||||
#include "mem/ruby/system/Sequencer.hh"
|
||||
#include "mem/ruby/system/GPUCoalescer.hh"
|
||||
#include "sim/system.hh"
|
||||
|
||||
AbstractController::AbstractController(const Params *p)
|
||||
|
|
|
|||
|
|
@ -49,6 +49,7 @@
|
|||
#include "mem/mem_object.hh"
|
||||
|
||||
class Network;
|
||||
class GPUCoalescer;
|
||||
|
||||
// used to communicate that an in_port peeked the wrong message type
|
||||
class RejectException: public std::exception
|
||||
|
|
@ -86,6 +87,7 @@ class AbstractController : public MemObject, public Consumer
|
|||
|
||||
virtual void recordCacheTrace(int cntrl, CacheRecorder* tr) = 0;
|
||||
virtual Sequencer* getCPUSequencer() const = 0;
|
||||
virtual GPUCoalescer* getGPUCoalescer() const = 0;
|
||||
|
||||
//! These functions are used by ruby system to read/write the data blocks
|
||||
//! that exist with in the controller.
|
||||
|
|
|
|||
|
|
@ -310,6 +310,7 @@ class $c_ident : public AbstractController
|
|||
|
||||
void recordCacheTrace(int cntrl, CacheRecorder* tr);
|
||||
Sequencer* getCPUSequencer() const;
|
||||
GPUCoalescer* getGPUCoalescer() const;
|
||||
|
||||
int functionalWriteBuffers(PacketPtr&);
|
||||
|
||||
|
|
@ -680,6 +681,12 @@ $c_ident::init()
|
|||
assert(param.pointer)
|
||||
seq_ident = "m_%s_ptr" % param.ident
|
||||
|
||||
coal_ident = "NULL"
|
||||
for param in self.config_parameters:
|
||||
if param.ident == "coalescer":
|
||||
assert(param.pointer)
|
||||
coal_ident = "m_%s_ptr" % param.ident
|
||||
|
||||
if seq_ident != "NULL":
|
||||
code('''
|
||||
Sequencer*
|
||||
|
|
@ -700,6 +707,28 @@ $c_ident::getCPUSequencer() const
|
|||
{
|
||||
return NULL;
|
||||
}
|
||||
''')
|
||||
|
||||
if coal_ident != "NULL":
|
||||
code('''
|
||||
GPUCoalescer*
|
||||
$c_ident::getGPUCoalescer() const
|
||||
{
|
||||
if (NULL != $coal_ident && !$coal_ident->isCPUSequencer()) {
|
||||
return $coal_ident;
|
||||
} else {
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
''')
|
||||
else:
|
||||
code('''
|
||||
|
||||
GPUCoalescer*
|
||||
$c_ident::getGPUCoalescer() const
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
''')
|
||||
|
||||
code('''
|
||||
|
|
|
|||
Loading…
Reference in a new issue